@inproceedings{6508, abstract = {{In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.}}, author = {{Kaufmann, Paul and Platzner, Marco}}, booktitle = {{Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}}, isbn = {{076952866X}}, keywords = {{integrated circuit design, hardware evolution, evolutionary hardware design, evolutionary optimizers, hash functions, preengineered circuits, Hardware, Circuits, Design optimization, Visualization, Genetic programming, Genetic mutations, Clustering algorithms, Biological cells, Field programmable gate arrays, Routing}}, location = {{Edinburgh, UK}}, pages = {{447--454}}, publisher = {{IEEE}}, title = {{{MOVES: A Modular Framework for Hardware Evolution}}}, doi = {{10.1109/ahs.2007.73}}, year = {{2007}}, } @inproceedings{9548, abstract = {{This paper presents a general model based on the electromechanical circuit theory. The model is set up as a mechanical equivalent model for base excited systems and describes the behaviour of a piezoelectric element around one resonance frequency which is sufficient for most practical applications. The model is extended to obtain the influence of geometrical and material properties. The derivated properties are used to describe the parameters of the general model which is easy to handle. Using this model either the calculation of the output power on a specific electric load or the determination of the design of the used piezoelectric element for a needed electric output power is possible. The paper focuses on the design of the ratio of length and width of a piezoelectric bimorph. The validity of the model is shown by the comparison of computed and experimental results.}}, author = {{Richter, Björn and Twiefel, Jens and Hemsel, Tobias and Wallaschek, Jörg}}, booktitle = {{ASME 2006 International Mechanical Engineering Congress and Exposition}}, keywords = {{Materials properties, Design, Generators}}, title = {{{Model based design of piezoelectric generators utilizing geometrical and material properties}}}, doi = {{doi:10.1115/IMECE2006-14862}}, year = {{2006}}, } @inproceedings{38107, abstract = {{TestML is an XML-based language for the exchange of test descriptions in automotive systems design and mainly introduced through the structural definition of an XML schema as an independent exchange format for existing tools and methods covering a wide range of different test technologies. In this paper, we present a rigorous formal behavioral semantics for TestML by means of Abstract State Machines (ASMs). Our semantics is a concise, unambiguous, high-level specification for TestML-based implementations and serves as a basis to define exact and well-defined mappings between existing test languages and TestML.}}, author = {{Großmann, Jürgen and Müller, Wolfgang}}, booktitle = {{Proc. of ISOLA 06}}, isbn = {{978-0-7695-3071-0}}, keywords = {{System testing, Software testing, Automotive engineering, Automatic testing, Machinery production industries, Protocols, Hardware design languages, Samarium, XML, Computer industry}}, location = {{Paphos, Cyprus}}, title = {{{A Formal Behavioral Semantics for TestML}}}, doi = {{10.1109/ISoLA.2006.37}}, year = {{2006}}, } @article{2412, abstract = {{ Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, journal = {{Microprocessors and Microsystems}}, keywords = {{FPGA, reconfigurable computing, co-simulation, Zippy}}, number = {{2-3}}, pages = {{63--73}}, publisher = {{Elsevier}}, title = {{{System-level performance evaluation of reconfigurable processors}}}, doi = {{10.1016/j.micpro.2004.06.004}}, volume = {{29}}, year = {{2005}}, } @inproceedings{39030, abstract = {{StateCharts are well accepted for embedded systems specification for various applications. However, for the specification of complex systems they have several limitations. In this article, we present a novel approach to efficiently execute an UML 2.0 subset for embedded real- time systems implementation with focus on hardware interrupts, software exceptions, and timeouts. We introduce a UML Virtual Machine, which directly executes sequence diagrams, which are embedded into hierarchically structured state transition diagrams. Whereas state diagrams are directly executed as Embedded State Machines (ESMs), sequence diagrams are translated into UVM Bytecode. The final UVM execution is performed by the interaction of the ESM and the Bytecode Interpreter. Due to our completely model- based approach, the UVM runtime kernel is easily adaptable and scalable to different scheduling and memory management strategies.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of ISNG 05}}, keywords = {{UML, Executable Models, Hardware/Software Co-design, Virtual Machine, Embedded Systems}}, title = {{{A UML Virtual Machine for Embedded Systems}}}, year = {{2005}}, } @inproceedings{39032, abstract = {{Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of VL/HCC 05}}, isbn = {{0-7695-2443-5}}, keywords = {{Unified modeling language, Software design, Virtual machining, Embedded system, Programming, Documentation, Hardware, Computer languages, Operating systems, Runtime}}, title = {{{Transformation of UML State Machines for Direct Execution}}}, doi = {{10.1109/VLHCC.2005.64}}, year = {{2005}}, } @inproceedings{39061, abstract = {{This article presents an approach, which combines theorem proving-based refinement with model checking for state based real-time systems. Our verification flow starts from UML state diagrams, which are translated to the formal B language and are model checked for real-time properties. By means of the B language and a B theorem prover, refined state diagrams are verified against their abstract representation. The approach is presented by means of the refinement of a digital echo cancellation unit.}}, author = {{Krupp, Alexander and Müller, Wolfgang and Oliver, Ian}}, booktitle = {{Proceedings of DATE’04 Designers' Forum}}, isbn = {{0-7695-2085-5}}, keywords = {{Echo cancellers, Logic, Unified modeling language, Automata, Data structures, Boolean functions, Electronic design automation and methodology, Prototypes, Specification languages, Constraint theory}}, title = {{{Formal Refinement and Model Checking of An Echo Cancellation Unit}}}, doi = {{10.1109/DATE.2004.1269214}}, year = {{2004}}, } @inproceedings{2422, abstract = {{Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.}}, author = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}}, booktitle = {{Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}}, isbn = {{1-932415-05-X}}, keywords = {{Zippy, co-simulation}}, pages = {{174--180}}, publisher = {{CSREA Press}}, title = {{{Co-simulation of a Hybrid Multi-Context Architecture}}}, year = {{2003}}, } @inproceedings{39411, abstract = {{Rapid prototyping based on 3D models is well accepted for several applications. This article addresses the application of animated virtual 3D prototypes for the development of computer-based systems supporting early collaboration of the system designer with the external customer. Our methodology seamlessly integrates illustration through 3D animation with the main tasks of computer-based real-time systems development, i.e., implementation and verification. The approach is outlined by the example of the design of a flexible manufacturing system.}}, author = {{Flake, Stephan and Geiger, Christian and Müller, Wolfgang and Ruf, Jürgen}}, booktitle = {{Proceedings of IEEE KMN 2001}}, isbn = {{0-7695-1269-0}}, keywords = {{Virtual prototyping, Animation, Collaboration, System analysis and design, Feedback, Application software, Power system modeling, Handicapped aids, Process design, Contracts}}, title = {{{Customer-Oriented Systems Design through Virtual Prototyps}}}, doi = {{10.1109/ENABL.2001.953425}}, year = {{2001}}, } @inproceedings{39421, abstract = {{We present a rigorous but transparent semantics definition of SystemC that covers method, thread, and clocked thread behavior as well as their interaction with the simulation kernel process. The semantics includes watching statements, signal assignment, and wait statements as they are introduced in SystemC V1.O. We present our definition in form of distributed Abstract State Machines (ASMs) rules reflecting the view given in the SystemC User's Manual and the reference implementation. We mainly see our formal semantics as a concise, unambiguous, high-level specification for SystemC-based implementations and for standardization. Additionally, it can be used as a sound basis to investigate SystemC interoperability with Verilog and VHDL.}}, author = {{Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W. and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}}, booktitle = {{Proceedings of the Design, Automation, and Test in Europe (DATE’01)}}, isbn = {{0-7695-0993-2}}, keywords = {{Yarn, Formal verification, Kernel, Hardware design languages, Electronic design automation and methodology, Algebra, Computational modeling, Logic functions, Computer languages, Clocks}}, publisher = {{IEEE}}, title = {{{The Simulation Semantics of SystemC}}}, doi = {{10.1109/DATE.2001.915002}}, year = {{2001}}, } @misc{2433, author = {{Plessl, Christian and Maurer, Simon}}, keywords = {{co-design, speech processing}}, publisher = {{Computer Engineering and Networks Lab, ETH Zurich, Switzerland}}, title = {{{Hardware/Software Codesign in Speech Compression Applications}}}, year = {{2000}}, } @inproceedings{39487, abstract = {{This article introduces and discusses different innovative means for visual specification and animation of complex concurrent systems. It introduces the completely visual programming language Pictorial Janus (PJ) and its application in the customer-oriented design process. PJ implements a completely visual programming language with inherent animation facilities. The article outlines the transformation of purely visual PJ programs into textual imperative programming languages. The second part of the article investigates animated 3D-presentations and introduces a novel approach to an animated 3D programming language for interactive customer-oriented illustrations.}}, author = {{Geiger, Christian and Lehrenfeld, G. and Müller, Wolfgang}}, booktitle = {{Proceedings of HICSS-32}}, isbn = {{0-7695-0001-3}}, keywords = {{Animation, Computer languages, Object oriented modeling, Collaboration, Process design, Graphical user interfaces, Jacobian matrices, Standardization, Feedback, Software prototyping}}, location = {{Maui, Hawaii}}, title = {{{Visual Specification, Modeling, and Illustrations of Complex Systems}}}, doi = {{10.1109/HICSS.1999.772621}}, year = {{1999}}, }