---
_id: '6508'
abstract:
- lang: eng
text: 'In this paper, we present a framework that supports experimenting with evolutionary
hardware design. We describe the framework''s modules for composing evolutionary
optimizers and for setting up, controlling, and analyzing experiments. Two case
studies demonstrate the usefulness of the framework: evolution of hash functions
and evolution based on pre-engineered circuits.'
author:
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution.
In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007).
IEEE; 2007:447-454. doi:10.1109/ahs.2007.73'
apa: 'Kaufmann, P., & Platzner, M. (2007). MOVES: A Modular Framework for Hardware
Evolution. In Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS
2007) (pp. 447–454). Edinburgh, UK: IEEE. https://doi.org/10.1109/ahs.2007.73'
bibtex: '@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework
for Hardware Evolution}, DOI={10.1109/ahs.2007.73},
booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)},
publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454}
}'
chicago: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware
Evolution.” In Second NASA/ESA Conference on Adaptive Hardware and Systems
(AHS 2007), 447–54. IEEE, 2007. https://doi.org/10.1109/ahs.2007.73.'
ieee: 'P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,”
in Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007),
Edinburgh, UK, 2007, pp. 447–454.'
mla: 'Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware
Evolution.” Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS
2007), IEEE, 2007, pp. 447–54, doi:10.1109/ahs.2007.73.'
short: 'P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware
and Systems (AHS 2007), IEEE, 2007, pp. 447–454.'
conference:
end_date: 2007-08-08
location: Edinburgh, UK
name: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
start_date: 2007-08-05
date_created: 2019-01-08T09:52:43Z
date_updated: 2022-01-06T07:03:08Z
department:
- _id: '78'
doi: 10.1109/ahs.2007.73
keyword:
- integrated circuit design
- hardware evolution
- evolutionary hardware design
- evolutionary optimizers
- hash functions
- preengineered circuits
- Hardware
- Circuits
- Design optimization
- Visualization
- Genetic programming
- Genetic mutations
- Clustering algorithms
- Biological cells
- Field programmable gate arrays
- Routing
language:
- iso: eng
page: 447-454
publication: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)
publication_identifier:
isbn:
- 076952866X
- '9780769528663'
publication_status: published
publisher: IEEE
status: public
title: 'MOVES: A Modular Framework for Hardware Evolution'
type: conference
user_id: '3118'
year: '2007'
...
---
_id: '9548'
abstract:
- lang: eng
text: This paper presents a general model based on the electromechanical circuit
theory. The model is set up as a mechanical equivalent model for base excited
systems and describes the behaviour of a piezoelectric element around one resonance
frequency which is sufficient for most practical applications. The model is extended
to obtain the influence of geometrical and material properties. The derivated
properties are used to describe the parameters of the general model which is easy
to handle. Using this model either the calculation of the output power on a specific
electric load or the determination of the design of the used piezoelectric element
for a needed electric output power is possible. The paper focuses on the design
of the ratio of length and width of a piezoelectric bimorph. The validity of the
model is shown by the comparison of computed and experimental results.
author:
- first_name: Björn
full_name: Richter, Björn
last_name: Richter
- first_name: Jens
full_name: Twiefel, Jens
last_name: Twiefel
- first_name: Tobias
full_name: Hemsel, Tobias
id: '210'
last_name: Hemsel
- first_name: Jörg
full_name: Wallaschek, Jörg
last_name: Wallaschek
citation:
ama: 'Richter B, Twiefel J, Hemsel T, Wallaschek J. Model based design of piezoelectric
generators utilizing geometrical and material properties. In: ASME 2006 International
Mechanical Engineering Congress and Exposition. Chicago, Illinois, USA; 2006.
doi:doi:10.1115/IMECE2006-14862'
apa: Richter, B., Twiefel, J., Hemsel, T., & Wallaschek, J. (2006). Model based
design of piezoelectric generators utilizing geometrical and material properties.
In ASME 2006 International Mechanical Engineering Congress and Exposition.
Chicago, Illinois, USA. https://doi.org/doi:10.1115/IMECE2006-14862
bibtex: '@inproceedings{Richter_Twiefel_Hemsel_Wallaschek_2006, place={Chicago,
Illinois, USA}, title={Model based design of piezoelectric generators utilizing
geometrical and material properties}, DOI={doi:10.1115/IMECE2006-14862},
booktitle={ASME 2006 International Mechanical Engineering Congress and Exposition},
author={Richter, Björn and Twiefel, Jens and Hemsel, Tobias and Wallaschek, Jörg},
year={2006} }'
chicago: Richter, Björn, Jens Twiefel, Tobias Hemsel, and Jörg Wallaschek. “Model
Based Design of Piezoelectric Generators Utilizing Geometrical and Material Properties.”
In ASME 2006 International Mechanical Engineering Congress and Exposition.
Chicago, Illinois, USA, 2006. https://doi.org/doi:10.1115/IMECE2006-14862.
ieee: B. Richter, J. Twiefel, T. Hemsel, and J. Wallaschek, “Model based design
of piezoelectric generators utilizing geometrical and material properties,” in
ASME 2006 International Mechanical Engineering Congress and Exposition,
2006.
mla: Richter, Björn, et al. “Model Based Design of Piezoelectric Generators Utilizing
Geometrical and Material Properties.” ASME 2006 International Mechanical Engineering
Congress and Exposition, 2006, doi:doi:10.1115/IMECE2006-14862.
short: 'B. Richter, J. Twiefel, T. Hemsel, J. Wallaschek, in: ASME 2006 International
Mechanical Engineering Congress and Exposition, Chicago, Illinois, USA, 2006.'
date_created: 2019-04-29T09:37:45Z
date_updated: 2022-01-06T07:04:16Z
department:
- _id: '151'
doi: doi:10.1115/IMECE2006-14862
keyword:
- Materials properties
- Design
- Generators
language:
- iso: eng
place: Chicago, Illinois, USA
publication: ASME 2006 International Mechanical Engineering Congress and Exposition
quality_controlled: '1'
status: public
title: Model based design of piezoelectric generators utilizing geometrical and material
properties
type: conference
user_id: '55222'
year: '2006'
...
---
_id: '38107'
abstract:
- lang: eng
text: TestML is an XML-based language for the exchange of test descriptions in automotive
systems design and mainly introduced through the structural definition of an XML
schema as an independent exchange format for existing tools and methods covering
a wide range of different test technologies. In this paper, we present a rigorous
formal behavioral semantics for TestML by means of Abstract State Machines (ASMs).
Our semantics is a concise, unambiguous, high-level specification for TestML-based
implementations and serves as a basis to define exact and well-defined mappings
between existing test languages and TestML.
author:
- first_name: Jürgen
full_name: Großmann, Jürgen
last_name: Großmann
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Großmann J, Müller W. A Formal Behavioral Semantics for TestML. In: Proc.
of ISOLA 06. ; 2006. doi:10.1109/ISoLA.2006.37'
apa: Großmann, J., & Müller, W. (2006). A Formal Behavioral Semantics for TestML.
Proc. of ISOLA 06. https://doi.org/10.1109/ISoLA.2006.37
bibtex: '@inproceedings{Großmann_Müller_2006, place={Paphos, Cyprus}, title={A Formal
Behavioral Semantics for TestML}, DOI={10.1109/ISoLA.2006.37},
booktitle={Proc. of ISOLA 06}, author={Großmann, Jürgen and Müller, Wolfgang},
year={2006} }'
chicago: Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for
TestML.” In Proc. of ISOLA 06. Paphos, Cyprus, 2006. https://doi.org/10.1109/ISoLA.2006.37.
ieee: 'J. Großmann and W. Müller, “A Formal Behavioral Semantics for TestML,” Paphos,
Cyprus, 2006, doi: 10.1109/ISoLA.2006.37.'
mla: Großmann, Jürgen, and Wolfgang Müller. “A Formal Behavioral Semantics for TestML.”
Proc. of ISOLA 06, 2006, doi:10.1109/ISoLA.2006.37.
short: 'J. Großmann, W. Müller, in: Proc. of ISOLA 06, Paphos, Cyprus, 2006.'
conference:
location: Paphos, Cyprus
date_created: 2023-01-23T12:00:06Z
date_updated: 2023-01-23T12:06:26Z
department:
- _id: '672'
doi: 10.1109/ISoLA.2006.37
keyword:
- System testing
- Software testing
- Automotive engineering
- Automatic testing
- Machinery production industries
- Protocols
- Hardware design languages
- Samarium
- XML
- Computer industry
language:
- iso: eng
place: Paphos, Cyprus
publication: Proc. of ISOLA 06
publication_identifier:
isbn:
- 978-0-7695-3071-0
status: public
title: A Formal Behavioral Semantics for TestML
type: conference
user_id: '5786'
year: '2006'
...
---
_id: '2412'
abstract:
- lang: eng
text: ' Reconfigurable architectures that tightly integrate a standard CPU core
with a field-programmable hardware structure have recently been receiving impact
of these design decisions on the overall system performance is a challenging task.
In this paper, we first present a framework for the cycle-accurate performance
evaluation of hybrid reconfigurable processors on the system level. Then, we discuss
a reconfigurable processor for data-streaming applications, which attaches a coarse-grained
reconfigurable unit to the coprocessor interface of a standard embedded CPU core.
By means of a case study we evaluate the system-level impact of certain design
features for the reconfigurable unit, such as multiple contexts, register replication,
and hardware context scheduling. The results illustrate that a system-level evaluation
framework is of paramount importance for studying the architectural trade-offs
and optimizing design parameters for reconfigurable processors.'
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable
processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004
apa: Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance
evaluation of reconfigurable processors. Microprocessors and Microsystems,
29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004
bibtex: '@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation
of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004},
number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005},
pages={63–73} }'
chicago: 'Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance
Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems
29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004.'
ieee: R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation
of reconfigurable processors,” Microprocessors and Microsystems, vol. 29,
no. 2–3, pp. 63–73, 2005.
mla: Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable
Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier,
2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.
short: R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005)
63–73.
date_created: 2018-04-17T14:36:10Z
date_updated: 2022-01-06T06:56:07Z
department:
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2004.06.004
intvolume: ' 29'
issue: 2-3
keyword:
- FPGA
- reconfigurable computing
- co-simulation
- Zippy
page: 63-73
publication: Microprocessors and Microsystems
publisher: Elsevier
status: public
title: System-level performance evaluation of reconfigurable processors
type: journal_article
user_id: '24135'
volume: 29
year: '2005'
...
---
_id: '39030'
abstract:
- lang: eng
text: "StateCharts are well accepted for embedded systems\r\nspecification for various
applications. However, for the\r\nspecification of complex systems they have several\r\nlimitations.
In this article, we present a novel approach to\r\nefficiently execute an UML
2.0 subset for embedded real-\r\ntime systems implementation with focus on hardware\r\ninterrupts,
software exceptions, and timeouts. We\r\nintroduce a UML Virtual Machine, which
directly\r\nexecutes sequence diagrams, which are embedded into\r\nhierarchically
structured state transition diagrams.\r\nWhereas state diagrams are directly executed
as\r\nEmbedded State Machines (ESMs), sequence diagrams\r\nare translated into
UVM Bytecode. The final UVM\r\nexecution is performed by the interaction of the
ESM and\r\nthe Bytecode Interpreter. Due to our completely model-\r\nbased approach,
the UVM runtime kernel is easily\r\nadaptable and scalable to different scheduling
and\r\nmemory management strategies."
author:
- first_name: Tim
full_name: Schattkowsky, Tim
last_name: Schattkowsky
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Schattkowsky T, Müller W. A UML Virtual Machine for Embedded Systems. In:
Proceedings of ISNG 05. ; 2005.'
apa: Schattkowsky, T., & Müller, W. (2005). A UML Virtual Machine for Embedded
Systems. Proceedings of ISNG 05.
bibtex: '@inproceedings{Schattkowsky_Müller_2005, place={Las Vegas, NV}, title={A
UML Virtual Machine for Embedded Systems}, booktitle={Proceedings of ISNG 05},
author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }'
chicago: Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded
Systems.” In Proceedings of ISNG 05. Las Vegas, NV, 2005.
ieee: T. Schattkowsky and W. Müller, “A UML Virtual Machine for Embedded Systems,”
2005.
mla: Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded
Systems.” Proceedings of ISNG 05, 2005.
short: 'T. Schattkowsky, W. Müller, in: Proceedings of ISNG 05, Las Vegas, NV, 2005.'
date_created: 2023-01-24T08:12:20Z
date_updated: 2023-01-24T08:12:26Z
department:
- _id: '672'
keyword:
- UML
- Executable Models
- Hardware/Software Co-design
- Virtual Machine
- Embedded Systems
language:
- iso: eng
place: Las Vegas, NV
publication: Proceedings of ISNG 05
status: public
title: A UML Virtual Machine for Embedded Systems
type: conference
user_id: '5786'
year: '2005'
...
---
_id: '39032'
abstract:
- lang: eng
text: Executable UML models are nowadays gaining interest in embedded systems design.
This domain is strongly devoted to the modeling of reactive behavior using StateChart
variants. In this context, the direct execution of UML state machines is an interesting
alternative to native code generation approaches since it significantly increases
portability. However, fully featured UML 2.0 State Machines may contain a broad
set of features with complex execution semantics that differ significantly from
other StateChart variants. This makes their direct execution complex and inefficient.
In this paper, we demonstrate how such state machines can be represented using
a small subset of the UML state machine features that enables efficient execution.
We describe the necessary model transformations in terms of graph transformations
and discuss the underlying semantics and implications for execution.
author:
- first_name: Tim
full_name: Schattkowsky, Tim
last_name: Schattkowsky
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Schattkowsky T, Müller W. Transformation of UML State Machines for Direct
Execution. In: Proceedings of VL/HCC 05. ; 2005. doi:10.1109/VLHCC.2005.64'
apa: Schattkowsky, T., & Müller, W. (2005). Transformation of UML State Machines
for Direct Execution. Proceedings of VL/HCC 05. https://doi.org/10.1109/VLHCC.2005.64
bibtex: '@inproceedings{Schattkowsky_Müller_2005, place={Dallas, TX, USA}, title={Transformation
of UML State Machines for Direct Execution}, DOI={10.1109/VLHCC.2005.64},
booktitle={Proceedings of VL/HCC 05}, author={Schattkowsky, Tim and Müller, Wolfgang},
year={2005} }'
chicago: Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines
for Direct Execution.” In Proceedings of VL/HCC 05. Dallas, TX, USA, 2005.
https://doi.org/10.1109/VLHCC.2005.64.
ieee: 'T. Schattkowsky and W. Müller, “Transformation of UML State Machines for
Direct Execution,” 2005, doi: 10.1109/VLHCC.2005.64.'
mla: Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines
for Direct Execution.” Proceedings of VL/HCC 05, 2005, doi:10.1109/VLHCC.2005.64.
short: 'T. Schattkowsky, W. Müller, in: Proceedings of VL/HCC 05, Dallas, TX, USA,
2005.'
date_created: 2023-01-24T08:18:10Z
date_updated: 2023-01-24T08:18:27Z
department:
- _id: '672'
doi: 10.1109/VLHCC.2005.64
keyword:
- Unified modeling language
- Software design
- Virtual machining
- Embedded system
- Programming
- Documentation
- Hardware
- Computer languages
- Operating systems
- Runtime
language:
- iso: eng
place: Dallas, TX, USA
publication: Proceedings of VL/HCC 05
publication_identifier:
isbn:
- 0-7695-2443-5
status: public
title: Transformation of UML State Machines for Direct Execution
type: conference
user_id: '5786'
year: '2005'
...
---
_id: '39061'
abstract:
- lang: eng
text: This article presents an approach, which combines theorem proving-based refinement
with model checking for state based real-time systems. Our verification flow starts
from UML state diagrams, which are translated to the formal B language and are
model checked for real-time properties. By means of the B language and a B theorem
prover, refined state diagrams are verified against their abstract representation.
The approach is presented by means of the refinement of a digital echo cancellation
unit.
author:
- first_name: Alexander
full_name: Krupp, Alexander
last_name: Krupp
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Ian
full_name: Oliver, Ian
last_name: Oliver
citation:
ama: 'Krupp A, Müller W, Oliver I. Formal Refinement and Model Checking of An Echo
Cancellation Unit. In: Proceedings of DATE’04 Designers’ Forum. ; 2004.
doi:10.1109/DATE.2004.1269214'
apa: Krupp, A., Müller, W., & Oliver, I. (2004). Formal Refinement and Model
Checking of An Echo Cancellation Unit. Proceedings of DATE’04 Designers’ Forum.
Proceedings Design, Automation and Test in Europe Conference and Exhibition. https://doi.org/10.1109/DATE.2004.1269214
bibtex: '@inproceedings{Krupp_Müller_Oliver_2004, place={Paris}, title={Formal Refinement
and Model Checking of An Echo Cancellation Unit}, DOI={10.1109/DATE.2004.1269214},
booktitle={Proceedings of DATE’04 Designers’ Forum}, author={Krupp, Alexander
and Müller, Wolfgang and Oliver, Ian}, year={2004} }'
chicago: Krupp, Alexander, Wolfgang Müller, and Ian Oliver. “Formal Refinement and
Model Checking of An Echo Cancellation Unit.” In Proceedings of DATE’04 Designers’
Forum. Paris, 2004. https://doi.org/10.1109/DATE.2004.1269214.
ieee: 'A. Krupp, W. Müller, and I. Oliver, “Formal Refinement and Model Checking
of An Echo Cancellation Unit,” presented at the Proceedings Design, Automation
and Test in Europe Conference and Exhibition, 2004, doi: 10.1109/DATE.2004.1269214.'
mla: Krupp, Alexander, et al. “Formal Refinement and Model Checking of An Echo Cancellation
Unit.” Proceedings of DATE’04 Designers’ Forum, 2004, doi:10.1109/DATE.2004.1269214.
short: 'A. Krupp, W. Müller, I. Oliver, in: Proceedings of DATE’04 Designers’ Forum,
Paris, 2004.'
conference:
name: Proceedings Design, Automation and Test in Europe Conference and Exhibition
date_created: 2023-01-24T08:53:26Z
date_updated: 2023-01-24T08:53:31Z
department:
- _id: '672'
doi: 10.1109/DATE.2004.1269214
keyword:
- Echo cancellers
- Logic
- Unified modeling language
- Automata
- Data structures
- Boolean functions
- Electronic design automation and methodology
- Prototypes
- Specification languages
- Constraint theory
language:
- iso: eng
place: Paris
publication: Proceedings of DATE’04 Designers' Forum
publication_identifier:
isbn:
- 0-7695-2085-5
status: public
title: Formal Refinement and Model Checking of An Echo Cancellation Unit
type: conference
user_id: '5786'
year: '2004'
...
---
_id: '2422'
abstract:
- lang: eng
text: Reconfigurable computing architectures aim to dynamically adapt their hardware
to the application at hand. As research shows, the time it takes to reconfigure
the hardware forms an overhead that can significantly impair the benefits of hardware
customization. Multi-context devices are one promising approach to overcome the
limitations posed by long reconfiguration times. In contrast to more traditional
reconfigurable architectures, multi-context devices hold several configurations
on-chip. On demand, the device can quickly switch to another context. In this
paper we present a co-simulation environment to investigate design trade-offs
for hybrid multi-context architectures. Our architectural model comprises a reconfigurable
unit closely coupled to a CPU core. As a case study, we discuss the implementation
of a FIR filter partitioned into several contexts. We outline the mapping process
and present simulation results for single- and multi-context reconfigurable units
coupled with both embedded and high-end CPUs.
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Enzler R, Plessl C, Platzner M. Co-simulation of a Hybrid Multi-Context Architecture.
In: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA). CSREA Press; 2003:174-180.'
apa: Enzler, R., Plessl, C., & Platzner, M. (2003). Co-simulation of a Hybrid
Multi-Context Architecture. In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA) (pp. 174–180). CSREA Press.
bibtex: '@inproceedings{Enzler_Plessl_Platzner_2003, title={Co-simulation of a Hybrid
Multi-Context Architecture}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Enzler, Rolf
and Plessl, Christian and Platzner, Marco}, year={2003}, pages={174–180} }'
chicago: Enzler, Rolf, Christian Plessl, and Marco Platzner. “Co-Simulation of a
Hybrid Multi-Context Architecture.” In Proc. Int. Conf. on Engineering of Reconfigurable
Systems and Algorithms (ERSA), 174–80. CSREA Press, 2003.
ieee: R. Enzler, C. Plessl, and M. Platzner, “Co-simulation of a Hybrid Multi-Context
Architecture,” in Proc. Int. Conf. on Engineering of Reconfigurable Systems
and Algorithms (ERSA), 2003, pp. 174–180.
mla: Enzler, Rolf, et al. “Co-Simulation of a Hybrid Multi-Context Architecture.”
Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA),
CSREA Press, 2003, pp. 174–80.
short: 'R. Enzler, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of
Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2003, pp. 174–180.'
date_created: 2018-04-17T15:12:56Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
keyword:
- Zippy
- co-simulation
page: 174-180
publication: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms
(ERSA)
publication_identifier:
isbn:
- 1-932415-05-X
publisher: CSREA Press
status: public
title: Co-simulation of a Hybrid Multi-Context Architecture
type: conference
user_id: '24135'
year: '2003'
...
---
_id: '39411'
abstract:
- lang: eng
text: Rapid prototyping based on 3D models is well accepted for several applications.
This article addresses the application of animated virtual 3D prototypes for the
development of computer-based systems supporting early collaboration of the system
designer with the external customer. Our methodology seamlessly integrates illustration
through 3D animation with the main tasks of computer-based real-time systems development,
i.e., implementation and verification. The approach is outlined by the example
of the design of a flexible manufacturing system.
author:
- first_name: Stephan
full_name: Flake, Stephan
last_name: Flake
- first_name: Christian
full_name: Geiger, Christian
last_name: Geiger
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Jürgen
full_name: Ruf, Jürgen
last_name: Ruf
citation:
ama: 'Flake S, Geiger C, Müller W, Ruf J. Customer-Oriented Systems Design through
Virtual Prototyps. In: Proceedings of IEEE KMN 2001. ; 2001. doi:10.1109/ENABL.2001.953425'
apa: 'Flake, S., Geiger, C., Müller, W., & Ruf, J. (2001). Customer-Oriented
Systems Design through Virtual Prototyps. Proceedings of IEEE KMN 2001.
Proceedings Tenth IEEE International Workshop on Enabling Technologies: Infrastructure
for Collaborative Enterprises. https://doi.org/10.1109/ENABL.2001.953425'
bibtex: '@inproceedings{Flake_Geiger_Müller_Ruf_2001, place={Cambridge, MA, USA
}, title={Customer-Oriented Systems Design through Virtual Prototyps}, DOI={10.1109/ENABL.2001.953425},
booktitle={Proceedings of IEEE KMN 2001}, author={Flake, Stephan and Geiger, Christian
and Müller, Wolfgang and Ruf, Jürgen}, year={2001} }'
chicago: Flake, Stephan, Christian Geiger, Wolfgang Müller, and Jürgen Ruf. “Customer-Oriented
Systems Design through Virtual Prototyps.” In Proceedings of IEEE KMN 2001.
Cambridge, MA, USA , 2001. https://doi.org/10.1109/ENABL.2001.953425.
ieee: 'S. Flake, C. Geiger, W. Müller, and J. Ruf, “Customer-Oriented Systems Design
through Virtual Prototyps,” presented at the Proceedings Tenth IEEE International
Workshop on Enabling Technologies: Infrastructure for Collaborative Enterprises,
2001, doi: 10.1109/ENABL.2001.953425.'
mla: Flake, Stephan, et al. “Customer-Oriented Systems Design through Virtual Prototyps.”
Proceedings of IEEE KMN 2001, 2001, doi:10.1109/ENABL.2001.953425.
short: 'S. Flake, C. Geiger, W. Müller, J. Ruf, in: Proceedings of IEEE KMN 2001,
Cambridge, MA, USA , 2001.'
conference:
name: 'Proceedings Tenth IEEE International Workshop on Enabling Technologies: Infrastructure
for Collaborative Enterprises'
date_created: 2023-01-24T10:30:14Z
date_updated: 2023-01-24T10:30:21Z
department:
- _id: '672'
doi: 10.1109/ENABL.2001.953425
keyword:
- Virtual prototyping
- Animation
- Collaboration
- System analysis and design
- Feedback
- Application software
- Power system modeling
- Handicapped aids
- Process design
- Contracts
language:
- iso: eng
place: 'Cambridge, MA, USA '
publication: Proceedings of IEEE KMN 2001
publication_identifier:
isbn:
- 0-7695-1269-0
status: public
title: Customer-Oriented Systems Design through Virtual Prototyps
type: conference
user_id: '5786'
year: '2001'
...
---
_id: '39421'
abstract:
- lang: eng
text: We present a rigorous but transparent semantics definition of SystemC that
covers method, thread, and clocked thread behavior as well as their interaction
with the simulation kernel process. The semantics includes watching statements,
signal assignment, and wait statements as they are introduced in SystemC V1.O.
We present our definition in form of distributed Abstract State Machines (ASMs)
rules reflecting the view given in the SystemC User's Manual and the reference
implementation. We mainly see our formal semantics as a concise, unambiguous,
high-level specification for SystemC-based implementations and for standardization.
Additionally, it can be used as a sound basis to investigate SystemC interoperability
with Verilog and VHDL.
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Jürgen
full_name: Ruf, Jürgen
last_name: Ruf
- first_name: D. W.
full_name: Hoffmann, D. W.
last_name: Hoffmann
- first_name: Joachim
full_name: Gerlach, Joachim
last_name: Gerlach
- first_name: Thomas
full_name: Kropf, Thomas
last_name: Kropf
- first_name: W.
full_name: Rosenstiehl, W.
last_name: Rosenstiehl
citation:
ama: 'Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation
Semantics of SystemC. In: Proceedings of the Design, Automation, and Test in
Europe (DATE’01). IEEE; 2001. doi:10.1109/DATE.2001.915002'
apa: Müller, W., Ruf, J., Hoffmann, D. W., Gerlach, J., Kropf, T., & Rosenstiehl,
W. (2001). The Simulation Semantics of SystemC. Proceedings of the Design,
Automation, and Test in Europe (DATE’01). Proceedings Design, Automation
and Test in Europe. Conference and Exhibition 2001. https://doi.org/10.1109/DATE.2001.915002
bibtex: '@inproceedings{Müller_Ruf_Hoffmann_Gerlach_Kropf_Rosenstiehl_2001, place={Munich,
Germany }, title={The Simulation Semantics of SystemC}, DOI={10.1109/DATE.2001.915002},
booktitle={Proceedings of the Design, Automation, and Test in Europe (DATE’01)},
publisher={IEEE}, author={Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W.
and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}, year={2001} }'
chicago: 'Müller, Wolfgang, Jürgen Ruf, D. W. Hoffmann, Joachim Gerlach, Thomas
Kropf, and W. Rosenstiehl. “The Simulation Semantics of SystemC.” In Proceedings
of the Design, Automation, and Test in Europe (DATE’01). Munich, Germany :
IEEE, 2001. https://doi.org/10.1109/DATE.2001.915002.'
ieee: 'W. Müller, J. Ruf, D. W. Hoffmann, J. Gerlach, T. Kropf, and W. Rosenstiehl,
“The Simulation Semantics of SystemC,” presented at the Proceedings Design, Automation
and Test in Europe. Conference and Exhibition 2001, 2001, doi: 10.1109/DATE.2001.915002.'
mla: Müller, Wolfgang, et al. “The Simulation Semantics of SystemC.” Proceedings
of the Design, Automation, and Test in Europe (DATE’01), IEEE, 2001, doi:10.1109/DATE.2001.915002.
short: 'W. Müller, J. Ruf, D.W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl,
in: Proceedings of the Design, Automation, and Test in Europe (DATE’01), IEEE,
Munich, Germany , 2001.'
conference:
name: ' Proceedings Design, Automation and Test in Europe. Conference and Exhibition
2001'
date_created: 2023-01-24T10:39:33Z
date_updated: 2023-01-24T10:39:38Z
department:
- _id: '672'
doi: 10.1109/DATE.2001.915002
keyword:
- Yarn
- Formal verification
- Kernel
- Hardware design languages
- Electronic design automation and methodology
- Algebra
- Computational modeling
- Logic functions
- Computer languages
- Clocks
language:
- iso: eng
place: 'Munich, Germany '
publication: Proceedings of the Design, Automation, and Test in Europe (DATE’01)
publication_identifier:
isbn:
- 0-7695-0993-2
publisher: IEEE
status: public
title: The Simulation Semantics of SystemC
type: conference
user_id: '5786'
year: '2001'
...
---
_id: '2433'
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Simon
full_name: Maurer, Simon
last_name: Maurer
citation:
ama: Plessl C, Maurer S. Hardware/Software Codesign in Speech Compression Applications.
Computer Engineering and Networks Lab, ETH Zurich, Switzerland; 2000.
apa: Plessl, C., & Maurer, S. (2000). Hardware/Software Codesign in Speech
Compression Applications. Computer Engineering and Networks Lab, ETH Zurich,
Switzerland.
bibtex: '@book{Plessl_Maurer_2000, title={Hardware/Software Codesign in Speech Compression
Applications}, publisher={Computer Engineering and Networks Lab, ETH Zurich, Switzerland},
author={Plessl, Christian and Maurer, Simon}, year={2000} }'
chicago: Plessl, Christian, and Simon Maurer. Hardware/Software Codesign in Speech
Compression Applications. Computer Engineering and Networks Lab, ETH Zurich,
Switzerland, 2000.
ieee: C. Plessl and S. Maurer, Hardware/Software Codesign in Speech Compression
Applications. Computer Engineering and Networks Lab, ETH Zurich, Switzerland,
2000.
mla: Plessl, Christian, and Simon Maurer. Hardware/Software Codesign in Speech
Compression Applications. Computer Engineering and Networks Lab, ETH Zurich,
Switzerland, 2000.
short: C. Plessl, S. Maurer, Hardware/Software Codesign in Speech Compression Applications,
Computer Engineering and Networks Lab, ETH Zurich, Switzerland, 2000.
date_created: 2018-04-17T15:56:00Z
date_updated: 2022-01-06T06:56:17Z
department:
- _id: '518'
keyword:
- co-design
- speech processing
publisher: Computer Engineering and Networks Lab, ETH Zurich, Switzerland
status: public
title: Hardware/Software Codesign in Speech Compression Applications
type: mastersthesis
user_id: '24135'
year: '2000'
...
---
_id: '39487'
abstract:
- lang: eng
text: This article introduces and discusses different innovative means for visual
specification and animation of complex concurrent systems. It introduces the completely
visual programming language Pictorial Janus (PJ) and its application in the customer-oriented
design process. PJ implements a completely visual programming language with inherent
animation facilities. The article outlines the transformation of purely visual
PJ programs into textual imperative programming languages. The second part of
the article investigates animated 3D-presentations and introduces a novel approach
to an animated 3D programming language for interactive customer-oriented illustrations.
author:
- first_name: Christian
full_name: Geiger, Christian
last_name: Geiger
- first_name: G.
full_name: Lehrenfeld, G.
last_name: Lehrenfeld
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Geiger C, Lehrenfeld G, Müller W. Visual Specification, Modeling, and Illustrations
of Complex Systems. In: Proceedings of HICSS-32. ; 1999. doi:10.1109/HICSS.1999.772621'
apa: Geiger, C., Lehrenfeld, G., & Müller, W. (1999). Visual Specification,
Modeling, and Illustrations of Complex Systems. Proceedings of HICSS-32.
Proceedings of the 32nd Annual Hawaii International Conference on Systems Sciences
1999, Maui, Hawaii. https://doi.org/10.1109/HICSS.1999.772621
bibtex: '@inproceedings{Geiger_Lehrenfeld_Müller_1999, place={Maui, Hawaii}, title={Visual
Specification, Modeling, and Illustrations of Complex Systems}, DOI={10.1109/HICSS.1999.772621},
booktitle={Proceedings of HICSS-32}, author={Geiger, Christian and Lehrenfeld,
G. and Müller, Wolfgang}, year={1999} }'
chicago: Geiger, Christian, G. Lehrenfeld, and Wolfgang Müller. “Visual Specification,
Modeling, and Illustrations of Complex Systems.” In Proceedings of HICSS-32.
Maui, Hawaii, 1999. https://doi.org/10.1109/HICSS.1999.772621.
ieee: 'C. Geiger, G. Lehrenfeld, and W. Müller, “Visual Specification, Modeling,
and Illustrations of Complex Systems,” presented at the Proceedings of the 32nd
Annual Hawaii International Conference on Systems Sciences 1999, Maui, Hawaii,
1999, doi: 10.1109/HICSS.1999.772621.'
mla: Geiger, Christian, et al. “Visual Specification, Modeling, and Illustrations
of Complex Systems.” Proceedings of HICSS-32, 1999, doi:10.1109/HICSS.1999.772621.
short: 'C. Geiger, G. Lehrenfeld, W. Müller, in: Proceedings of HICSS-32, Maui,
Hawaii, 1999.'
conference:
location: Maui, Hawaii
name: Proceedings of the 32nd Annual Hawaii International Conference on Systems
Sciences 1999
date_created: 2023-01-24T11:33:05Z
date_updated: 2023-01-24T11:33:35Z
department:
- _id: '672'
doi: 10.1109/HICSS.1999.772621
keyword:
- Animation
- Computer languages
- Object oriented modeling
- Collaboration
- Process design
- Graphical user interfaces
- Jacobian matrices
- Standardization
- Feedback
- Software prototyping
language:
- iso: eng
place: Maui, Hawaii
publication: Proceedings of HICSS-32
publication_identifier:
isbn:
- 0-7695-0001-3
status: public
title: Visual Specification, Modeling, and Illustrations of Complex Systems
type: conference
user_id: '5786'
year: '1999'
...