@inproceedings{10780, author = {{Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}}, booktitle = {{12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, keywords = {{embedded systems, image sensors, power aware computing, wireless sensor networks, Zynq-based VSN node prototype, computational self-awareness, design approach, platform levels, power consumption, visual sensor networks, visual sensor nodes, Cameras, Hardware, Middleware, Multicore processing, Operating systems, Runtime, Reconfigurable platforms, distributed embedded systems, performance-resource trade-off, self-awareness, visual sensor nodes}}, pages = {{1--8}}, title = {{{Computational self-awareness as design approach for visual sensor nodes}}}, doi = {{10.1109/ReCoSoC.2017.8016147}}, year = {{2017}}, } @inproceedings{10779, author = {{Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}}, booktitle = {{25th International Conference on Field Programmable Logic and Applications (FPL)}}, issn = {{1946-147X}}, keywords = {{embedded systems, field programmable gate arrays, operating systems (computers), scheduling, μC/OS-II, FPGAs, OS foundation, SafeRTOS, Xenomai, chip utilization ration, complex time constraints, embedded systems, hard real-time hardware task allocation, hard real-time hardware task scheduling, hardware-software real-time operating systems, partially reconfigurable field-programmable gate arrays, resource constraints, safety-critical RTOS, Field programmable gate arrays, Hardware, Job shop scheduling, Real-time systems, Shape, Software}}, publisher = {{Imperial College}}, title = {{{Over effective hard real-time hardware tasks scheduling and allocation}}}, doi = {{10.1109/FPL.2015.7293994}}, year = {{2015}}, } @misc{33312, abstract = {{Mechatronic systems are used more than ever in human life. They can be found in a very wide range of domain contexts, from household appliances, and cars, to medical equipment. Mechatronic systems, as a kind of embedded systems, are the tight integration of mechanical and electrical engineering, which embed software systems. Information security of mechatronic systems has not received much attention yet. However, wherever data exists, cyber attacks threaten mechatronic systems. The thesis focuses on the early design stages of the development of mechatronic systems. Model sequence diagrams (MSDs) are used to model requirements with real-time and safety properties. In this thesis, MSDs are extended such that security properties for example authenticity and privacy can be modeled and analyzed automatically.}}, author = {{Schwichtenberg, Bahar}}, keywords = {{Software Architecture, Requirements Engineering, Embedded Systems}}, title = {{{Early Prediction of Security Properties for Mechatronic Systems}}}, year = {{2015}}, } @inproceedings{10674, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}}, keywords = {{Linux, hardware-software codesign, multiprocessing systems, parallel processing, LEON3 multicore platform, Linux kernel, PMU, hardware counters, hardware-software infrastructure, high performance embedded computing, perf_event, performance monitoring unit, Computer architecture, Hardware, Monitoring, Phasor measurement units, Radiation detectors, Registers, Software}}, pages = {{1--4}}, title = {{{A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}}}, doi = {{10.1109/FPL.2014.6927437}}, year = {{2014}}, } @inproceedings{10677, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}}, keywords = {{Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}}, pages = {{31--37}}, title = {{{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}}, doi = {{10.1109/ICES.2014.7008719}}, year = {{2014}}, } @inproceedings{37009, abstract = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}}, author = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{Assertion-Based Verification of RTOS Properties}}}, doi = {{10.1109/DATE.2010.5457130}}, year = {{2010}}, } @inproceedings{37037, abstract = {{Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.}}, author = {{Krupp, Alexander and Müller, Wolfgang}}, booktitle = {{Proceedings of DATE’10}}, keywords = {{System testing, Automatic testing, Object oriented modeling, Classification tree analysis, Automotive engineering, Mathematical model, Embedded system, Control systems, Electronic equipment testing, Software testing}}, location = {{Dresden}}, publisher = {{IEEE}}, title = {{{A Systematic Approach to Combined HW/SW System Test}}}, doi = {{10.1109/DATE.2010.5457186}}, year = {{2010}}, } @inproceedings{2392, author = {{Woehrle, Matthias and Plessl, Christian and Beutel, Jan and Thiele, Lothar}}, booktitle = {{Proc. Workshop on Embedded Networked Sensors (EmNets)}}, isbn = {{978-1-59593-694-3}}, keywords = {{WSN, testing, distributed, embedded}}, pages = {{93--97}}, publisher = {{ACM}}, title = {{{Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework}}}, doi = {{10.1145/1278972.1278996}}, year = {{2007}}, } @inproceedings{38784, abstract = {{This article presents the classification tree method for functional verification to close the gap from the specification of a test plan to SystemVerilog (Chandra and Chakrabarty, 2001) test bench generation. Our method supports the systematic development of test configurations and is based on the classification tree method for embedded systems (CTM/ES) (Chakrabarty et al., 2000) extending CTM/ES for random test generation as well as for functional coverage and property specification}}, author = {{Krupp, Alexander and Müller, Wolfgang}}, booktitle = {{Proceedings of the Design Automation & Test in Europe Conference}}, isbn = {{3-9810801-1-4}}, keywords = {{Classification tree analysis, System testing, Embedded system, Safety, Automatic testing, Automation}}, publisher = {{IEEE}}, title = {{{Classification Trees for Functional Coverage and Random Test Generation}}}, doi = {{10.1109/DATE.2006.243902}}, year = {{2006}}, } @inproceedings{39029, abstract = {{UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}}, booktitle = {{Proceedings of DATE’05}}, isbn = {{0-7695-2288-2}}, keywords = {{Hardware, Unified modeling language, Virtual machining, Object oriented modeling, Field programmable gate arrays, Java, Microcontrollers, Embedded software, Real time systems, Documentation}}, publisher = {{IEEE}}, title = {{{A Model-Based Approach for Executable Specification on Reconfigurable Hardware}}}, doi = {{10.1109/DATE.2005.20}}, year = {{2005}}, } @inproceedings{39030, abstract = {{StateCharts are well accepted for embedded systems specification for various applications. However, for the specification of complex systems they have several limitations. In this article, we present a novel approach to efficiently execute an UML 2.0 subset for embedded real- time systems implementation with focus on hardware interrupts, software exceptions, and timeouts. We introduce a UML Virtual Machine, which directly executes sequence diagrams, which are embedded into hierarchically structured state transition diagrams. Whereas state diagrams are directly executed as Embedded State Machines (ESMs), sequence diagrams are translated into UVM Bytecode. The final UVM execution is performed by the interaction of the ESM and the Bytecode Interpreter. Due to our completely model- based approach, the UVM runtime kernel is easily adaptable and scalable to different scheduling and memory management strategies.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of ISNG 05}}, keywords = {{UML, Executable Models, Hardware/Software Co-design, Virtual Machine, Embedded Systems}}, title = {{{A UML Virtual Machine for Embedded Systems}}}, year = {{2005}}, } @inproceedings{39032, abstract = {{Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of VL/HCC 05}}, isbn = {{0-7695-2443-5}}, keywords = {{Unified modeling language, Software design, Virtual machining, Embedded system, Programming, Documentation, Hardware, Computer languages, Operating systems, Runtime}}, title = {{{Transformation of UML State Machines for Direct Execution}}}, doi = {{10.1109/VLHCC.2005.64}}, year = {{2005}}, } @inproceedings{39052, abstract = {{Smart homes provide their users with maximum comfort and convenience. In this paper, we present a profile management framework for situation-dependent customization in smart home environments, which meet the user preferences with given device capabilities. We apply profile processing and evolution methods to customize profiles on the fly and to automatically evolve user preferences. Furthermore, we give a comprehensive study on profile management technology.}}, author = {{Groppe, Jinghua and Müller, Wolfgang}}, booktitle = {{Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005)}}, isbn = {{0-7695-2424-9}}, keywords = {{Technology management, Smart homes, Environmental management, Resource description framework, Data models, Navigation, Mobile computing, Embedded computing, Ubiquitous computing, Mobile communication}}, location = {{Copenhagen, Denmark }}, publisher = {{IEEE}}, title = {{{Profile Management technology for Smart Customization in Private Home Applications}}}, doi = {{10.1109/DEXA.2005.156}}, year = {{2005}}, }