[{"type":"conference","publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","status":"public","_id":"10780","user_id":"3118","department":[{"_id":"78"}],"keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"language":[{"iso":"eng"}],"year":"2017","citation":{"bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>.","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","apa":"Guettatfi, Z., Hübner, P., Platzner, M., &#38; Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i> (pp. 1–8). <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>","ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2017:1-8. doi:<a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">10.1109/ReCoSoC.2017.8016147</a>","chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>, 1–8, 2017. <a href=\"https://doi.org/10.1109/ReCoSoC.2017.8016147\">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>.","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in <i>12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8."},"page":"1-8","date_updated":"2022-01-06T06:50:50Z","author":[{"last_name":"Guettatfi","full_name":"Guettatfi, Zakarya","first_name":"Zakarya"},{"first_name":"Philipp","full_name":"Hübner, Philipp","last_name":"Hübner"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"},{"full_name":"Rinner, Bernhard","last_name":"Rinner","first_name":"Bernhard"}],"date_created":"2019-07-10T12:13:15Z","title":"Computational self-awareness as design approach for visual sensor nodes","doi":"10.1109/ReCoSoC.2017.8016147"},{"publication_identifier":{"issn":["1946-147X"]},"citation":{"chicago":"Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College, 2015. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>.","ieee":"Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2015.","ama":"Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College; 2015. doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>","mla":"Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, Imperial College, 2015, doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>.","bibtex":"@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }","short":"Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.","apa":"Guettatfi, Z., Kermia, O., &#38; Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>"},"year":"2015","author":[{"last_name":"Guettatfi","full_name":"Guettatfi, Zakarya","first_name":"Zakarya"},{"first_name":"Omar","last_name":"Kermia","full_name":"Kermia, Omar"},{"first_name":"Abdelhakim","full_name":"Khouas, Abdelhakim","last_name":"Khouas"}],"date_created":"2019-07-10T12:11:36Z","date_updated":"2022-01-06T06:50:50Z","publisher":"Imperial College","doi":"10.1109/FPL.2015.7293994","title":"Over effective hard real-time hardware tasks scheduling and allocation","type":"conference","publication":"25th International Conference on Field Programmable Logic and Applications (FPL)","status":"public","user_id":"398","department":[{"_id":"78"}],"_id":"10779","extern":"1","language":[{"iso":"eng"}],"keyword":["embedded systems","field programmable gate arrays","operating systems (computers)","scheduling","μC/OS-II","FPGAs","OS foundation","SafeRTOS","Xenomai","chip utilization ration","complex time constraints","embedded systems","hard real-time hardware task allocation","hard real-time hardware task scheduling","hardware-software real-time operating systems","partially reconfigurable field-programmable gate arrays","resource constraints","safety-critical RTOS","Field programmable gate arrays","Hardware","Job shop scheduling","Real-time systems","Shape","Software"]},{"publication_status":"published","has_accepted_license":"1","year":"2015","citation":{"chicago":"Schwichtenberg, Bahar. <i>Early Prediction of Security Properties for Mechatronic Systems</i>, 2015.","ieee":"B. Schwichtenberg, <i>Early Prediction of Security Properties for Mechatronic Systems</i>. 2015.","ama":"Schwichtenberg B. <i>Early Prediction of Security Properties for Mechatronic Systems</i>.; 2015.","mla":"Schwichtenberg, Bahar. <i>Early Prediction of Security Properties for Mechatronic Systems</i>. 2015.","short":"B. Schwichtenberg, Early Prediction of Security Properties for Mechatronic Systems, 2015.","bibtex":"@book{Schwichtenberg_2015, title={Early Prediction of Security Properties for Mechatronic Systems}, author={Schwichtenberg, Bahar}, year={2015} }","apa":"Schwichtenberg, B. (2015). <i>Early Prediction of Security Properties for Mechatronic Systems</i>."},"date_updated":"2022-12-30T22:12:13Z","author":[{"first_name":"Bahar","last_name":"Schwichtenberg","id":"36399","full_name":"Schwichtenberg, Bahar"}],"date_created":"2022-09-09T11:42:25Z","title":"Early Prediction of Security Properties for Mechatronic Systems","type":"mastersthesis","abstract":[{"text":"Mechatronic systems are used more than ever in human life. They can be found in a very wide range of domain contexts, from household appliances, and cars, to medical equipment. Mechatronic systems, as a kind of embedded systems, are the tight integration of mechanical and electrical engineering, which embed software systems. Information security of mechatronic systems has not received much attention yet. However, wherever data exists, cyber attacks threaten mechatronic systems.\r\n\r\nThe thesis focuses on the early design stages of the development of mechatronic systems. Model sequence diagrams (MSDs) are used to model requirements with real-time and safety properties. In this thesis, MSDs are extended such that security properties for example authenticity and privacy can be modeled and analyzed automatically.","lang":"eng"}],"file":[{"content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2022-12-30T22:10:51Z","creator":"bahareh","date_updated":"2022-12-30T22:10:51Z","file_name":"Bahar_Jazayeri_Masterarbeit.pdf","access_level":"closed","file_id":"35068","file_size":11423528}],"status":"public","_id":"33312","user_id":"36399","ddc":["000"],"keyword":["Software Architecture","Requirements Engineering","Embedded Systems"],"extern":"1","language":[{"iso":"eng"}],"file_date_updated":"2022-12-30T22:10:51Z"},{"page":"1-4","citation":{"apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i> (pp. 1–4). <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>","mla":"Ho, Nam, et al. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4, doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 24th Intl. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–4.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms}, DOI={<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>}, booktitle={24th Intl. Conf. on Field Programmable Logic and Applications (FPL)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={1–4} }","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “A Hardware/Software Infrastructure for Performance Monitoring on LEON3 Multicore Platforms.” In <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 1–4, 2014. <a href=\"https://doi.org/10.1109/FPL.2014.6927437\">https://doi.org/10.1109/FPL.2014.6927437</a>.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms,” in <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2014, pp. 1–4.","ama":"Ho N, Kaufmann P, Platzner M. A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms. In: <i>24th Intl. Conf. on Field Programmable Logic and Applications (FPL)</i>. ; 2014:1-4. doi:<a href=\"https://doi.org/10.1109/FPL.2014.6927437\">10.1109/FPL.2014.6927437</a>"},"year":"2014","author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"date_created":"2019-07-10T11:18:01Z","date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/FPL.2014.6927437","title":"A hardware/software infrastructure for performance monitoring on LEON3 multicore platforms","publication":"24th Intl. Conf. on Field Programmable Logic and Applications (FPL)","type":"conference","status":"public","department":[{"_id":"78"}],"user_id":"3118","_id":"10674","project":[{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"language":[{"iso":"eng"}],"keyword":["Linux","hardware-software codesign","multiprocessing systems","parallel processing","LEON3 multicore platform","Linux kernel","PMU","hardware counters","hardware-software infrastructure","high performance embedded computing","perf_event","performance monitoring unit","Computer architecture","Hardware","Monitoring","Phasor measurement units","Radiation detectors","Registers","Software"]},{"keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"],"language":[{"iso":"eng"}],"_id":"10677","department":[{"_id":"78"}],"user_id":"3118","status":"public","publication":"2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)","type":"conference","title":"Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure","doi":"10.1109/ICES.2014.7008719","date_updated":"2022-01-06T06:50:49Z","date_created":"2019-07-10T11:23:00Z","author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"year":"2014","page":"31-37","citation":{"bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }","mla":"Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37, doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i> (pp. 31–37). <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 31–37, 2014. <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37.","ama":"Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>. ; 2014:31-37. doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>"}},{"title":"Assertion-Based Verification of RTOS Properties","conference":{"location":"Dresden","name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"},"doi":"10.1109/DATE.2010.5457130","publisher":"IEEE","date_updated":"2023-01-17T09:15:18Z","author":[{"first_name":"Marcio F. S.","full_name":"Oliveira, Marcio F. S.","last_name":"Oliveira"},{"last_name":"Zabel","full_name":"Zabel, Henning","first_name":"Henning"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"}],"date_created":"2023-01-17T09:15:10Z","year":"2010","place":"Dresden","citation":{"mla":"Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>.","bibtex":"@inproceedings{Oliveira_Zabel_Müller_2010, place={Dresden}, title={Assertion-Based Verification of RTOS Properties}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}, year={2010} }","short":"M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","apa":"Oliveira, M. F. S., Zabel, H., &#38; Müller, W. (2010). Assertion-Based Verification of RTOS Properties. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">https://doi.org/10.1109/DATE.2010.5457130</a>","ama":"Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>","ieee":"M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification of RTOS Properties,” presented at the 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">10.1109/DATE.2010.5457130</a>.","chicago":"Oliveira, Marcio F. S., Henning Zabel, and Wolfgang Müller. “Assertion-Based Verification of RTOS Properties.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5457130\">https://doi.org/10.1109/DATE.2010.5457130</a>."},"keyword":["Operating systems","Real time systems","Timing","Hardware","Analytical models","Embedded software","Software systems","Processor scheduling","Software performance","Performance analysis"],"language":[{"iso":"eng"}],"_id":"37009","department":[{"_id":"672"}],"user_id":"5786","abstract":[{"lang":"eng","text":"Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties."}],"status":"public","publication":"Proceedings of DATE’10","type":"conference"},{"type":"conference","publication":"Proceedings of DATE’10","abstract":[{"lang":"eng","text":"Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition."}],"status":"public","_id":"37037","user_id":"5786","department":[{"_id":"672"}],"keyword":["System testing","Automatic testing","Object oriented modeling","Classification tree analysis","Automotive engineering","Mathematical model","Embedded system","Control systems","Electronic equipment testing","Software testing"],"language":[{"iso":"eng"}],"year":"2010","place":"Dresden","citation":{"chicago":"Krupp, Alexander, and Wolfgang Müller. “A Systematic Approach to Combined HW/SW System Test.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5457186\">https://doi.org/10.1109/DATE.2010.5457186</a>.","ieee":"A. Krupp and W. Müller, “A Systematic Approach to Combined HW/SW System Test,” presented at the Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5457186\">10.1109/DATE.2010.5457186</a>.","ama":"Krupp A, Müller W. A Systematic Approach to Combined HW/SW System Test. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457186\">10.1109/DATE.2010.5457186</a>","apa":"Krupp, A., &#38; Müller, W. (2010). A Systematic Approach to Combined HW/SW System Test. <i>Proceedings of DATE’10</i>. Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5457186\">https://doi.org/10.1109/DATE.2010.5457186</a>","short":"A. Krupp, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","mla":"Krupp, Alexander, and Wolfgang Müller. “A Systematic Approach to Combined HW/SW System Test.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5457186\">10.1109/DATE.2010.5457186</a>.","bibtex":"@inproceedings{Krupp_Müller_2010, place={Dresden}, title={A Systematic Approach to Combined HW/SW System Test}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5457186\">10.1109/DATE.2010.5457186</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Krupp, Alexander and Müller, Wolfgang}, year={2010} }"},"date_updated":"2023-01-17T10:41:25Z","publisher":"IEEE","date_created":"2023-01-17T10:41:15Z","author":[{"first_name":"Alexander","last_name":"Krupp","full_name":"Krupp, Alexander"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"}],"title":"A Systematic Approach to Combined HW/SW System Test","conference":{"name":"Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)","location":"Dresden"},"doi":"10.1109/DATE.2010.5457186"},{"status":"public","publication":"Proc. Workshop on Embedded Networked Sensors (EmNets)","type":"conference","language":[{"iso":"eng"}],"keyword":["WSN","testing","distributed","embedded"],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","_id":"2392","page":"93-97","citation":{"apa":"Woehrle, M., Plessl, C., Beutel, J., &#38; Thiele, L. (2007). Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 93–97. <a href=\"https://doi.org/10.1145/1278972.1278996\">https://doi.org/10.1145/1278972.1278996</a>","short":"M. Woehrle, C. Plessl, J. Beutel, L. Thiele, in: Proc. Workshop on Embedded Networked Sensors (EmNets), ACM, New York, NY, USA, 2007, pp. 93–97.","mla":"Woehrle, Matthias, et al. “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework.” <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, ACM, 2007, pp. 93–97, doi:<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>.","bibtex":"@inproceedings{Woehrle_Plessl_Beutel_Thiele_2007, place={New York, NY, USA}, title={Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework}, DOI={<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>}, booktitle={Proc. Workshop on Embedded Networked Sensors (EmNets)}, publisher={ACM}, author={Woehrle, Matthias and Plessl, Christian and Beutel, Jan and Thiele, Lothar}, year={2007}, pages={93–97} }","ieee":"M. Woehrle, C. Plessl, J. Beutel, and L. Thiele, “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework,” in <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 2007, pp. 93–97, doi: <a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>.","chicago":"Woehrle, Matthias, Christian Plessl, Jan Beutel, and Lothar Thiele. “Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework.” In <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>, 93–97. New York, NY, USA: ACM, 2007. <a href=\"https://doi.org/10.1145/1278972.1278996\">https://doi.org/10.1145/1278972.1278996</a>.","ama":"Woehrle M, Plessl C, Beutel J, Thiele L. Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework. In: <i>Proc. Workshop on Embedded Networked Sensors (EmNets)</i>. ACM; 2007:93-97. doi:<a href=\"https://doi.org/10.1145/1278972.1278996\">10.1145/1278972.1278996</a>"},"place":"New York, NY, USA","year":"2007","quality_controlled":"1","publication_identifier":{"isbn":["978-1-59593-694-3"]},"doi":"10.1145/1278972.1278996","title":"Increasing the Reliability of Wireless Sensor Networks with a Distributed Testing Framework","date_created":"2018-04-17T13:34:42Z","author":[{"full_name":"Woehrle, Matthias","last_name":"Woehrle","first_name":"Matthias"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Jan","full_name":"Beutel, Jan","last_name":"Beutel"},{"first_name":"Lothar","full_name":"Thiele, Lothar","last_name":"Thiele"}],"date_updated":"2023-09-26T14:00:38Z","publisher":"ACM"},{"department":[{"_id":"672"}],"user_id":"5786","_id":"38784","language":[{"iso":"eng"}],"keyword":["Classification tree analysis","System testing","Embedded system","Safety","Automatic testing","Automation"],"publication":"Proceedings of the Design Automation & Test in Europe Conference","type":"conference","status":"public","abstract":[{"lang":"eng","text":"This article presents the classification tree method for functional verification to close the gap from the specification of a test plan to SystemVerilog (Chandra and Chakrabarty, 2001) test bench generation. Our method supports the systematic development of test configurations and is based on the classification tree method for embedded systems (CTM/ES) (Chakrabarty et al., 2000) extending CTM/ES for random test generation as well as for functional coverage and property specification"}],"author":[{"first_name":"Alexander","full_name":"Krupp, Alexander","last_name":"Krupp"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"}],"date_created":"2023-01-24T08:06:09Z","publisher":"IEEE","date_updated":"2023-01-24T08:06:14Z","doi":"10.1109/DATE.2006.243902","title":"Classification Trees for Functional Coverage and Random Test Generation","publication_identifier":{"isbn":["3-9810801-1-4"]},"citation":{"ieee":"A. Krupp and W. Müller, “Classification Trees for Functional Coverage and Random Test Generation,” 2006, doi: <a href=\"https://doi.org/10.1109/DATE.2006.243902\">10.1109/DATE.2006.243902</a>.","chicago":"Krupp, Alexander, and Wolfgang Müller. “Classification Trees for Functional Coverage and Random Test Generation.” In <i>Proceedings of the Design Automation &#38; Test in Europe Conference</i>. Munich, Germany: IEEE, 2006. <a href=\"https://doi.org/10.1109/DATE.2006.243902\">https://doi.org/10.1109/DATE.2006.243902</a>.","ama":"Krupp A, Müller W. Classification Trees for Functional Coverage and Random Test Generation. In: <i>Proceedings of the Design Automation &#38; Test in Europe Conference</i>. IEEE; 2006. doi:<a href=\"https://doi.org/10.1109/DATE.2006.243902\">10.1109/DATE.2006.243902</a>","apa":"Krupp, A., &#38; Müller, W. (2006). Classification Trees for Functional Coverage and Random Test Generation. <i>Proceedings of the Design Automation &#38; Test in Europe Conference</i>. <a href=\"https://doi.org/10.1109/DATE.2006.243902\">https://doi.org/10.1109/DATE.2006.243902</a>","bibtex":"@inproceedings{Krupp_Müller_2006, place={Munich, Germany}, title={Classification Trees for Functional Coverage and Random Test Generation}, DOI={<a href=\"https://doi.org/10.1109/DATE.2006.243902\">10.1109/DATE.2006.243902</a>}, booktitle={Proceedings of the Design Automation &#38; Test in Europe Conference}, publisher={IEEE}, author={Krupp, Alexander and Müller, Wolfgang}, year={2006} }","mla":"Krupp, Alexander, and Wolfgang Müller. “Classification Trees for Functional Coverage and Random Test Generation.” <i>Proceedings of the Design Automation &#38; Test in Europe Conference</i>, IEEE, 2006, doi:<a href=\"https://doi.org/10.1109/DATE.2006.243902\">10.1109/DATE.2006.243902</a>.","short":"A. Krupp, W. Müller, in: Proceedings of the Design Automation &#38; Test in Europe Conference, IEEE, Munich, Germany, 2006."},"year":"2006","place":"Munich, Germany"},{"doi":"10.1109/DATE.2005.20","title":"A Model-Based Approach for Executable Specification on Reconfigurable Hardware","author":[{"last_name":"Schattkowsky","full_name":"Schattkowsky, Tim","first_name":"Tim"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"first_name":"Achim","last_name":"Rettberg","full_name":"Rettberg, Achim"}],"date_created":"2023-01-24T08:10:40Z","publisher":"IEEE","date_updated":"2023-01-24T08:10:44Z","citation":{"apa":"Schattkowsky, T., Müller, W., &#38; Rettberg, A. (2005). A Model-Based Approach for Executable Specification on Reconfigurable Hardware. <i>Proceedings of DATE’05</i>. <a href=\"https://doi.org/10.1109/DATE.2005.20\">https://doi.org/10.1109/DATE.2005.20</a>","short":"T. Schattkowsky, W. Müller, A. Rettberg, in: Proceedings of DATE’05, IEEE, Munich, Germany , 2005.","mla":"Schattkowsky, Tim, et al. “A Model-Based Approach for Executable Specification on Reconfigurable Hardware.” <i>Proceedings of DATE’05</i>, IEEE, 2005, doi:<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>.","bibtex":"@inproceedings{Schattkowsky_Müller_Rettberg_2005, place={Munich, Germany }, title={A Model-Based Approach for Executable Specification on Reconfigurable Hardware}, DOI={<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>}, booktitle={Proceedings of DATE’05}, publisher={IEEE}, author={Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}, year={2005} }","chicago":"Schattkowsky, Tim, Wolfgang Müller, and Achim Rettberg. “A Model-Based Approach for Executable Specification on Reconfigurable Hardware.” In <i>Proceedings of DATE’05</i>. Munich, Germany : IEEE, 2005. <a href=\"https://doi.org/10.1109/DATE.2005.20\">https://doi.org/10.1109/DATE.2005.20</a>.","ieee":"T. Schattkowsky, W. Müller, and A. Rettberg, “A Model-Based Approach for Executable Specification on Reconfigurable Hardware,” 2005, doi: <a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>.","ama":"Schattkowsky T, Müller W, Rettberg A. A Model-Based Approach for Executable Specification on Reconfigurable Hardware. In: <i>Proceedings of DATE’05</i>. IEEE; 2005. doi:<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>"},"year":"2005","place":"Munich, Germany ","publication_identifier":{"isbn":["0-7695-2288-2"]},"language":[{"iso":"eng"}],"keyword":["Hardware","Unified modeling language","Virtual machining","Object oriented modeling","Field programmable gate arrays","Java","Microcontrollers","Embedded software","Real time systems","Documentation"],"department":[{"_id":"672"}],"user_id":"5786","_id":"39029","status":"public","abstract":[{"lang":"eng","text":"UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller."}],"publication":"Proceedings of DATE’05","type":"conference"},{"year":"2005","place":"Las Vegas, NV","citation":{"chicago":"Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded Systems.” In <i>Proceedings of ISNG 05</i>. Las Vegas, NV, 2005.","ieee":"T. Schattkowsky and W. Müller, “A UML Virtual Machine for Embedded Systems,” 2005.","ama":"Schattkowsky T, Müller W. A UML Virtual Machine for Embedded Systems. In: <i>Proceedings of ISNG 05</i>. ; 2005.","apa":"Schattkowsky, T., &#38; Müller, W. (2005). A UML Virtual Machine for Embedded Systems. <i>Proceedings of ISNG 05</i>.","mla":"Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded Systems.” <i>Proceedings of ISNG 05</i>, 2005.","short":"T. Schattkowsky, W. Müller, in: Proceedings of ISNG 05, Las Vegas, NV, 2005.","bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Las Vegas, NV}, title={A UML Virtual Machine for Embedded Systems}, booktitle={Proceedings of ISNG 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }"},"title":"A UML Virtual Machine for Embedded Systems","date_updated":"2023-01-24T08:12:26Z","date_created":"2023-01-24T08:12:20Z","author":[{"full_name":"Schattkowsky, Tim","last_name":"Schattkowsky","first_name":"Tim"},{"first_name":"Wolfgang","id":"16243","full_name":"Müller, Wolfgang","last_name":"Müller"}],"abstract":[{"text":"StateCharts are well accepted for embedded systems\r\nspecification for various applications. However, for the\r\nspecification of complex systems they have several\r\nlimitations. In this article, we present a novel approach to\r\nefficiently execute an UML 2.0 subset for embedded real-\r\ntime systems implementation with focus on hardware\r\ninterrupts, software exceptions, and timeouts. We\r\nintroduce a UML Virtual Machine, which directly\r\nexecutes sequence diagrams, which are embedded into\r\nhierarchically structured state transition diagrams.\r\nWhereas state diagrams are directly executed as\r\nEmbedded State Machines (ESMs), sequence diagrams\r\nare translated into UVM Bytecode. The final UVM\r\nexecution is performed by the interaction of the ESM and\r\nthe Bytecode Interpreter. Due to our completely model-\r\nbased approach, the UVM runtime kernel is easily\r\nadaptable and scalable to different scheduling and\r\nmemory management strategies.","lang":"eng"}],"status":"public","type":"conference","publication":"Proceedings of ISNG 05","keyword":["UML","Executable Models","Hardware/Software Co-design","Virtual Machine","Embedded Systems"],"language":[{"iso":"eng"}],"_id":"39030","user_id":"5786","department":[{"_id":"672"}]},{"publication":"Proceedings of VL/HCC 05","type":"conference","status":"public","abstract":[{"text":"Executable UML models are nowadays gaining interest in embedded systems design. This domain is strongly devoted to the modeling of reactive behavior using StateChart variants. In this context, the direct execution of UML state machines is an interesting alternative to native code generation approaches since it significantly increases portability. However, fully featured UML 2.0 State Machines may contain a broad set of features with complex execution semantics that differ significantly from other StateChart variants. This makes their direct execution complex and inefficient. In this paper, we demonstrate how such state machines can be represented using a small subset of the UML state machine features that enables efficient execution. We describe the necessary model transformations in terms of graph transformations and discuss the underlying semantics and implications for execution.","lang":"eng"}],"department":[{"_id":"672"}],"user_id":"5786","_id":"39032","language":[{"iso":"eng"}],"keyword":["Unified modeling language","Software design","Virtual machining","Embedded system","Programming","Documentation","Hardware","Computer languages","Operating systems","Runtime"],"publication_identifier":{"isbn":["0-7695-2443-5"]},"citation":{"apa":"Schattkowsky, T., &#38; Müller, W. (2005). Transformation of UML State Machines for Direct Execution. <i>Proceedings of VL/HCC 05</i>. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>","short":"T. Schattkowsky, W. Müller, in: Proceedings of VL/HCC 05, Dallas, TX, USA, 2005.","bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Dallas, TX, USA}, title={Transformation of UML State Machines for Direct Execution}, DOI={<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>}, booktitle={Proceedings of VL/HCC 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }","mla":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” <i>Proceedings of VL/HCC 05</i>, 2005, doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>.","chicago":"Schattkowsky, Tim, and Wolfgang Müller. “Transformation of UML State Machines for Direct Execution.” In <i>Proceedings of VL/HCC 05</i>. Dallas, TX, USA, 2005. <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">https://doi.org/10.1109/VLHCC.2005.64</a>.","ieee":"T. Schattkowsky and W. Müller, “Transformation of UML State Machines for Direct Execution,” 2005, doi: <a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>.","ama":"Schattkowsky T, Müller W. Transformation of UML State Machines for Direct Execution. In: <i>Proceedings of VL/HCC 05</i>. ; 2005. doi:<a href=\"https://doi.org/10.1109/VLHCC.2005.64\">10.1109/VLHCC.2005.64</a>"},"year":"2005","place":"Dallas, TX, USA","date_created":"2023-01-24T08:18:10Z","author":[{"first_name":"Tim","last_name":"Schattkowsky","full_name":"Schattkowsky, Tim"},{"last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243","first_name":"Wolfgang"}],"date_updated":"2023-01-24T08:18:27Z","doi":"10.1109/VLHCC.2005.64","title":"Transformation of UML State Machines for Direct Execution"},{"publication_identifier":{"isbn":["0-7695-2424-9"]},"year":"2005","place":"Copenhagen, Denmark ","citation":{"short":"J. Groppe, W. Müller, in: Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005), IEEE, Copenhagen, Denmark , 2005.","mla":"Groppe, Jinghua, and Wolfgang Müller. “Profile Management Technology for Smart Customization in Private Home Applications.” <i>Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005)</i>, IEEE, 2005, doi:<a href=\"https://doi.org/10.1109/DEXA.2005.156\">10.1109/DEXA.2005.156</a>.","bibtex":"@inproceedings{Groppe_Müller_2005, place={Copenhagen, Denmark }, title={Profile Management technology for Smart Customization in Private Home Applications}, DOI={<a href=\"https://doi.org/10.1109/DEXA.2005.156\">10.1109/DEXA.2005.156</a>}, booktitle={Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005)}, publisher={IEEE}, author={Groppe, Jinghua and Müller, Wolfgang}, year={2005} }","apa":"Groppe, J., &#38; Müller, W. (2005). Profile Management technology for Smart Customization in Private Home Applications. <i>Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005)</i>. 16th International Workshop on Database and Expert Systems Applications (DEXA’05), Copenhagen, Denmark . <a href=\"https://doi.org/10.1109/DEXA.2005.156\">https://doi.org/10.1109/DEXA.2005.156</a>","ama":"Groppe J, Müller W. Profile Management technology for Smart Customization in Private Home Applications. In: <i>Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005)</i>. IEEE; 2005. doi:<a href=\"https://doi.org/10.1109/DEXA.2005.156\">10.1109/DEXA.2005.156</a>","ieee":"J. Groppe and W. Müller, “Profile Management technology for Smart Customization in Private Home Applications,” presented at the 16th International Workshop on Database and Expert Systems Applications (DEXA’05), Copenhagen, Denmark , 2005, doi: <a href=\"https://doi.org/10.1109/DEXA.2005.156\">10.1109/DEXA.2005.156</a>.","chicago":"Groppe, Jinghua, and Wolfgang Müller. “Profile Management Technology for Smart Customization in Private Home Applications.” In <i>Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005)</i>. Copenhagen, Denmark : IEEE, 2005. <a href=\"https://doi.org/10.1109/DEXA.2005.156\">https://doi.org/10.1109/DEXA.2005.156</a>."},"date_updated":"2023-01-24T08:43:27Z","publisher":"IEEE","author":[{"last_name":"Groppe","full_name":"Groppe, Jinghua","first_name":"Jinghua"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"}],"date_created":"2023-01-24T08:43:21Z","title":"Profile Management technology for Smart Customization in Private Home Applications","doi":"10.1109/DEXA.2005.156","conference":{"name":"16th International Workshop on Database and Expert Systems Applications (DEXA'05)","location":"Copenhagen, Denmark "},"publication":"Proceedings of the 1st International Workshop on Secure and Ubiquitous Networks (SUN-2005)","type":"conference","abstract":[{"lang":"eng","text":"Smart homes provide their users with maximum comfort and convenience. In this paper, we present a profile management framework for situation-dependent customization in smart home environments, which meet the user preferences with given device capabilities. We apply profile processing and evolution methods to customize profiles on the fly and to automatically evolve user preferences. Furthermore, we give a comprehensive study on profile management technology."}],"status":"public","_id":"39052","department":[{"_id":"672"}],"user_id":"5786","keyword":["Technology management","Smart homes","Environmental management","Resource description framework","Data models","Navigation","Mobile computing","Embedded computing","Ubiquitous computing","Mobile communication"],"language":[{"iso":"eng"}]}]