@inproceedings{10780, author = {{Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}}, booktitle = {{12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}}, keywords = {{embedded systems, image sensors, power aware computing, wireless sensor networks, Zynq-based VSN node prototype, computational self-awareness, design approach, platform levels, power consumption, visual sensor networks, visual sensor nodes, Cameras, Hardware, Middleware, Multicore processing, Operating systems, Runtime, Reconfigurable platforms, distributed embedded systems, performance-resource trade-off, self-awareness, visual sensor nodes}}, pages = {{1--8}}, title = {{{Computational self-awareness as design approach for visual sensor nodes}}}, doi = {{10.1109/ReCoSoC.2017.8016147}}, year = {{2017}}, } @inproceedings{10779, author = {{Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}}, booktitle = {{25th International Conference on Field Programmable Logic and Applications (FPL)}}, issn = {{1946-147X}}, keywords = {{embedded systems, field programmable gate arrays, operating systems (computers), scheduling, μC/OS-II, FPGAs, OS foundation, SafeRTOS, Xenomai, chip utilization ration, complex time constraints, embedded systems, hard real-time hardware task allocation, hard real-time hardware task scheduling, hardware-software real-time operating systems, partially reconfigurable field-programmable gate arrays, resource constraints, safety-critical RTOS, Field programmable gate arrays, Hardware, Job shop scheduling, Real-time systems, Shape, Software}}, publisher = {{Imperial College}}, title = {{{Over effective hard real-time hardware tasks scheduling and allocation}}}, doi = {{10.1109/FPL.2015.7293994}}, year = {{2015}}, } @misc{33312, abstract = {{Mechatronic systems are used more than ever in human life. They can be found in a very wide range of domain contexts, from household appliances, and cars, to medical equipment. Mechatronic systems, as a kind of embedded systems, are the tight integration of mechanical and electrical engineering, which embed software systems. Information security of mechatronic systems has not received much attention yet. However, wherever data exists, cyber attacks threaten mechatronic systems. The thesis focuses on the early design stages of the development of mechatronic systems. Model sequence diagrams (MSDs) are used to model requirements with real-time and safety properties. In this thesis, MSDs are extended such that security properties for example authenticity and privacy can be modeled and analyzed automatically.}}, author = {{Schwichtenberg, Bahar}}, keywords = {{Software Architecture, Requirements Engineering, Embedded Systems}}, title = {{{Early Prediction of Security Properties for Mechatronic Systems}}}, year = {{2015}}, } @inproceedings{10677, author = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}}, booktitle = {{2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}}, keywords = {{Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}}, pages = {{31--37}}, title = {{{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}}, doi = {{10.1109/ICES.2014.7008719}}, year = {{2014}}, } @inproceedings{39030, abstract = {{StateCharts are well accepted for embedded systems specification for various applications. However, for the specification of complex systems they have several limitations. In this article, we present a novel approach to efficiently execute an UML 2.0 subset for embedded real- time systems implementation with focus on hardware interrupts, software exceptions, and timeouts. We introduce a UML Virtual Machine, which directly executes sequence diagrams, which are embedded into hierarchically structured state transition diagrams. Whereas state diagrams are directly executed as Embedded State Machines (ESMs), sequence diagrams are translated into UVM Bytecode. The final UVM execution is performed by the interaction of the ESM and the Bytecode Interpreter. Due to our completely model- based approach, the UVM runtime kernel is easily adaptable and scalable to different scheduling and memory management strategies.}}, author = {{Schattkowsky, Tim and Müller, Wolfgang}}, booktitle = {{Proceedings of ISNG 05}}, keywords = {{UML, Executable Models, Hardware/Software Co-design, Virtual Machine, Embedded Systems}}, title = {{{A UML Virtual Machine for Embedded Systems}}}, year = {{2005}}, }