[{"date_updated":"2022-01-06T06:50:50Z","_id":"10780","doi":"10.1109/ReCoSoC.2017.8016147","language":[{"iso":"eng"}],"citation":{"bibtex":"@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational self-awareness as design approach for visual sensor nodes}, DOI={10.1109/ReCoSoC.2017.8016147}, booktitle={12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }","mla":"Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8, doi:10.1109/ReCoSoC.2017.8016147.","apa":"Guettatfi, Z., Hübner, P., Platzner, M., & Rinner, B. (2017). Computational self-awareness as design approach for visual sensor nodes. In 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) (pp. 1–8). https://doi.org/10.1109/ReCoSoC.2017.8016147","ama":"Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness as design approach for visual sensor nodes. In: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC). ; 2017:1-8. doi:10.1109/ReCoSoC.2017.8016147","chicago":"Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner. “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 1–8, 2017. https://doi.org/10.1109/ReCoSoC.2017.8016147.","ieee":"Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness as design approach for visual sensor nodes,” in 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8.","short":"Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017, pp. 1–8."},"year":"2017","type":"conference","page":"1-8","user_id":"3118","title":"Computational self-awareness as design approach for visual sensor nodes","author":[{"first_name":"Zakarya","full_name":"Guettatfi, Zakarya","last_name":"Guettatfi"},{"last_name":"Hübner","full_name":"Hübner, Philipp","first_name":"Philipp"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"},{"last_name":"Rinner","first_name":"Bernhard","full_name":"Rinner, Bernhard"}],"department":[{"_id":"78"}],"keyword":["embedded systems","image sensors","power aware computing","wireless sensor networks","Zynq-based VSN node prototype","computational self-awareness","design approach","platform levels","power consumption","visual sensor networks","visual sensor nodes","Cameras","Hardware","Middleware","Multicore processing","Operating systems","Runtime","Reconfigurable platforms","distributed embedded systems","performance-resource trade-off","self-awareness","visual sensor nodes"],"publication":"12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","status":"public","date_created":"2019-07-10T12:13:15Z"},{"_id":"10779","date_updated":"2022-01-06T06:50:50Z","doi":"10.1109/FPL.2015.7293994","citation":{"ama":"Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College; 2015. doi:10.1109/FPL.2015.7293994","apa":"Guettatfi, Z., Kermia, O., & Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College. https://doi.org/10.1109/FPL.2015.7293994","chicago":"Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In 25th International Conference on Field Programmable Logic and Applications (FPL). Imperial College, 2015. https://doi.org/10.1109/FPL.2015.7293994.","bibtex":"@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={10.1109/FPL.2015.7293994}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }","mla":"Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015, doi:10.1109/FPL.2015.7293994.","short":"Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.","ieee":"Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in 25th International Conference on Field Programmable Logic and Applications (FPL), 2015."},"type":"conference","year":"2015","language":[{"iso":"eng"}],"extern":"1","title":"Over effective hard real-time hardware tasks scheduling and allocation","user_id":"398","publisher":"Imperial College","author":[{"last_name":"Guettatfi","full_name":"Guettatfi, Zakarya","first_name":"Zakarya"},{"first_name":"Omar","full_name":"Kermia, Omar","last_name":"Kermia"},{"first_name":"Abdelhakim","full_name":"Khouas, Abdelhakim","last_name":"Khouas"}],"keyword":["embedded systems","field programmable gate arrays","operating systems (computers)","scheduling","μC/OS-II","FPGAs","OS foundation","SafeRTOS","Xenomai","chip utilization ration","complex time constraints","embedded systems","hard real-time hardware task allocation","hard real-time hardware task scheduling","hardware-software real-time operating systems","partially reconfigurable field-programmable gate arrays","resource constraints","safety-critical RTOS","Field programmable gate arrays","Hardware","Job shop scheduling","Real-time systems","Shape","Software"],"department":[{"_id":"78"}],"publication":"25th International Conference on Field Programmable Logic and Applications (FPL)","publication_identifier":{"issn":["1946-147X"]},"status":"public","date_created":"2019-07-10T12:11:36Z"},{"publication_status":"published","status":"public","has_accepted_license":"1","date_created":"2022-09-09T11:42:25Z","author":[{"first_name":"Bahar","full_name":"Schwichtenberg, Bahar","last_name":"Schwichtenberg","id":"36399"}],"keyword":["Software Architecture","Requirements Engineering","Embedded Systems"],"file_date_updated":"2022-12-30T22:10:51Z","file":[{"file_name":"Bahar_Jazayeri_Masterarbeit.pdf","date_created":"2022-12-30T22:10:51Z","access_level":"closed","file_size":11423528,"file_id":"35068","creator":"bahareh","date_updated":"2022-12-30T22:10:51Z","content_type":"application/pdf","success":1,"relation":"main_file"}],"title":"Early Prediction of Security Properties for Mechatronic Systems","ddc":["000"],"user_id":"36399","extern":"1","abstract":[{"text":"Mechatronic systems are used more than ever in human life. They can be found in a very wide range of domain contexts, from household appliances, and cars, to medical equipment. Mechatronic systems, as a kind of embedded systems, are the tight integration of mechanical and electrical engineering, which embed software systems. Information security of mechatronic systems has not received much attention yet. However, wherever data exists, cyber attacks threaten mechatronic systems.\r\n\r\nThe thesis focuses on the early design stages of the development of mechatronic systems. Model sequence diagrams (MSDs) are used to model requirements with real-time and safety properties. In this thesis, MSDs are extended such that security properties for example authenticity and privacy can be modeled and analyzed automatically.","lang":"eng"}],"type":"mastersthesis","year":"2015","citation":{"ieee":"B. Schwichtenberg, Early Prediction of Security Properties for Mechatronic Systems. 2015.","short":"B. Schwichtenberg, Early Prediction of Security Properties for Mechatronic Systems, 2015.","bibtex":"@book{Schwichtenberg_2015, title={Early Prediction of Security Properties for Mechatronic Systems}, author={Schwichtenberg, Bahar}, year={2015} }","mla":"Schwichtenberg, Bahar. Early Prediction of Security Properties for Mechatronic Systems. 2015.","chicago":"Schwichtenberg, Bahar. Early Prediction of Security Properties for Mechatronic Systems, 2015.","ama":"Schwichtenberg B. Early Prediction of Security Properties for Mechatronic Systems.; 2015.","apa":"Schwichtenberg, B. (2015). Early Prediction of Security Properties for Mechatronic Systems."},"language":[{"iso":"eng"}],"_id":"33312","date_updated":"2022-12-30T22:12:13Z"},{"_id":"10677","date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/ICES.2014.7008719","language":[{"iso":"eng"}],"page":"31-37","year":"2014","citation":{"short":"N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.","ama":"Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719","apa":"Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }","mla":"Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37, doi:10.1109/ICES.2014.7008719."},"type":"conference","user_id":"3118","title":"Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure","department":[{"_id":"78"}],"keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"],"publication":"2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)","author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2019-07-10T11:23:00Z","status":"public"},{"language":[{"iso":"eng"}],"year":"2005","citation":{"apa":"Schattkowsky, T., & Müller, W. (2005). A UML Virtual Machine for Embedded Systems. Proceedings of ISNG 05.","ama":"Schattkowsky T, Müller W. A UML Virtual Machine for Embedded Systems. In: Proceedings of ISNG 05. ; 2005.","chicago":"Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded Systems.” In Proceedings of ISNG 05. Las Vegas, NV, 2005.","bibtex":"@inproceedings{Schattkowsky_Müller_2005, place={Las Vegas, NV}, title={A UML Virtual Machine for Embedded Systems}, booktitle={Proceedings of ISNG 05}, author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }","mla":"Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded Systems.” Proceedings of ISNG 05, 2005.","short":"T. Schattkowsky, W. Müller, in: Proceedings of ISNG 05, Las Vegas, NV, 2005.","ieee":"T. Schattkowsky and W. Müller, “A UML Virtual Machine for Embedded Systems,” 2005."},"type":"conference","date_updated":"2023-01-24T08:12:26Z","_id":"39030","status":"public","date_created":"2023-01-24T08:12:20Z","author":[{"full_name":"Schattkowsky, Tim","first_name":"Tim","last_name":"Schattkowsky"},{"last_name":"Müller","id":"16243","first_name":"Wolfgang","full_name":"Müller, Wolfgang"}],"department":[{"_id":"672"}],"keyword":["UML","Executable Models","Hardware/Software Co-design","Virtual Machine","Embedded Systems"],"publication":"Proceedings of ISNG 05","user_id":"5786","title":"A UML Virtual Machine for Embedded Systems","place":"Las Vegas, NV","abstract":[{"text":"StateCharts are well accepted for embedded systems\r\nspecification for various applications. However, for the\r\nspecification of complex systems they have several\r\nlimitations. In this article, we present a novel approach to\r\nefficiently execute an UML 2.0 subset for embedded real-\r\ntime systems implementation with focus on hardware\r\ninterrupts, software exceptions, and timeouts. We\r\nintroduce a UML Virtual Machine, which directly\r\nexecutes sequence diagrams, which are embedded into\r\nhierarchically structured state transition diagrams.\r\nWhereas state diagrams are directly executed as\r\nEmbedded State Machines (ESMs), sequence diagrams\r\nare translated into UVM Bytecode. The final UVM\r\nexecution is performed by the interaction of the ESM and\r\nthe Bytecode Interpreter. Due to our completely model-\r\nbased approach, the UVM runtime kernel is easily\r\nadaptable and scalable to different scheduling and\r\nmemory management strategies.","lang":"eng"}]}]