---
_id: '10780'
author:
- first_name: Zakarya
  full_name: Guettatfi, Zakarya
  last_name: Guettatfi
- first_name: Philipp
  full_name: Hübner, Philipp
  last_name: Hübner
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
- first_name: Bernhard
  full_name: Rinner, Bernhard
  last_name: Rinner
citation:
  ama: 'Guettatfi Z, Hübner P, Platzner M, Rinner B. Computational self-awareness
    as design approach for visual sensor nodes. In: <i>12th International Symposium
    on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)</i>. ; 2017:1-8.
    doi:<a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">10.1109/ReCoSoC.2017.8016147</a>'
  apa: Guettatfi, Z., Hübner, P., Platzner, M., &#38; Rinner, B. (2017). Computational
    self-awareness as design approach for visual sensor nodes. In <i>12th International
    Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>
    (pp. 1–8). <a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>
  bibtex: '@inproceedings{Guettatfi_Hübner_Platzner_Rinner_2017, title={Computational
    self-awareness as design approach for visual sensor nodes}, DOI={<a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">10.1109/ReCoSoC.2017.8016147</a>},
    booktitle={12th International Symposium on Reconfigurable Communication-centric
    Systems-on-Chip (ReCoSoC)}, author={Guettatfi, Zakarya and Hübner, Philipp and
    Platzner, Marco and Rinner, Bernhard}, year={2017}, pages={1–8} }'
  chicago: Guettatfi, Zakarya, Philipp Hübner, Marco Platzner, and Bernhard Rinner.
    “Computational Self-Awareness as Design Approach for Visual Sensor Nodes.” In
    <i>12th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip
    (ReCoSoC)</i>, 1–8, 2017. <a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">https://doi.org/10.1109/ReCoSoC.2017.8016147</a>.
  ieee: Z. Guettatfi, P. Hübner, M. Platzner, and B. Rinner, “Computational self-awareness
    as design approach for visual sensor nodes,” in <i>12th International Symposium
    on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)</i>, 2017, pp.
    1–8.
  mla: Guettatfi, Zakarya, et al. “Computational Self-Awareness as Design Approach
    for Visual Sensor Nodes.” <i>12th International Symposium on Reconfigurable Communication-Centric
    Systems-on-Chip (ReCoSoC)</i>, 2017, pp. 1–8, doi:<a href="https://doi.org/10.1109/ReCoSoC.2017.8016147">10.1109/ReCoSoC.2017.8016147</a>.
  short: 'Z. Guettatfi, P. Hübner, M. Platzner, B. Rinner, in: 12th International
    Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC), 2017,
    pp. 1–8.'
date_created: 2019-07-10T12:13:15Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ReCoSoC.2017.8016147
keyword:
- embedded systems
- image sensors
- power aware computing
- wireless sensor networks
- Zynq-based VSN node prototype
- computational self-awareness
- design approach
- platform levels
- power consumption
- visual sensor networks
- visual sensor nodes
- Cameras
- Hardware
- Middleware
- Multicore processing
- Operating systems
- Runtime
- Reconfigurable platforms
- distributed embedded systems
- performance-resource trade-off
- self-awareness
- visual sensor nodes
language:
- iso: eng
page: 1-8
publication: 12th International Symposium on Reconfigurable Communication-centric
  Systems-on-Chip (ReCoSoC)
status: public
title: Computational self-awareness as design approach for visual sensor nodes
type: conference
user_id: '3118'
year: '2017'
...
---
_id: '10779'
author:
- first_name: Zakarya
  full_name: Guettatfi, Zakarya
  last_name: Guettatfi
- first_name: Omar
  full_name: Kermia, Omar
  last_name: Kermia
- first_name: Abdelhakim
  full_name: Khouas, Abdelhakim
  last_name: Khouas
citation:
  ama: 'Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks
    scheduling and allocation. In: <i>25th International Conference on Field Programmable
    Logic and Applications (FPL)</i>. Imperial College; 2015. doi:<a href="https://doi.org/10.1109/FPL.2015.7293994">10.1109/FPL.2015.7293994</a>'
  apa: Guettatfi, Z., Kermia, O., &#38; Khouas, A. (2015). Over effective hard real-time
    hardware tasks scheduling and allocation. In <i>25th International Conference
    on Field Programmable Logic and Applications (FPL)</i>. Imperial College. <a href="https://doi.org/10.1109/FPL.2015.7293994">https://doi.org/10.1109/FPL.2015.7293994</a>
  bibtex: '@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard
    real-time hardware tasks scheduling and allocation}, DOI={<a href="https://doi.org/10.1109/FPL.2015.7293994">10.1109/FPL.2015.7293994</a>},
    booktitle={25th International Conference on Field Programmable Logic and Applications
    (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar
    and Khouas, Abdelhakim}, year={2015} }'
  chicago: Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective
    Hard Real-Time Hardware Tasks Scheduling and Allocation.” In <i>25th International
    Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College,
    2015. <a href="https://doi.org/10.1109/FPL.2015.7293994">https://doi.org/10.1109/FPL.2015.7293994</a>.
  ieee: Z. Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware
    tasks scheduling and allocation,” in <i>25th International Conference on Field
    Programmable Logic and Applications (FPL)</i>, 2015.
  mla: Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling
    and Allocation.” <i>25th International Conference on Field Programmable Logic
    and Applications (FPL)</i>, Imperial College, 2015, doi:<a href="https://doi.org/10.1109/FPL.2015.7293994">10.1109/FPL.2015.7293994</a>.
  short: 'Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on
    Field Programmable Logic and Applications (FPL), Imperial College, 2015.'
date_created: 2019-07-10T12:11:36Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/FPL.2015.7293994
extern: '1'
keyword:
- embedded systems
- field programmable gate arrays
- operating systems (computers)
- scheduling
- μC/OS-II
- FPGAs
- OS foundation
- SafeRTOS
- Xenomai
- chip utilization ration
- complex time constraints
- embedded systems
- hard real-time hardware task allocation
- hard real-time hardware task scheduling
- hardware-software real-time operating systems
- partially reconfigurable field-programmable gate arrays
- resource constraints
- safety-critical RTOS
- Field programmable gate arrays
- Hardware
- Job shop scheduling
- Real-time systems
- Shape
- Software
language:
- iso: eng
publication: 25th International Conference on Field Programmable Logic and Applications
  (FPL)
publication_identifier:
  issn:
  - 1946-147X
publisher: Imperial College
status: public
title: Over effective hard real-time hardware tasks scheduling and allocation
type: conference
user_id: '398'
year: '2015'
...
---
_id: '33312'
abstract:
- lang: eng
  text: "Mechatronic systems are used more than ever in human life. They can be found
    in a very wide range of domain contexts, from household appliances, and cars,
    to medical equipment. Mechatronic systems, as a kind of embedded systems, are
    the tight integration of mechanical and electrical engineering, which embed software
    systems. Information security of mechatronic systems has not received much attention
    yet. However, wherever data exists, cyber attacks threaten mechatronic systems.\r\n\r\nThe
    thesis focuses on the early design stages of the development of mechatronic systems.
    Model sequence diagrams (MSDs) are used to model requirements with real-time and
    safety properties. In this thesis, MSDs are extended such that security properties
    for example authenticity and privacy can be modeled and analyzed automatically."
author:
- first_name: Bahar
  full_name: Schwichtenberg, Bahar
  id: '36399'
  last_name: Schwichtenberg
citation:
  ama: Schwichtenberg B. <i>Early Prediction of Security Properties for Mechatronic
    Systems</i>.; 2015.
  apa: Schwichtenberg, B. (2015). <i>Early Prediction of Security Properties for Mechatronic
    Systems</i>.
  bibtex: '@book{Schwichtenberg_2015, title={Early Prediction of Security Properties
    for Mechatronic Systems}, author={Schwichtenberg, Bahar}, year={2015} }'
  chicago: Schwichtenberg, Bahar. <i>Early Prediction of Security Properties for Mechatronic
    Systems</i>, 2015.
  ieee: B. Schwichtenberg, <i>Early Prediction of Security Properties for Mechatronic
    Systems</i>. 2015.
  mla: Schwichtenberg, Bahar. <i>Early Prediction of Security Properties for Mechatronic
    Systems</i>. 2015.
  short: B. Schwichtenberg, Early Prediction of Security Properties for Mechatronic
    Systems, 2015.
date_created: 2022-09-09T11:42:25Z
date_updated: 2022-12-30T22:12:13Z
ddc:
- '000'
extern: '1'
file:
- access_level: closed
  content_type: application/pdf
  creator: bahareh
  date_created: 2022-12-30T22:10:51Z
  date_updated: 2022-12-30T22:10:51Z
  file_id: '35068'
  file_name: Bahar_Jazayeri_Masterarbeit.pdf
  file_size: 11423528
  relation: main_file
  success: 1
file_date_updated: 2022-12-30T22:10:51Z
has_accepted_license: '1'
keyword:
- Software Architecture
- Requirements Engineering
- Embedded Systems
language:
- iso: eng
publication_status: published
status: public
title: Early Prediction of Security Properties for Mechatronic Systems
type: mastersthesis
user_id: '36399'
year: '2015'
...
---
_id: '10677'
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable
    multi-core infrastructure. In: <i>2014 {IEEE} Intl. Conf. on Evolvable Systems
    (ICES)</i>. ; 2014:31-37. doi:<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>'
  apa: 'Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). Towards self-adaptive caches:
    A run-time reconfigurable multi-core infrastructure. In <i>2014 {IEEE} Intl. Conf.
    on Evolvable Systems (ICES)</i> (pp. 31–37). <a href="https://doi.org/10.1109/ICES.2014.7008719">https://doi.org/10.1109/ICES.2014.7008719</a>'
  bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive
    caches: A run-time reconfigurable multi-core infrastructure}, DOI={<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>},
    booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam
    and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }'
  chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches:
    A Run-Time Reconfigurable Multi-Core Infrastructure.” In <i>2014 {IEEE} Intl.
    Conf. on Evolvable Systems (ICES)</i>, 31–37, 2014. <a href="https://doi.org/10.1109/ICES.2014.7008719">https://doi.org/10.1109/ICES.2014.7008719</a>.'
  ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time
    reconfigurable multi-core infrastructure,” in <i>2014 {IEEE} Intl. Conf. on Evolvable
    Systems (ICES)</i>, 2014, pp. 31–37.'
  mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core
    Infrastructure.” <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014,
    pp. 31–37, doi:<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>.'
  short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable
    Systems (ICES), 2014, pp. 31–37.'
date_created: 2019-07-10T11:23:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/ICES.2014.7008719
keyword:
- Linux
- cache storage
- embedded systems
- granular computing
- multiprocessing systems
- reconfigurable architectures
- Leon3 SPARe processor
- custom logic events
- evolvable-self-adaptable processor cache
- fine granular profiling
- integer unit events
- measurement infrastructure
- microarchitectural events
- multicore embedded system
- perf_event standard Linux performance measurement interface
- processor properties
- run-time reconfigurable memory-to-cache address mapping engine
- run-time reconfigurable multicore infrastructure
- split-level caching
- Field programmable gate arrays
- Frequency locked loops
- Irrigation
- Phasor measurement units
- Registers
- Weaving
language:
- iso: eng
page: 31-37
publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)
status: public
title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '39030'
abstract:
- lang: eng
  text: "StateCharts are well accepted for embedded systems\r\nspecification for various
    applications. However, for the\r\nspecification of complex systems they have several\r\nlimitations.
    In this article, we present a novel approach to\r\nefficiently execute an UML
    2.0 subset for embedded real-\r\ntime systems implementation with focus on hardware\r\ninterrupts,
    software exceptions, and timeouts. We\r\nintroduce a UML Virtual Machine, which
    directly\r\nexecutes sequence diagrams, which are embedded into\r\nhierarchically
    structured state transition diagrams.\r\nWhereas state diagrams are directly executed
    as\r\nEmbedded State Machines (ESMs), sequence diagrams\r\nare translated into
    UVM Bytecode. The final UVM\r\nexecution is performed by the interaction of the
    ESM and\r\nthe Bytecode Interpreter. Due to our completely model-\r\nbased approach,
    the UVM runtime kernel is easily\r\nadaptable and scalable to different scheduling
    and\r\nmemory management strategies."
author:
- first_name: Tim
  full_name: Schattkowsky, Tim
  last_name: Schattkowsky
- first_name: Wolfgang
  full_name: Müller, Wolfgang
  id: '16243'
  last_name: Müller
citation:
  ama: 'Schattkowsky T, Müller W. A UML Virtual Machine for Embedded Systems. In:
    <i>Proceedings of ISNG 05</i>. ; 2005.'
  apa: Schattkowsky, T., &#38; Müller, W. (2005). A UML Virtual Machine for Embedded
    Systems. <i>Proceedings of ISNG 05</i>.
  bibtex: '@inproceedings{Schattkowsky_Müller_2005, place={Las Vegas, NV}, title={A
    UML Virtual Machine for Embedded Systems}, booktitle={Proceedings of ISNG 05},
    author={Schattkowsky, Tim and Müller, Wolfgang}, year={2005} }'
  chicago: Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded
    Systems.” In <i>Proceedings of ISNG 05</i>. Las Vegas, NV, 2005.
  ieee: T. Schattkowsky and W. Müller, “A UML Virtual Machine for Embedded Systems,”
    2005.
  mla: Schattkowsky, Tim, and Wolfgang Müller. “A UML Virtual Machine for Embedded
    Systems.” <i>Proceedings of ISNG 05</i>, 2005.
  short: 'T. Schattkowsky, W. Müller, in: Proceedings of ISNG 05, Las Vegas, NV, 2005.'
date_created: 2023-01-24T08:12:20Z
date_updated: 2023-01-24T08:12:26Z
department:
- _id: '672'
keyword:
- UML
- Executable Models
- Hardware/Software Co-design
- Virtual Machine
- Embedded Systems
language:
- iso: eng
place: Las Vegas, NV
publication: Proceedings of ISNG 05
status: public
title: A UML Virtual Machine for Embedded Systems
type: conference
user_id: '5786'
year: '2005'
...