@inproceedings{10673,
  author       = {{Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}},
  keywords     = {{cache storage, field programmable gate arrays, multiprocessing systems, parallel architectures, reconfigurable architectures, FPGA, dynamic reconfiguration, evolvable cache mapping, many-core architecture, memory-to-cache address mapping function, microarchitectural optimization, multicore architecture, nature-inspired optimization, parallelization degrees, processor, reconfigurable cache mapping, reconfigurable computing, Field programmable gate arrays, Software, Tuning}},
  pages        = {{1--7}},
  title        = {{{Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}}},
  doi          = {{10.1109/AHS.2015.7231178}},
  year         = {{2015}},
}

@inproceedings{10779,
  author       = {{Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}},
  booktitle    = {{25th International Conference on Field Programmable Logic and Applications (FPL)}},
  issn         = {{1946-147X}},
  keywords     = {{embedded systems, field programmable gate arrays, operating systems (computers), scheduling, μC/OS-II, FPGAs, OS foundation, SafeRTOS, Xenomai, chip utilization ration, complex time constraints, embedded systems, hard real-time hardware task allocation, hard real-time hardware task scheduling, hardware-software real-time operating systems, partially reconfigurable field-programmable gate arrays, resource constraints, safety-critical RTOS, Field programmable gate arrays, Hardware, Job shop scheduling, Real-time systems, Shape, Software}},
  publisher    = {{Imperial College}},
  title        = {{{Over effective hard real-time hardware tasks scheduling and allocation}}},
  doi          = {{10.1109/FPL.2015.7293994}},
  year         = {{2015}},
}

@inproceedings{10677,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}},
  keywords     = {{Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}},
  pages        = {{31--37}},
  title        = {{{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}},
  doi          = {{10.1109/ICES.2014.7008719}},
  year         = {{2014}},
}

@inproceedings{10620,
  author       = {{Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}},
  booktitle    = {{Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}},
  keywords     = {{fault tolerant computing, field programmable gate arrays, logic design, reliability, BYU-LANL tool, DRM tool flow, FPGA based hardware designs, avionic application, device technologies, dynamic reliability management, fault-tolerant operation, hardware designs, reconfiguring reliability levels, space applications, Field programmable gate arrays, Hardware, Redundancy, Reliability engineering, Runtime, Tunneling magnetoresistance}},
  pages        = {{1--6}},
  title        = {{{Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}}},
  doi          = {{10.1109/ReConFig.2013.6732280}},
  year         = {{2013}},
}

@inproceedings{37007,
  abstract     = {{UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.}},
  author       = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Unified modeling language, Field programmable gate arrays, Bridges, Helium, Real time systems, Operating systems, Documentation, Application software, XML, Space exploration}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}}},
  doi          = {{10.1109/DATE.2010.5456990}},
  year         = {{2010}},
}

@inproceedings{6508,
  abstract     = {{In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.}},
  author       = {{Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}},
  isbn         = {{076952866X}},
  keywords     = {{integrated circuit design, hardware evolution, evolutionary hardware design, evolutionary optimizers, hash functions, preengineered circuits, Hardware, Circuits, Design optimization, Visualization, Genetic programming, Genetic mutations, Clustering algorithms, Biological cells, Field programmable gate arrays, Routing}},
  location     = {{Edinburgh, UK}},
  pages        = {{447--454}},
  publisher    = {{IEEE}},
  title        = {{{MOVES: A Modular Framework for Hardware Evolution}}},
  doi          = {{10.1109/ahs.2007.73}},
  year         = {{2007}},
}

@inproceedings{39029,
  abstract     = {{UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.}},
  author       = {{Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}},
  booktitle    = {{Proceedings of DATE’05}},
  isbn         = {{0-7695-2288-2}},
  keywords     = {{Hardware, Unified modeling language, Virtual machining, Object oriented modeling, Field programmable gate arrays, Java, Microcontrollers, Embedded software, Real time systems, Documentation}},
  publisher    = {{IEEE}},
  title        = {{{A Model-Based Approach for Executable Specification on Reconfigurable Hardware}}},
  doi          = {{10.1109/DATE.2005.20}},
  year         = {{2005}},
}