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Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7, doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>.","ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7.","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 1–7, 2015. <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>."},"year":"2015","date_created":"2019-07-10T11:18:00Z","author":[{"last_name":"Ho","full_name":"Ho, Nam","first_name":"Nam"},{"first_name":"Abdullah Fathi","last_name":"Ahmed","full_name":"Ahmed, Abdullah Fathi"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/AHS.2015.7231178","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","publication":"Proc. NASA/ESA Conf. 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Guettatfi, O. Kermia, and A. Khouas, “Over effective hard real-time hardware tasks scheduling and allocation,” in <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, 2015.","chicago":"Guettatfi, Zakarya, Omar Kermia, and Abdelhakim Khouas. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College, 2015. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>.","ama":"Guettatfi Z, Kermia O, Khouas A. Over effective hard real-time hardware tasks scheduling and allocation. In: <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College; 2015. doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>","apa":"Guettatfi, Z., Kermia, O., &#38; Khouas, A. (2015). Over effective hard real-time hardware tasks scheduling and allocation. In <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>. Imperial College. <a href=\"https://doi.org/10.1109/FPL.2015.7293994\">https://doi.org/10.1109/FPL.2015.7293994</a>","bibtex":"@inproceedings{Guettatfi_Kermia_Khouas_2015, title={Over effective hard real-time hardware tasks scheduling and allocation}, DOI={<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>}, booktitle={25th International Conference on Field Programmable Logic and Applications (FPL)}, publisher={Imperial College}, author={Guettatfi, Zakarya and Kermia, Omar and Khouas, Abdelhakim}, year={2015} }","short":"Z. Guettatfi, O. Kermia, A. Khouas, in: 25th International Conference on Field Programmable Logic and Applications (FPL), Imperial College, 2015.","mla":"Guettatfi, Zakarya, et al. “Over Effective Hard Real-Time Hardware Tasks Scheduling and Allocation.” <i>25th International Conference on Field Programmable Logic and Applications (FPL)</i>, Imperial College, 2015, doi:<a href=\"https://doi.org/10.1109/FPL.2015.7293994\">10.1109/FPL.2015.7293994</a>."},"publication_identifier":{"issn":["1946-147X"]},"title":"Over effective hard real-time hardware tasks scheduling and allocation","doi":"10.1109/FPL.2015.7293994","date_updated":"2022-01-06T06:50:50Z","publisher":"Imperial College","date_created":"2019-07-10T12:11:36Z","author":[{"last_name":"Guettatfi","full_name":"Guettatfi, Zakarya","first_name":"Zakarya"},{"last_name":"Kermia","full_name":"Kermia, Omar","first_name":"Omar"},{"full_name":"Khouas, Abdelhakim","last_name":"Khouas","first_name":"Abdelhakim"}]},{"page":"31-37","citation":{"ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37.","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 31–37, 2014. <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>.","ama":"Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>. ; 2014:31-37. doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.","mla":"Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014, pp. 31–37, doi:<a href=\"https://doi.org/10.1109/ICES.2014.7008719\">10.1109/ICES.2014.7008719</a>.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i> (pp. 31–37). <a href=\"https://doi.org/10.1109/ICES.2014.7008719\">https://doi.org/10.1109/ICES.2014.7008719</a>"},"year":"2014","doi":"10.1109/ICES.2014.7008719","title":"Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure","author":[{"full_name":"Ho, Nam","last_name":"Ho","first_name":"Nam"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2019-07-10T11:23:00Z","date_updated":"2022-01-06T06:50:49Z","status":"public","publication":"2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)","type":"conference","language":[{"iso":"eng"}],"keyword":["Linux","cache storage","embedded systems","granular computing","multiprocessing systems","reconfigurable architectures","Leon3 SPARe processor","custom logic events","evolvable-self-adaptable processor cache","fine granular profiling","integer unit events","measurement infrastructure","microarchitectural events","multicore embedded system","perf_event standard Linux performance measurement interface","processor properties","run-time reconfigurable memory-to-cache address mapping engine","run-time reconfigurable multicore infrastructure","split-level caching","Field programmable gate arrays","Frequency locked loops","Irrigation","Phasor measurement units","Registers","Weaving"],"department":[{"_id":"78"}],"user_id":"3118","_id":"10677"},{"keyword":["fault tolerant computing","field programmable gate arrays","logic design","reliability","BYU-LANL tool","DRM tool flow","FPGA based hardware designs","avionic application","device technologies","dynamic reliability management","fault-tolerant operation","hardware designs","reconfiguring reliability levels","space applications","Field programmable gate arrays","Hardware","Redundancy","Reliability engineering","Runtime","Tunneling magnetoresistance"],"language":[{"iso":"eng"}],"_id":"10620","department":[{"_id":"78"}],"user_id":"3118","status":"public","publication":"Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on","type":"conference","title":"Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime","doi":"10.1109/ReConFig.2013.6732280","date_updated":"2022-01-06T06:50:48Z","date_created":"2019-07-10T09:32:57Z","author":[{"last_name":"Anwer","full_name":"Anwer, Jahanzeb","first_name":"Jahanzeb"},{"first_name":"Sebastian","full_name":"Meisner, Sebastian","last_name":"Meisner"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"year":"2013","page":"1-6","citation":{"apa":"Anwer, J., Meisner, S., &#38; Platzner, M. (2013). Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on</i> (pp. 1–6). <a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">https://doi.org/10.1109/ReConFig.2013.6732280</a>","short":"J. Anwer, S. Meisner, M. Platzner, in: Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On, 2013, pp. 1–6.","mla":"Anwer, Jahanzeb, et al. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>, 2013, pp. 1–6, doi:<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>.","bibtex":"@inproceedings{Anwer_Meisner_Platzner_2013, title={Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>}, booktitle={Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on}, author={Anwer, Jahanzeb and Meisner, Sebastian and Platzner, Marco}, year={2013}, pages={1–6} }","chicago":"Anwer, Jahanzeb, Sebastian Meisner, and Marco Platzner. “Dynamic Reliability Management: Reconfiguring Reliability-Levels of Hardware Designs at Runtime.” In <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>, 1–6, 2013. <a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">https://doi.org/10.1109/ReConFig.2013.6732280</a>.","ieee":"J. Anwer, S. Meisner, and M. Platzner, “Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime,” in <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference on</i>, 2013, pp. 1–6.","ama":"Anwer J, Meisner S, Platzner M. Dynamic reliability management: Reconfiguring reliability-levels of hardware designs at runtime. In: <i>Reconfigurable Computing and FPGAs (ReConFig), 2013 International Conference On</i>. ; 2013:1-6. doi:<a href=\"https://doi.org/10.1109/ReConFig.2013.6732280\">10.1109/ReConFig.2013.6732280</a>"}},{"abstract":[{"lang":"eng","text":"UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach."}],"status":"public","type":"conference","publication":"Proceedings of DATE’10","keyword":["Unified modeling language","Field programmable gate arrays","Bridges","Helium","Real time systems","Operating systems","Documentation","Application software","XML","Space exploration"],"language":[{"iso":"eng"}],"_id":"37007","user_id":"5786","department":[{"_id":"672"}],"place":"Dresden","year":"2010","citation":{"chicago":"Mischkalla, Fabian, Da He, and Wolfgang Müller. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” In <i>Proceedings of DATE’10</i>. Dresden: IEEE, 2010. <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">https://doi.org/10.1109/DATE.2010.5456990</a>.","ieee":"F. Mischkalla, D. He, and W. Müller, “Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems,” presented at the 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden, 2010, doi: <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>.","ama":"Mischkalla F, He D, Müller W. Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. In: <i>Proceedings of DATE’10</i>. IEEE; 2010. doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>","apa":"Mischkalla, F., He, D., &#38; Müller, W. (2010). Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems. <i>Proceedings of DATE’10</i>. 2010 Design, Automation &#38; Test in Europe Conference &#38; Exhibition (DATE 2010), Dresden. <a href=\"https://doi.org/10.1109/DATE.2010.5456990\">https://doi.org/10.1109/DATE.2010.5456990</a>","bibtex":"@inproceedings{Mischkalla_He_Müller_2010, place={Dresden}, title={Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}, DOI={<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Mischkalla, Fabian and He, Da and Müller, Wolfgang}, year={2010} }","short":"F. Mischkalla, D. He, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.","mla":"Mischkalla, Fabian, et al. “Closing the Gap between UML-Based Modeling and Simulation of Combined HW/SW Systems.” <i>Proceedings of DATE’10</i>, IEEE, 2010, doi:<a href=\"https://doi.org/10.1109/DATE.2010.5456990\">10.1109/DATE.2010.5456990</a>."},"publication_identifier":{"eisbn":["978-3-9810801-6-2"]},"title":"Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems","doi":"10.1109/DATE.2010.5456990","conference":{"location":"Dresden","name":"2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010)"},"date_updated":"2023-01-17T09:12:44Z","publisher":"IEEE","date_created":"2023-01-17T09:12:35Z","author":[{"last_name":"Mischkalla","full_name":"Mischkalla, Fabian","first_name":"Fabian"},{"first_name":"Da","full_name":"He, Da","last_name":"He"},{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"}]},{"abstract":[{"text":"In this paper, we present a framework that supports experimenting with evolutionary hardware design. We describe the framework's modules for composing evolutionary optimizers and for setting up, controlling, and analyzing experiments. Two case studies demonstrate the usefulness of the framework: evolution of hash functions and evolution based on pre-engineered circuits.","lang":"eng"}],"status":"public","type":"conference","publication":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","keyword":["integrated circuit design","hardware evolution","evolutionary hardware design","evolutionary optimizers","hash functions","preengineered circuits","Hardware","Circuits","Design optimization","Visualization","Genetic programming","Genetic mutations","Clustering algorithms","Biological cells","Field programmable gate arrays","Routing"],"language":[{"iso":"eng"}],"_id":"6508","user_id":"3118","department":[{"_id":"78"}],"year":"2007","citation":{"short":"P. Kaufmann, M. Platzner, in: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), IEEE, 2007, pp. 447–454.","mla":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, IEEE, 2007, pp. 447–54, doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>.","bibtex":"@inproceedings{Kaufmann_Platzner_2007, title={MOVES: A Modular Framework for Hardware Evolution}, DOI={<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>}, booktitle={Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)}, publisher={IEEE}, author={Kaufmann, Paul and Platzner, Marco}, year={2007}, pages={447–454} }","apa":"Kaufmann, P., &#38; Platzner, M. (2007). MOVES: A Modular Framework for Hardware Evolution. In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i> (pp. 447–454). Edinburgh, UK: IEEE. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>","ama":"Kaufmann P, Platzner M. MOVES: A Modular Framework for Hardware Evolution. In: <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>. IEEE; 2007:447-454. doi:<a href=\"https://doi.org/10.1109/ahs.2007.73\">10.1109/ahs.2007.73</a>","chicago":"Kaufmann, Paul, and Marco Platzner. “MOVES: A Modular Framework for Hardware Evolution.” In <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, 447–54. IEEE, 2007. <a href=\"https://doi.org/10.1109/ahs.2007.73\">https://doi.org/10.1109/ahs.2007.73</a>.","ieee":"P. Kaufmann and M. Platzner, “MOVES: A Modular Framework for Hardware Evolution,” in <i>Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)</i>, Edinburgh, UK, 2007, pp. 447–454."},"page":"447-454","publication_status":"published","publication_identifier":{"isbn":["076952866X","9780769528663"]},"title":"MOVES: A Modular Framework for Hardware Evolution","doi":"10.1109/ahs.2007.73","conference":{"name":"Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007)","start_date":"2007-08-05","end_date":"2007-08-08","location":"Edinburgh, UK"},"publisher":"IEEE","date_updated":"2022-01-06T07:03:08Z","date_created":"2019-01-08T09:52:43Z","author":[{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}]},{"abstract":[{"text":"UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.","lang":"eng"}],"status":"public","publication":"Proceedings of DATE’05","type":"conference","keyword":["Hardware","Unified modeling language","Virtual machining","Object oriented modeling","Field programmable gate arrays","Java","Microcontrollers","Embedded software","Real time systems","Documentation"],"language":[{"iso":"eng"}],"_id":"39029","department":[{"_id":"672"}],"user_id":"5786","place":"Munich, Germany ","year":"2005","citation":{"ieee":"T. Schattkowsky, W. Müller, and A. Rettberg, “A Model-Based Approach for Executable Specification on Reconfigurable Hardware,” 2005, doi: <a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>.","chicago":"Schattkowsky, Tim, Wolfgang Müller, and Achim Rettberg. “A Model-Based Approach for Executable Specification on Reconfigurable Hardware.” In <i>Proceedings of DATE’05</i>. Munich, Germany : IEEE, 2005. <a href=\"https://doi.org/10.1109/DATE.2005.20\">https://doi.org/10.1109/DATE.2005.20</a>.","ama":"Schattkowsky T, Müller W, Rettberg A. A Model-Based Approach for Executable Specification on Reconfigurable Hardware. In: <i>Proceedings of DATE’05</i>. IEEE; 2005. doi:<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>","apa":"Schattkowsky, T., Müller, W., &#38; Rettberg, A. (2005). A Model-Based Approach for Executable Specification on Reconfigurable Hardware. <i>Proceedings of DATE’05</i>. <a href=\"https://doi.org/10.1109/DATE.2005.20\">https://doi.org/10.1109/DATE.2005.20</a>","bibtex":"@inproceedings{Schattkowsky_Müller_Rettberg_2005, place={Munich, Germany }, title={A Model-Based Approach for Executable Specification on Reconfigurable Hardware}, DOI={<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>}, booktitle={Proceedings of DATE’05}, publisher={IEEE}, author={Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}, year={2005} }","short":"T. Schattkowsky, W. Müller, A. Rettberg, in: Proceedings of DATE’05, IEEE, Munich, Germany , 2005.","mla":"Schattkowsky, Tim, et al. “A Model-Based Approach for Executable Specification on Reconfigurable Hardware.” <i>Proceedings of DATE’05</i>, IEEE, 2005, doi:<a href=\"https://doi.org/10.1109/DATE.2005.20\">10.1109/DATE.2005.20</a>."},"publication_identifier":{"isbn":["0-7695-2288-2"]},"title":"A Model-Based Approach for Executable Specification on Reconfigurable Hardware","doi":"10.1109/DATE.2005.20","date_updated":"2023-01-24T08:10:44Z","publisher":"IEEE","author":[{"first_name":"Tim","last_name":"Schattkowsky","full_name":"Schattkowsky, Tim"},{"first_name":"Wolfgang","last_name":"Müller","full_name":"Müller, Wolfgang","id":"16243"},{"first_name":"Achim","last_name":"Rettberg","full_name":"Rettberg, Achim"}],"date_created":"2023-01-24T08:10:40Z"}]