[{"abstract":[{"text":"Banks face a 'behavioralization' of their balance sheets since deposit funding increasingly consists of non-maturing deposits with uncertain cash flows exposing banks to asset liability (ALM) risk. Thus, this study examines the behavior of banks’ retail customers regarding non-maturing deposits. Our unique sample comprises the contract and cash flow data for 2.2 million individual contracts from 1991 to 2010. We find that contractual rewards, i.e., qualified interest payments, and government subsidies, effectively stabilize saving behavior and thus bank funding. The probability of an early deposit withdrawal decreases by approximately 40%, and cash flow volatility drops by about 25%. Our findings provide important insights for banks using pricing incentives to steer desired saving patterns for their non-maturing deposit portfolios. Finally, these results are informative regarding the bank liquidity regulations (Basel III) concerning the stability of deposits and the minimum requirements for risk management (European Commission DIRECTIVE 2006/48/EC). ","lang":"eng"}],"status":"public","publication":"Journal of Banking & Finance (VHB-JOURQUAL 4 Ranking A)","type":"journal_article","keyword":["retail saving behavior","non-maturing deposits","deposit funding","contractual rewards","interest rate bonus","saving persistence","cash flow volatility"],"article_type":"original","language":[{"iso":"eng"}],"_id":"4873","department":[{"_id":"275"}],"user_id":"115848","year":"2015","page":"43-61","intvolume":"        51","jel":["G01","G21","G28"],"citation":{"short":"T. Schlueter, S. Sievers, T. Hartmann-Wendels, Journal of Banking &#38; Finance (VHB-JOURQUAL 4 Ranking A) 51 (2015) 43–61.","bibtex":"@article{Schlueter_Sievers_Hartmann-Wendels_2015, title={Bank funding stability, pricing strategies and the guidance of depositors}, volume={51}, DOI={<a href=\"https://doi.org/10.2139/ssrn.2001449\">10.2139/ssrn.2001449</a>}, journal={Journal of Banking &#38; Finance (VHB-JOURQUAL 4 Ranking A)}, author={Schlueter, Tobias and Sievers, Sönke and Hartmann-Wendels, Thomas}, year={2015}, pages={43–61} }","mla":"Schlueter, Tobias, et al. “Bank Funding Stability, Pricing Strategies and the Guidance of Depositors.” <i>Journal of Banking &#38; Finance (VHB-JOURQUAL 4 Ranking A)</i>, vol. 51, 2015, pp. 43–61, doi:<a href=\"https://doi.org/10.2139/ssrn.2001449\">10.2139/ssrn.2001449</a>.","apa":"Schlueter, T., Sievers, S., &#38; Hartmann-Wendels, T. (2015). Bank funding stability, pricing strategies and the guidance of depositors. <i>Journal of Banking &#38; Finance (VHB-JOURQUAL 4 Ranking A)</i>, <i>51</i>, 43–61. <a href=\"https://doi.org/10.2139/ssrn.2001449\">https://doi.org/10.2139/ssrn.2001449</a>","ieee":"T. Schlueter, S. Sievers, and T. Hartmann-Wendels, “Bank funding stability, pricing strategies and the guidance of depositors,” <i>Journal of Banking &#38; Finance (VHB-JOURQUAL 4 Ranking A)</i>, vol. 51, pp. 43–61, 2015, doi: <a href=\"https://doi.org/10.2139/ssrn.2001449\">10.2139/ssrn.2001449</a>.","chicago":"Schlueter, Tobias, Sönke Sievers, and Thomas Hartmann-Wendels. “Bank Funding Stability, Pricing Strategies and the Guidance of Depositors.” <i>Journal of Banking &#38; Finance (VHB-JOURQUAL 4 Ranking A)</i> 51 (2015): 43–61. <a href=\"https://doi.org/10.2139/ssrn.2001449\">https://doi.org/10.2139/ssrn.2001449</a>.","ama":"Schlueter T, Sievers S, Hartmann-Wendels T. Bank funding stability, pricing strategies and the guidance of depositors. <i>Journal of Banking &#38; Finance (VHB-JOURQUAL 4 Ranking A)</i>. 2015;51:43-61. doi:<a href=\"https://doi.org/10.2139/ssrn.2001449\">10.2139/ssrn.2001449</a>"},"quality_controlled":"1","publication_status":"published","title":"Bank funding stability, pricing strategies and the guidance of depositors","doi":"10.2139/ssrn.2001449","main_file_link":[{"url":"https://www.sciencedirect.com/science/article/pii/S0378426614003380"}],"date_updated":"2026-04-09T08:14:22Z","volume":51,"date_created":"2018-10-26T07:08:32Z","author":[{"full_name":"Schlueter, Tobias","last_name":"Schlueter","first_name":"Tobias"},{"first_name":"Sönke","last_name":"Sievers","full_name":"Sievers, Sönke","id":"46447"},{"first_name":"Thomas","last_name":"Hartmann-Wendels","full_name":"Hartmann-Wendels, Thomas"}]},{"keyword":["funding-maxup","tet_topic_hpc"],"language":[{"iso":"eng"}],"publication":"ACM SIGARCH Computer Architecture News","publisher":"ACM","date_created":"2018-03-26T13:42:34Z","title":"Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers","quality_controlled":"1","issue":"5","year":"2014","_id":"1779","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"61"},{"_id":"78"}],"type":"journal_article","status":"public","date_updated":"2023-09-26T13:35:58Z","author":[{"first_name":"Heiner","last_name":"Giefers","full_name":"Giefers, Heiner"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"orcid":"0000-0001-7059-9862","last_name":"Förstner","full_name":"Förstner, Jens","id":"158","first_name":"Jens"}],"volume":41,"doi":"10.1145/2641361.2641372","publication_identifier":{"issn":["0163-5964"]},"citation":{"ama":"Giefers H, Plessl C, Förstner J. Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. <i>ACM SIGARCH Computer Architecture News</i>. 2014;41(5):65-70. doi:<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>","ieee":"H. Giefers, C. Plessl, and J. Förstner, “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers,” <i>ACM SIGARCH Computer Architecture News</i>, vol. 41, no. 5, pp. 65–70, 2014, doi: <a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>.","chicago":"Giefers, Heiner, Christian Plessl, and Jens Förstner. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” <i>ACM SIGARCH Computer Architecture News</i> 41, no. 5 (2014): 65–70. <a href=\"https://doi.org/10.1145/2641361.2641372\">https://doi.org/10.1145/2641361.2641372</a>.","short":"H. Giefers, C. Plessl, J. Förstner, ACM SIGARCH Computer Architecture News 41 (2014) 65–70.","bibtex":"@article{Giefers_Plessl_Förstner_2014, title={Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers}, volume={41}, DOI={<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>}, number={5}, journal={ACM SIGARCH Computer Architecture News}, publisher={ACM}, author={Giefers, Heiner and Plessl, Christian and Förstner, Jens}, year={2014}, pages={65–70} }","mla":"Giefers, Heiner, et al. “Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers.” <i>ACM SIGARCH Computer Architecture News</i>, vol. 41, no. 5, ACM, 2014, pp. 65–70, doi:<a href=\"https://doi.org/10.1145/2641361.2641372\">10.1145/2641361.2641372</a>.","apa":"Giefers, H., Plessl, C., &#38; Förstner, J. (2014). Accelerating Finite Difference Time Domain Simulations with Reconfigurable Dataflow Computers. <i>ACM SIGARCH Computer Architecture News</i>, <i>41</i>(5), 65–70. <a href=\"https://doi.org/10.1145/2641361.2641372\">https://doi.org/10.1145/2641361.2641372</a>"},"page":"65-70","intvolume":"        41"},{"type":"journal_article","publication":" International Journal of Monetary Economics and Finance ","abstract":[{"text":"Employing a Hausman–Taylor instrument variable (HT–IV) estimator to data from 558 microfinance institutions (MFIs) in 80 developing countries for the period from 2002 to 2007, this paper provides empirical evidence for a positive impact of a country's external governance quality and outcome on local microbanks' economic success in terms of profitability and sustainability. Evidence as well suggests a negative relationship between external governance and the microbanks' social success measured by the depth of outreach. In this context, our analysis reveals that a country's political stability, governance effectiveness, regulatory quality and rule of law are significant key elements of external governance affecting the MFIs' functional performance. Moreover, results from sensitivity analyses indicate that the relationship between external governance quality and microfinance functional performance significantly depends on the microbanks' business concepts, their lending methodologies and sources of funding.","lang":"eng"}],"status":"public","_id":"4398","user_id":"21810","department":[{"_id":"186"},{"_id":"188"}],"keyword":["microfinance","external governance","economic success","social success","developing countries","profitability","sustainability","microbanks","outreach","political stability","governance effectiveness","regulatory quality","rule of law","governance quality","lending methodologies","funding sources"],"alternative_title":["The impact of external governance quality on the economic and social success of microfinance institutions "],"language":[{"iso":"eng"}],"publication_status":"published","publication_identifier":{"eissn":["1752-0487"]},"issue":"2/3","year":"2013","citation":{"ama":"Uhde A, Müller O. External governance outcome and microfinance success. <i> International Journal of Monetary Economics and Finance </i>. 2013;6(2/3):116-149. doi:<a href=\"https://doi.org/10.1504/IJMEF.2013.056394\">https://doi.org/10.1504/IJMEF.2013.056394</a>","ieee":"A. Uhde and O. Müller, “External governance outcome and microfinance success,” <i> International Journal of Monetary Economics and Finance </i>, vol. 6, no. 2/3, pp. 116–149, 2013, doi: <a href=\"https://doi.org/10.1504/IJMEF.2013.056394\">https://doi.org/10.1504/IJMEF.2013.056394</a>.","chicago":"Uhde, André, and Oliver Müller. “External Governance Outcome and Microfinance Success.” <i> International Journal of Monetary Economics and Finance </i> 6, no. 2/3 (2013): 116–49. <a href=\"https://doi.org/10.1504/IJMEF.2013.056394\">https://doi.org/10.1504/IJMEF.2013.056394</a>.","apa":"Uhde, A., &#38; Müller, O. (2013). External governance outcome and microfinance success. <i> International Journal of Monetary Economics and Finance </i>, <i>6</i>(2/3), 116–149. <a href=\"https://doi.org/10.1504/IJMEF.2013.056394\">https://doi.org/10.1504/IJMEF.2013.056394</a>","bibtex":"@article{Uhde_Müller_2013, title={External governance outcome and microfinance success}, volume={6}, DOI={<a href=\"https://doi.org/10.1504/IJMEF.2013.056394\">https://doi.org/10.1504/IJMEF.2013.056394</a>}, number={2/3}, journal={ International Journal of Monetary Economics and Finance }, author={Uhde, André and Müller, Oliver}, year={2013}, pages={116–149} }","short":"A. Uhde, O. Müller,  International Journal of Monetary Economics and Finance  6 (2013) 116–149.","mla":"Uhde, André, and Oliver Müller. “External Governance Outcome and Microfinance Success.” <i> International Journal of Monetary Economics and Finance </i>, vol. 6, no. 2/3, 2013, pp. 116–49, doi:<a href=\"https://doi.org/10.1504/IJMEF.2013.056394\">https://doi.org/10.1504/IJMEF.2013.056394</a>."},"jel":["G21","G28"],"intvolume":"         6","page":"116-149","date_updated":"2023-01-10T09:38:58Z","date_created":"2018-09-14T11:53:25Z","author":[{"last_name":"Uhde","orcid":"https://orcid.org/0000-0002-8058-8857","id":"36049","full_name":"Uhde, André","first_name":"André"},{"last_name":"Müller","full_name":"Müller, Oliver","first_name":"Oliver"}],"volume":6,"title":"External governance outcome and microfinance success","doi":"https://doi.org/10.1504/IJMEF.2013.056394"},{"type":"conference","status":"public","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"15"},{"_id":"78"}],"_id":"2106","file_date_updated":"2019-02-13T09:04:46Z","has_accepted_license":"1","citation":{"short":"B. Meyer, J. Schumacher, C. Plessl, J. Förstner, in: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL), IEEE, 2012, pp. 189–196.","bibtex":"@inproceedings{Meyer_Schumacher_Plessl_Förstner_2012, title={Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?}, DOI={<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>}, booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Meyer, Björn and Schumacher, Jörn and Plessl, Christian and Förstner, Jens}, year={2012}, pages={189–196} }","mla":"Meyer, Björn, et al. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, IEEE, 2012, pp. 189–96, doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","apa":"Meyer, B., Schumacher, J., Plessl, C., &#38; Förstner, J. (2012). Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–196. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>","ama":"Meyer B, Schumacher J, Plessl C, Förstner J. Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort? In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>. IEEE; 2012:189-196. doi:<a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>","ieee":"B. Meyer, J. Schumacher, C. Plessl, and J. Förstner, “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 2012, pp. 189–196, doi: <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">10.1109/FPL.2012.6339370</a>.","chicago":"Meyer, Björn, Jörn Schumacher, Christian Plessl, and Jens Förstner. “Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?” In <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, 189–96. IEEE, 2012. <a href=\"https://doi.org/10.1109/FPL.2012.6339370\">https://doi.org/10.1109/FPL.2012.6339370</a>."},"page":"189-196","author":[{"first_name":"Björn","full_name":"Meyer, Björn","last_name":"Meyer"},{"last_name":"Schumacher","full_name":"Schumacher, Jörn","first_name":"Jörn"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Jens","id":"158","full_name":"Förstner, Jens","last_name":"Förstner","orcid":"0000-0001-7059-9862"}],"date_updated":"2023-09-26T13:39:13Z","conference":{"name":"22nd International Conference on Field Programmable Logic and Applicaitons (FPL)"},"doi":"10.1109/FPL.2012.6339370","publication":"Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)","file":[{"relation":"main_file","success":1,"content_type":"application/pdf","access_level":"closed","file_id":"7638","file_name":"2012-11 Meyer,Schumacher,Plessl,Förstner_Convey vector personalities-FPGA acceleratin with an openmp-like programming effort.pdf","file_size":2148787,"date_created":"2019-02-13T09:04:46Z","creator":"fossie","date_updated":"2019-02-13T09:04:46Z"}],"abstract":[{"text":"Although the benefits of FPGAs for accelerating scientific codes are widely acknowledged, the use of FPGA accelerators in scientific computing is not widespread because reaping these benefits requires knowledge of hardware design methods and tools that is typically not available with domain scientists. A promising but hardly investigated approach is to develop tool flows that keep the common languages for scientific code (C,C++, and Fortran) and allow the developer to augment the source code with OpenMPlike directives for instructing the compiler which parts of the application shall be offloaded the FPGA accelerator.\r\nIn this work we study whether the promise of effective FPGA acceleration with an OpenMP-like programming effort\r\ncan actually be held. Our target system is the Convey HC-1 reconfigurable computer for which an OpenMP-like\r\nprogramming environment exists. As case study we use an application from computational nanophotonics. Our results\r\nshow that a developer without previous FPGA experience could create an FPGA-accelerated application that is competitive to an optimized OpenMP-parallelized CPU version running on a two socket quad-core server. Finally, we discuss our experiences with this tool flow and the Convey HC-1 from a productivity and economic point of view.","lang":"eng"}],"language":[{"iso":"eng"}],"ddc":["000"],"keyword":["funding-upb-forschungspreis","funding-maxup","tet_topic_hpc"],"quality_controlled":"1","year":"2012","date_created":"2018-03-29T15:04:25Z","publisher":"IEEE","title":"Convey Vector Personalities – FPGA Acceleration with an OpenMP-like Effort?"},{"language":[{"iso":"eng"}],"keyword":["funding-altera"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"2108","status":"public","publication":"Microprocessors and Microsystems","type":"journal_article","doi":"10.1016/j.micpro.2011.04.002","title":"IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators","volume":36,"author":[{"full_name":"Schumacher, Tobias","last_name":"Schumacher","first_name":"Tobias"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"},{"last_name":"Platzner","full_name":"Platzner, Marco","id":"398","first_name":"Marco"}],"date_created":"2018-03-29T15:12:38Z","date_updated":"2023-09-26T13:39:30Z","page":"110-126","intvolume":"        36","citation":{"apa":"Schumacher, T., Plessl, C., &#38; Platzner, M. (2012). IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>, <i>36</i>(2), 110–126. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>","mla":"Schumacher, Tobias, et al. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, 2012, pp. 110–26, doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>.","bibtex":"@article{Schumacher_Plessl_Platzner_2012, title={IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators}, volume={36}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>}, number={2}, journal={Microprocessors and Microsystems}, author={Schumacher, Tobias and Plessl, Christian and Platzner, Marco}, year={2012}, pages={110–126} }","short":"T. Schumacher, C. Plessl, M. Platzner, Microprocessors and Microsystems 36 (2012) 110–126.","ama":"Schumacher T, Plessl C, Platzner M. IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators. <i>Microprocessors and Microsystems</i>. 2012;36(2):110-126. doi:<a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>","chicago":"Schumacher, Tobias, Christian Plessl, and Marco Platzner. “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators.” <i>Microprocessors and Microsystems</i> 36, no. 2 (2012): 110–26. <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">https://doi.org/10.1016/j.micpro.2011.04.002</a>.","ieee":"T. Schumacher, C. Plessl, and M. Platzner, “IMORC: An Infrastructure and Architecture Template for Implementing High-Performance Reconfigurable FPGA Accelerators,” <i>Microprocessors and Microsystems</i>, vol. 36, no. 2, pp. 110–126, 2012, doi: <a href=\"https://doi.org/10.1016/j.micpro.2011.04.002\">10.1016/j.micpro.2011.04.002</a>."},"year":"2012","issue":"2","quality_controlled":"1","publication_identifier":{"issn":["0141-9331"]}},{"title":"Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux","date_updated":"2023-09-26T13:40:17Z","date_created":"2018-04-03T09:18:33Z","author":[{"full_name":"Beisel, Tobias","last_name":"Beisel","first_name":"Tobias"},{"first_name":"Tobias","full_name":"Wiersema, Tobias","id":"3118","last_name":"Wiersema"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"first_name":"André","full_name":"Brinkmann, André","last_name":"Brinkmann"}],"year":"2012","citation":{"ama":"Beisel T, Wiersema T, Plessl C, Brinkmann A. Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. In: <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>. ; 2012.","ieee":"T. Beisel, T. Wiersema, C. Plessl, and A. Brinkmann, “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux,” 2012.","chicago":"Beisel, Tobias, Tobias Wiersema, Christian Plessl, and André Brinkmann. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” In <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012.","short":"T. Beisel, T. Wiersema, C. Plessl, A. Brinkmann, in: Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS), 2012.","mla":"Beisel, Tobias, et al. “Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux.” <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>, 2012.","bibtex":"@inproceedings{Beisel_Wiersema_Plessl_Brinkmann_2012, title={Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux}, booktitle={Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)}, author={Beisel, Tobias and Wiersema, Tobias and Plessl, Christian and Brinkmann, André}, year={2012} }","apa":"Beisel, T., Wiersema, T., Plessl, C., &#38; Brinkmann, A. (2012). Programming and Scheduling Model for Supporting Heterogeneous Accelerators in Linux. <i>Proc. Workshop on Computer Architecture and Operating System Co-Design (CAOS)</i>."},"quality_controlled":"1","keyword":["funding-enhance"],"language":[{"iso":"eng"}],"project":[{"_id":"30","name":"Enabling Heterogeneous Hardware Acceleration using Novel Programming and Scheduling Models","grant_number":"01|H11004A"}],"_id":"2180","user_id":"15278","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"status":"public","type":"conference","publication":"Proc. Workshop on Computer Architecture and Operating System Co-design (CAOS)"},{"_id":"2191","user_id":"24135","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"keyword":["funding-intel"],"type":"conference","publication":"Intel European Research and Innovation Conference","status":"public","date_updated":"2022-01-06T06:55:19Z","date_created":"2018-04-03T14:34:57Z","author":[{"first_name":"Tobias","full_name":"Kenter, Tobias","id":"3145","last_name":"Kenter"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"},{"first_name":"Michael","last_name":"Kauschke","full_name":"Kauschke, Michael"}],"title":"Estimation and Partitioning for CPU-Accelerator Architectures","year":"2011","citation":{"apa":"Kenter, T., Plessl, C., Platzner, M., &#38; Kauschke, M. (2011). Estimation and Partitioning for CPU-Accelerator Architectures. In <i>Intel European Research and Innovation Conference</i>.","short":"T. Kenter, C. Plessl, M. Platzner, M. Kauschke, in: Intel European Research and Innovation Conference, 2011.","mla":"Kenter, Tobias, et al. “Estimation and Partitioning for CPU-Accelerator Architectures.” <i>Intel European Research and Innovation Conference</i>, 2011.","bibtex":"@inproceedings{Kenter_Plessl_Platzner_Kauschke_2011, title={Estimation and Partitioning for CPU-Accelerator Architectures}, booktitle={Intel European Research and Innovation Conference}, author={Kenter, Tobias and Plessl, Christian and Platzner, Marco and Kauschke, Michael}, year={2011} }","ama":"Kenter T, Plessl C, Platzner M, Kauschke M. Estimation and Partitioning for CPU-Accelerator Architectures. In: <i>Intel European Research and Innovation Conference</i>. ; 2011.","ieee":"T. Kenter, C. Plessl, M. Platzner, and M. Kauschke, “Estimation and Partitioning for CPU-Accelerator Architectures,” in <i>Intel European Research and Innovation Conference</i>, 2011.","chicago":"Kenter, Tobias, Christian Plessl, Marco Platzner, and Michael Kauschke. “Estimation and Partitioning for CPU-Accelerator Architectures.” In <i>Intel European Research and Innovation Conference</i>, 2011."}},{"quality_controlled":"1","publication_identifier":{"isbn":["978-1-4503-0554-9"]},"page":"177-180","citation":{"bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>","chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–80. New York, NY, USA: ACM, 2011. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>.","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi: <a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>"},"year":"2011","place":"New York, NY, USA","author":[{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian","first_name":"Christian"},{"full_name":"Kauschke, Michael","last_name":"Kauschke","first_name":"Michael"}],"date_created":"2018-04-03T15:08:13Z","publisher":"ACM","date_updated":"2023-09-26T13:45:04Z","doi":"10.1145/1950413.1950448","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","type":"conference","status":"public","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"2200","language":[{"iso":"eng"}],"keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"]},{"quality_controlled":"1","year":"2011","citation":{"bibtex":"@article{Schumacher_Süß_Plessl_Platzner_2011, title={FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study}, DOI={<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>}, journal={Int. Journal of Recon- figurable Computing (IJRC)}, publisher={Hindawi Publishing Corp.}, author={Schumacher, Tobias and Süß, Tim and Plessl, Christian and Platzner, Marco}, year={2011} }","short":"T. Schumacher, T. Süß, C. Plessl, M. Platzner, Int. Journal of Recon- Figurable Computing (IJRC) (2011).","mla":"Schumacher, Tobias, et al. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>, Hindawi Publishing Corp., 2011, doi:<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>.","apa":"Schumacher, T., Süß, T., Plessl, C., &#38; Platzner, M. (2011). FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>. <a href=\"https://doi.org/10.1155/2011/760954\">https://doi.org/10.1155/2011/760954</a>","chicago":"Schumacher, Tobias, Tim Süß, Christian Plessl, and Marco Platzner. “FPGA Acceleration of Communication-Bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study.” <i>Int. Journal of Recon- Figurable Computing (IJRC)</i>, 2011. <a href=\"https://doi.org/10.1155/2011/760954\">https://doi.org/10.1155/2011/760954</a>.","ieee":"T. Schumacher, T. Süß, C. Plessl, and M. Platzner, “FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study,” <i>Int. Journal of Recon- figurable Computing (IJRC)</i>, 2011, doi: <a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>.","ama":"Schumacher T, Süß T, Plessl C, Platzner M. FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study. <i>Int Journal of Recon- figurable Computing (IJRC)</i>. Published online 2011. doi:<a href=\"https://doi.org/10.1155/2011/760954\">10.1155/2011/760954</a>"},"date_updated":"2023-09-26T13:45:46Z","publisher":"Hindawi Publishing Corp.","date_created":"2018-04-03T15:09:49Z","author":[{"first_name":"Tobias","full_name":"Schumacher, Tobias","last_name":"Schumacher"},{"first_name":"Tim","full_name":"Süß, Tim","last_name":"Süß"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"title":"FPGA Acceleration of Communication-bound Streaming Applications: Architecture Modeling and a 3D Image Compositing Case Study","doi":"10.1155/2011/760954","publication":"Int. Journal of Recon- figurable Computing (IJRC)","type":"journal_article","status":"public","_id":"2201","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","keyword":["funding-altera"],"language":[{"iso":"eng"}]},{"user_id":"24135","department":[{"_id":"518"},{"_id":"78"}],"_id":"2428","keyword":["minimum covering","accelerator","funding-sundance"],"type":"conference","publication":"Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)","status":"public","abstract":[{"lang":"eng","text":" In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups. "}],"author":[{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Marco","full_name":"Platzner, Marco","id":"398","last_name":"Platzner"}],"date_created":"2018-04-17T15:39:17Z","publisher":"CSREA Press","date_updated":"2022-01-06T06:56:17Z","title":"Instance-Specific Accelerators for Minimum Covering","citation":{"apa":"Plessl, C., &#38; Platzner, M. (2001). Instance-Specific Accelerators for Minimum Covering. In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i> (pp. 85–91). CSREA Press.","bibtex":"@inproceedings{Plessl_Platzner_2001, title={Instance-Specific Accelerators for Minimum Covering}, booktitle={Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)}, publisher={CSREA Press}, author={Plessl, Christian and Platzner, Marco}, year={2001}, pages={85–91} }","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, CSREA Press, 2001, pp. 85–91.","short":"C. Plessl, M. Platzner, in: Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA), CSREA Press, 2001, pp. 85–91.","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. In: <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>. CSREA Press; 2001:85-91.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” In <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 85–91. CSREA Press, 2001.","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” in <i>Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA)</i>, 2001, pp. 85–91."},"page":"85-91","year":"2001"}]