--- _id: '10673' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Abdullah Fathi full_name: Ahmed, Abdullah Fathi last_name: Ahmed - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178' apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178 bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }' chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178. ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7. mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178. short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.' date_created: 2019-07-10T11:18:00Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1109/AHS.2015.7231178 keyword: - cache storage - field programmable gate arrays - multiprocessing systems - parallel architectures - reconfigurable architectures - FPGA - dynamic reconfiguration - evolvable cache mapping - many-core architecture - memory-to-cache address mapping function - microarchitectural optimization - multicore architecture - nature-inspired optimization - parallelization degrees - processor - reconfigurable cache mapping - reconfigurable computing - Field programmable gate arrays - Software - Tuning language: - iso: eng page: 1-7 project: - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) status: public title: Microarchitectural optimization by means of reconfigurable and evolvable cache mappings type: conference user_id: '3118' year: '2015' ...