@article{11867,
  abstract     = {{New waves of consumer-centric applications, such as voice search and voice interaction with mobile devices and home entertainment systems, increasingly require automatic speech recognition (ASR) to be robust to the full range of real-world noise and other acoustic distorting conditions. Despite its practical importance, however, the inherent links between and distinctions among the myriad of methods for noise-robust ASR have yet to be carefully studied in order to advance the field further. To this end, it is critical to establish a solid, consistent, and common mathematical foundation for noise-robust ASR, which is lacking at present. This article is intended to fill this gap and to provide a thorough overview of modern noise-robust techniques for ASR developed over the past 30 years. We emphasize methods that are proven to be successful and that are likely to sustain or expand their future applicability. We distill key insights from our comprehensive overview in this field and take a fresh look at a few old problems, which nevertheless are still highly relevant today. Specifically, we have analyzed and categorized a wide range of noise-robust techniques using five different criteria: 1) feature-domain vs. model-domain processing, 2) the use of prior knowledge about the acoustic environment distortion, 3) the use of explicit environment-distortion models, 4) deterministic vs. uncertainty processing, and 5) the use of acoustic models trained jointly with the same feature enhancement or model adaptation process used in the testing stage. With this taxonomy-oriented review, we equip the reader with the insight to choose among techniques and with the awareness of the performance-complexity tradeoffs. The pros and cons of using different noise-robust ASR techniques in practical application scenarios are provided as a guide to interested practitioners. The current challenges and future research directions in this field is also carefully analyzed.}},
  author       = {{Li, Jinyu and Deng, Li and Gong, Yifan and Haeb-Umbach, Reinhold}},
  journal      = {{IEEE Transactions on Audio, Speech and Language Processing}},
  keywords     = {{Speech recognition, compensation, distortion modeling, joint model training, noise, robustness, uncertainty processing}},
  number       = {{4}},
  pages        = {{745--777}},
  title        = {{{An Overview of Noise-Robust Automatic Speech Recognition}}},
  doi          = {{10.1109/TASLP.2014.2304637}},
  volume       = {{22}},
  year         = {{2014}},
}

@inproceedings{36918,
  abstract     = {{This paper presents an advanced eight levels spanning SystemC based virtual platform methodology and framework - referred to as HeroeS 3 - providing smooth application to platform mapping and continuous co-refinement of a virtual prototype with its physical environment model. For heterogeneity support, various SystemC extensions are combined covering continuous/discrete models of computation and different communication abstractions, such as analog mixed-signal models, abstract RTOS/HAL/middleware models, TLM bus models, and QEMU wrappers. We enable dependability assessment by Fault Effect Modeling (FEM) at the virtual prototype in order to avoid risking physical injury or damage. Also, simulation results are deterministic and can be evaluated interactively or offline. We apply FEM to both the physical environment model and the different abstractions of the virtual prototype. Currently, we focus on sensor failures and application control flow errors.}},
  author       = {{Becker, Markus and Kuznik, Christoph and Müller, Wolfgang}},
  keywords     = {{Computational modeling, Finite element analysis, Prototypes, Abstracts, Software, Fault tolerance, Fault tolerant systems}},
  location     = {{Berlin}},
  publisher    = {{IEEE}},
  title        = {{{Fault Effect Modeling in a Heterogeneous SystemC Based Virtual Platform Framework for Cyber Physical Systems}}},
  doi          = {{10.1109/ICCPS.2014.6843726}},
  year         = {{2014}},
}

@inproceedings{4480,
  abstract     = {{The proposed paper aims to investigate the longitudinal development of students' motivation over the first year of their studies at a business school by using latent growth curve modeling. The study tackles the following core research questions: How do first-year university students' intrinsic and extrinsic vary over time? Which (motivational) factors are related to students' motivational development? Although motivational dispositions have been analyzed extensively in previous studies, their longitudinal development has hitherto not been examined in the higher education context.

This longitudinal study is conducted at the University of St. Gallen in Switzerland. The current sample includes 280 first-year students who have been surveyed three times and who are representative of the first-year student population.

Descriptive results show that prior to their studies, students were motivated most by intrinsic factors, however, extrinsic motivation was also quite high. Employing latent growth curve modeling, it could be shown that both intrinsic and extrinsic motivation decline significantly over the course of the first year (8 months).

The study contributes to motivation theory by providing further insights into the development of academic motivation over time. Latent growth curve modeling as a method can be well used for longitudinal data analysis, thus, excluding measurement error from longitudinal data. Furthermore, the study supports educational developers by determining factors influencing students' motivational development.}},
  author       = {{Brahm, Taiga and Jenert, Tobias}},
  keywords     = {{motivation, intrinsic motivation, extrinsic motivation, latent growth curve modeling, longitudinal data analysis, ASEQ, higher education, studying}},
  location     = {{München}},
  publisher    = {{EARLI European Association for Research on Learning and Instruction}},
  title        = {{{A latent growth curve analysis of Business students' intrinsic and extrinsic motivation}}},
  year         = {{2013}},
}

@article{4699,
  author       = {{Becker, Jörg and Beverungen, Daniel and Knackstedt, Ralf and Matzner, Martin and Müller, Oliver and Pöppelbuss, Jens}},
  issn         = {{09050167}},
  journal      = {{Scandinavian Journal of Information Systems}},
  keywords     = {{Business process management, Conceptual modeling, Interaction routines, Modular design, Service networks, Social construction}},
  number       = {{1}},
  pages        = {{17----47}},
  title        = {{{Designing interaction routines in service networks: A modularity and social construction-based approach}}},
  year         = {{2013}},
}

@inproceedings{9796,
  abstract     = {{A basic autonomous system powered by a piezoelectric harvester contains three components apart from the harvester: a fullwave rectifier, a reservoir capacitor and an electronic device performing the primary task of the system. In this contribution, a model describing the operation of such a system is derived. It is found that in steady-state operation, the piezoelectric harvester experiences two alternating load conditions due to the rectification process. These alternating load conditions can have a significant effect on the operation of the harvester and must be considered in the design of autonomous systems. The results also show that such an autonomous system works efficiently if it is connected to a high impedance load and excited by a frequency matching the anti-resonance frequency of the piezoelectric harvester.}},
  author       = {{Al-Ashtari, Waleed and Hunstig, Matthias and Hemsel, Tobias and Sextro, Walter}},
  booktitle    = {{Proceedings of 10th International Workshop on Piezoelectric Materials and Applications and 8th Energy Harvesting Workshop, Hannover, Germany, 14.-17.7.2013}},
  keywords     = {{Energy harvesting, harvester modeling, load dependence, generated voltage}},
  number       = {{05/2013}},
  pages        = {{159--161}},
  title        = {{{Characteristics of Piezoelectric Energy Harvesters in Autonomous Systems}}},
  year         = {{2013}},
}

@inproceedings{9797,
  abstract     = {{A model approach for wedge/wedge bonding copper wire is presented. The connection between wire and substrate is based on a variety of physical effects, but the dominant one is the friction based welding while applying ultrasound. Consequently, a friction model was used to investigate the welding process. This model is built up universal and can be used to describe the formation of micro welds in the time variant contact area between wire and substrate. Aim of the model is to identify the interactions between touchdown, bond normal force, ultrasonic power and bonding time. To do so, the contact area is discretized into partial areas where a Point Contact Model is applied. Based on this approach it is possible to simulate micro and macro slip inside the contact area between wire and substrate. The work done by friction force is a main criterion to define occurring micro joints which influence the subsequent welding.}},
  author       = {{Althoff, Simon and Neuhaus, Jan and Hemsel, Tobias and Sextro, Walter}},
  booktitle    = {{IMAPS 2013, 46th International Symposium on Microelectronics}},
  keywords     = {{Wire bonding, friction modeling, wire bond quality, contact element modeling}},
  title        = {{{A friction based approach for modeling wire bonding}}},
  doi          = {{10.4071/isom-2013-TA67}},
  year         = {{2013}},
}

@inproceedings{36919,
  abstract     = {{Faced with increasing demands on energy efficiency, current electronic systems operate according to complex power management schemes including more and more fine-grained voltage frequency scaling and power shutdown scenarios. Consequently, validation of the power design intent should begin as early as possible at electronic system-level (ESL) together with first executable system specifications for integrity tests. However, today's system-level design methodologies usually focus on the abstraction of digital logic and time, so that typical low-power aspects cannot be considered so far. In this paper, we present a high-level modeling approach on top of the SystemC/TLM standard to simulate power distribution and voltage based implications in a "loosely-timed" functional execution context. The approach reuses legacy TLM models and prevents the need for detailed lock-step process synchronization in contrast to existing methods. A case study derived from an open source low-power design demonstrates the efficiency of our approach in terms of simulation performance and testability.}},
  author       = {{Mischkalla, Fabian and Müller, Wolfgang}},
  keywords     = {{Time-varying systems, Time-domain analysis, Synchronization, Context modeling, Clocks, Semantics, Standards}},
  publisher    = {{IEEE}},
  title        = {{{Efficient Power-Intent Validation Using "Loosely-Timed" Simulation Models: A Non-Invasive Approach}}},
  doi          = {{10.1109/PATMOS.2013.6662171}},
  year         = {{2013}},
}

@inproceedings{9784,
  abstract     = {{Piezoelectric inertia motors use the inertia of a body to drive it by means of a friction contact in a series of small steps. These motors can operate in ``stick-slip'' or ``slip-slip'' mode, with the fundamental frequency of the driving signal ranging from several Hertz to more than 100 kHz. To predict the motor characteristics, a Coulomb friction model is sufficient in many cases, but numerical simulation requires microscopic time steps. This contribution proposes a much faster simulation technique using one evaluation per period of the excitation signal. The proposed technique produces results very close to those of timestep simulation for ultrasonics inertia motors and allows direct determination of the steady-state velocity of an inertia motor from the motion profile of the driving part. Thus it is a useful simulation technique which can be applied in both analysis and design of inertia motors, especially for parameter studies and optimisation.}},
  author       = {{Hunstig, Matthias and Hemsel, Tobias and Sextro, Walter}},
  booktitle    = {{Ultrasonics Symposium (IUS), 2012 IEEE International}},
  issn         = {{1948-5719}},
  keywords     = {{friction, ultrasonic motors, Coulomb friction model, efficient simulation technique, friction contact, high-frequency piezoelectric inertia motor, motor characteristics prediction, numerical simulation, slip-slip mode, stick-slip mode, time-step simulation, ultrasonic inertia motor, Acceleration, Acoustics, Actuators, Computational modeling, Friction, Numerical models, Steady-state}},
  pages        = {{277--280}},
  title        = {{{An efficient simulation technique for high-frequency piezoelectric inertia motors}}},
  doi          = {{10.1109/ULTSYM.2012.0068}},
  year         = {{2012}},
}

@article{45933,
  author       = {{Karátson, J. and Kovács, Balázs}},
  issn         = {{0898-1221}},
  journal      = {{Computers & Mathematics with Applications}},
  keywords     = {{Computational Mathematics, Computational Theory and Mathematics, Modeling and Simulation}},
  number       = {{3}},
  pages        = {{449--459}},
  publisher    = {{Elsevier BV}},
  title        = {{{Variable preconditioning in complex Hilbert space and its application to the nonlinear Schrödinger equation}}},
  doi          = {{10.1016/j.camwa.2012.04.021}},
  volume       = {{65}},
  year         = {{2012}},
}

@inproceedings{37002,
  abstract     = {{HDL-mutation based fault injection and analysis is considered as an important coverage metric for measuring the quality of design simulation processes [20, 3, 1, 2]. In this work, we try to solve the problem of automatic simulation data generation targeting HDL mutation faults. We follow a search based approach and eliminate the need for symbolic execution and mathematical constraint solving from existing work. An objective cost function is defined on the test input space and serves the guidance of search for fault-detecting test data. This is done by first mapping the simulation traces under a test onto a control and data flow graph structure which is extracted from the design. Then the progress of fault detection can be measured quantitatively on this graph to be the cost value. By minimizing this cost we approach the target test data. The effectiveness of the cost function is investigated under an example neighborhood search scheme. Case study with a floating point arithmetic IP design has shown that the cost function is able to guide effectively the search procedure towards a fault-detecting test. The cost calculation time as the search overhead was also observed to be minor compared to the actual design simulation time.}},
  author       = {{Xie, Tao and Müller, Wolfgang and Letombe, Florian}},
  booktitle    = {{Proceedings of Euromicro DSD 2011}},
  isbn         = {{978-1-4577-1048-3}},
  keywords     = {{Hardware design languages, Cost function, Computational modeling, Fault detection, Data models, Analytical models, Testing}},
  publisher    = {{IEEE}},
  title        = {{{HDL-Mutation Based Simulation Data Generation by Propagation Guided Search}}},
  doi          = {{10.1109/DSD.2011.83}},
  year         = {{2011}},
}

@inproceedings{37007,
  abstract     = {{UML is widely applied for the specification and modeling of software and some studies have demonstrated that it is applicable for HW/SW codesign. However, in this area there is still a big gap from UML modeling to SystemC-based verification and synthesis environments. This paper presents an efficient approach to bridge this gap in the context of Systems-on-a-Chip (SoC) design. We propose a framework for the seamless integration of a customized SysML entry with code generation for HW/SW cosimulation and high-level FPGA synthesis. For this, we extended the SysML UML profile by SystemC and synthesis capabilities. Two case studies demonstrate the applicability of our approach.}},
  author       = {{Mischkalla, Fabian and He, Da and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Unified modeling language, Field programmable gate arrays, Bridges, Helium, Real time systems, Operating systems, Documentation, Application software, XML, Space exploration}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{Closing the Gap between UML-based Modeling and Simulation of Combined HW/SW Systems}}},
  doi          = {{10.1109/DATE.2010.5456990}},
  year         = {{2010}},
}

@inproceedings{37037,
  abstract     = {{Today we can identify a big gap between requirement specification and the generation of test environments. This article extends the Classification Tree Method for Embedded Systems (CTM/ES) to fill this gap by new concepts for the precise specification of stimuli for operational ranges of continuous control systems. It introduces novel means for continuous acceptance criteria definition and for functional coverage definition.}},
  author       = {{Krupp, Alexander and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{System testing, Automatic testing, Object oriented modeling, Classification tree analysis, Automotive engineering, Mathematical model, Embedded system, Control systems, Electronic equipment testing, Software testing}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{A Systematic Approach to Combined HW/SW System Test}}},
  doi          = {{10.1109/DATE.2010.5457186}},
  year         = {{2010}},
}

@inproceedings{37040,
  abstract     = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}},
  author       = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}},
  doi          = {{10.1109/DATE.2010.5456965}},
  year         = {{2010}},
}

@inproceedings{37057,
  abstract     = {{Many heterogeneous embedded systems, for example industrial automation and automotive applications, require hard-real time constraints to be exhaustively verified - which is a challenging task for the verification engineer. To cope with complexity, verification techniques working on different abstraction levels are best practice. SystemC is a versatile C++ based design and verification language, offering various mechanisms and constructs required for embedded systems modeling. Using the add-on SystemC Verification Library (SCV) elemental constrained-random stimuli techniques may be used for verification. However, SCV has several drawbacks such as lack of functional coverage. In this paper we present a functional coverage library that implements parts of the IEEE 1800-2005 SystemVerilog standard and allows capturing functional coverage throughout the design and verification process with SystemC. Moreover, we will demonstrate the usability of the approach with a case study working on a CAN bus model written in SystemC.}},
  author       = {{Defo, Gilles B. and Müller, Wolfgang and Kuznik, Christoph}},
  booktitle    = {{Proceedings of SIES 2010}},
  keywords     = {{Libraries, Generators, Transfer functions, Monitoring, Computational modeling, Driver circuits, Adaptation model}},
  location     = {{ Trento, Italy}},
  publisher    = {{IEEE}},
  title        = {{{Verification of a CAN Bus Model in SystemC with Functional Coverage}}},
  doi          = {{10.1109/SIES.2010.5551379}},
  year         = {{2010}},
}

@inproceedings{37039,
  abstract     = {{Refinement of untimed TLM models into a timed HW/SW platform is a step by step design process which is a trade-off between timing accuracy of the used models and correct estimation of the final timing performance. The use of an RTOS on the target platform is mandatory in the case real-time properties must be guaranteed. Thus, the question is when the RTOS must be introduced in this step by step refinement process. This paper proposes a four-level RTOS-aware refinement methodology that, starting from an untimed TLM SystemC description of the whole system, progressively introduce HW/SW partitioning, timing, device driver and RTOS functionalities, till to obtain an accurate model of the final platform, where SW tasks run upon an RTOS hosted by QEMU and HW components are modeled by cycle accurate TLM descriptions. Each refinement level allows the designer to estimate more and more accurate timing properties, thus anticipating design decisions without being constrained to leave timing analysis to the final step of the refinement. The effectiveness of the methodology has been evaluated in the design of two complex platforms.}},
  author       = {{Becker, Markus and Di Guglielmo, Giuseppe and Fummi, Franco and Müller, Wolfgang and Pravadelli, Graziano and Xie, Tao}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Timing, Hardware, Operating systems, Process design, Accuracy, Standards development, Context modeling, Real time systems, Communication channels, Microprogramming}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{RTOS-Aware Refinement for TLM2.0-based HW/SW Design}}},
  doi          = {{10.1109/DATE.2010.5456965}},
  year         = {{2010}},
}

@inproceedings{24065,
  author       = {{Pottebaum, Jens and Japs, Anna Maria and Prödel, Stephan and Koch, Rainer}},
  booktitle    = {{ISCRAM 2010 -- 7th International Conference on Information Systems for Crisis Response and Management}},
  editor       = {{French, Simon and Tomaszewski, Brian and Zobel, Chris}},
  keywords     = {{Command and control process, Command and control systems, Design and modeling, Domain ontologies, Emergency response, Fire extinguishers, Fire protection, Heterogeneous domains, Information analysis, Information sharing, Information systems, Interoperability, Ontology language, Semantic technologies, Semantic Web, Semantics}},
  title        = {{{Design and modeling of a domain ontology for fire protection}}},
  year         = {{2010}},
}

@inproceedings{37067,
  abstract     = {{IP-XACT is a well accepted standard for the exchange of IP components at Electronic System and Register Transfer Level. Still, the creation and manipulation of these descriptions at the XML level can be time-consuming and error-prone. In this paper, we show that the UML can be consistently applied as an efficient and comprehensible frontend for IP-XACT-based IP description and integration. For this, we present an IP-XACT UML profile that enables UML-based descriptions covering the same information as a corresponding IP-XACT description. This enables the automated generation of IP-XACT component and design descriptions from respective UML models. In particular, it also allows the integration of existing IPs with UML. To illustrate our approach, we present an application example based on the IBM PowerPC Evaluation Kit.}},
  author       = {{Schattkowsky, Tim and Xie, Tao and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE'09}},
  isbn         = {{978-1-4244-3781-8}},
  keywords     = {{Unified modeling language, XML, Power system modeling, Application software, Master-slave, Power system management, Acceleration, Scattering, Software engineering, Software standards}},
  publisher    = {{IEEE}},
  title        = {{{A UML Frontend for IP-XACT-based IP Management}}},
  doi          = {{10.1109/DATE.2009.5090664}},
  year         = {{2009}},
}

@inproceedings{37066,
  abstract     = {{Today, mobile and embedded real-time systems have to cope with the migration and allocation of multiple software tasks running on top of a real-time operating system (RTOS) residing on one or multiple system processors. Abstract RTOS simulations and timing analysis applies for fast and early estimation to configure it towards the individual needs of the application and environment. In this context, a high accuracy of the simulation compared to an instruction set simulation (ISS) is of key importance. In this paper, we investigate the accuracy of abstract RTOS simulation and compare it to ISS and the behavior of the physical system. We show that we can reach an increased accuracy of the simulation when we inject noise into the time model. Our results indicate that it is sufficient to inject uniformly distributed random time values to the RTOS real-time clock.}},
  author       = {{Zabel, Henning and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE'09}},
  isbn         = {{978-1-4244-3781-8}},
  keywords     = {{Timing, Analytical models, Clocks, Performance analysis, Scheduling, Operating systems, Delay, Real time systems, Application software, Context modeling}},
  title        = {{{Increased Accuracy through Noise Injection in Abstract RTOS Simulation}}},
  doi          = {{10.1109/DATE.2009.5090925}},
  year         = {{2009}},
}

@article{9571,
  abstract     = {{Several positioning tasks demand translatory drive instead of rotary motion. To achieve drives that are capable, e.g., to drive the sunroof of a car or to lift a car's window, multiple miniaturized motors can be combined. But in this case many other questions arise: The electromechanical behavior of the individual motors differs slightly, the motor characteristics are strongly dependent on the driving parameters and the driven load, many applications need some extra power for special cases like overcoming higher forces periodically. Thus, the bundle of motors has to act well-organized and at last controlled to get an optimized drive that is not oversized and costly.}},
  author       = {{Mracek, Maik and Hemsel, Tobias and Sattel, Thomas and Vasiljev, Piotr and Wallaschek, Jörg}},
  issn         = {{1385-3449}},
  journal      = {{Journal of Electroceramics}},
  keywords     = {{Ultrasonic linear motor, High power, Control, Modeling, Characteristics}},
  number       = {{3-4}},
  pages        = {{153--158}},
  publisher    = {{Springer US}},
  title        = {{{Driving concepts for bundled ultrasonic linear motors}}},
  doi          = {{10.1007/s10832-007-9123-5}},
  volume       = {{20}},
  year         = {{2008}},
}

@inproceedings{39029,
  abstract     = {{UML 2.0 provides a rich set of diagrams for systems documentation and specification. Much effort has been undertaken to employ different aspects of UML for multiple domains, mainly in the area of software systems. Considering the area of electronic design automation, however, we currently see only very few approaches which investigate UML for hardware design and hardware/software co-design. We present an approach for executable UML closing the gap from system specification to its model-based execution on reconfigurable hardware. For this purpose, we present our abstract execution platform (AEP), which is based on a virtual machine running an executable UML subset for embedded software and reconfigurable hardware. This subset combines UML 2.0 classes, state-machines and sequence diagrams for a complete system specification. We describe how these binary encoded UML specifications can be directly executed and give the implementation of such a virtual machine on a Virtex II FPGA. Finally, we present evaluation results comparing the AEP implementation with C code on a C167 microcontroller.}},
  author       = {{Schattkowsky, Tim and Müller, Wolfgang and Rettberg, Achim}},
  booktitle    = {{Proceedings of DATE’05}},
  isbn         = {{0-7695-2288-2}},
  keywords     = {{Hardware, Unified modeling language, Virtual machining, Object oriented modeling, Field programmable gate arrays, Java, Microcontrollers, Embedded software, Real time systems, Documentation}},
  publisher    = {{IEEE}},
  title        = {{{A Model-Based Approach for Executable Specification on Reconfigurable Hardware}}},
  doi          = {{10.1109/DATE.2005.20}},
  year         = {{2005}},
}