---
_id: '2424'
abstract:
- lang: eng
  text: ' Recent generations of high-density and high-speed FPGAs provide a sufficient
    capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid
    CPUs that combine standard CPU cores with reconfigurable coprocessors are an important
    subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded
    on demand while the CPU remains running. However, the lack of high-level design
    tools for partial reconfiguration makes practical implementations a challenging
    task. In this paper, we introduce a design flow to implement hybrid processors
    on Xilinx Virtex. The design flow is based on two techniques, virtual sockets
    and feed-through components, and can efficiently generate partial configurations
    from industry-quality cores. We discuss the design flow and present a fully operational
    audio streaming prototype to demonstrate its feasibility. '
author:
- first_name: Matthias
  full_name: Dyer, Matthias
  last_name: Dyer
- first_name: Christian
  full_name: Plessl, Christian
  id: '16153'
  last_name: Plessl
  orcid: 0000-0001-5728-9982
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Dyer M, Plessl C, Platzner M. Partially Reconfigurable Cores for Xilinx Virtex.
    In: <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>.
    Vol 2438. Lecture Notes in Computer Science (LNCS). Springer; 2002:292-301. doi:<a
    href="https://doi.org/10.1007/3-540-46117-5">10.1007/3-540-46117-5</a>'
  apa: Dyer, M., Plessl, C., &#38; Platzner, M. (2002). Partially Reconfigurable Cores
    for Xilinx Virtex. In <i>Proc. Int. Conf. on Field Programmable Logic and Applications
    (FPL)</i> (Vol. 2438, pp. 292–301). Springer. <a href="https://doi.org/10.1007/3-540-46117-5">https://doi.org/10.1007/3-540-46117-5</a>
  bibtex: '@inproceedings{Dyer_Plessl_Platzner_2002, series={Lecture Notes in Computer
    Science (LNCS)}, title={Partially Reconfigurable Cores for Xilinx Virtex}, volume={2438},
    DOI={<a href="https://doi.org/10.1007/3-540-46117-5">10.1007/3-540-46117-5</a>},
    booktitle={Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)},
    publisher={Springer}, author={Dyer, Matthias and Plessl, Christian and Platzner,
    Marco}, year={2002}, pages={292–301}, collection={Lecture Notes in Computer Science
    (LNCS)} }'
  chicago: Dyer, Matthias, Christian Plessl, and Marco Platzner. “Partially Reconfigurable
    Cores for Xilinx Virtex.” In <i>Proc. Int. Conf. on Field Programmable Logic and
    Applications (FPL)</i>, 2438:292–301. Lecture Notes in Computer Science (LNCS).
    Springer, 2002. <a href="https://doi.org/10.1007/3-540-46117-5">https://doi.org/10.1007/3-540-46117-5</a>.
  ieee: M. Dyer, C. Plessl, and M. Platzner, “Partially Reconfigurable Cores for Xilinx
    Virtex,” in <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>,
    2002, vol. 2438, pp. 292–301.
  mla: Dyer, Matthias, et al. “Partially Reconfigurable Cores for Xilinx Virtex.”
    <i>Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)</i>, vol.
    2438, Springer, 2002, pp. 292–301, doi:<a href="https://doi.org/10.1007/3-540-46117-5">10.1007/3-540-46117-5</a>.
  short: 'M. Dyer, C. Plessl, M. Platzner, in: Proc. Int. Conf. on Field Programmable
    Logic and Applications (FPL), Springer, 2002, pp. 292–301.'
date_created: 2018-04-17T15:14:39Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '518'
- _id: '78'
doi: 10.1007/3-540-46117-5
intvolume: '      2438'
keyword:
- partial reconfiguration
page: 292-301
publication: Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
publisher: Springer
series_title: Lecture Notes in Computer Science (LNCS)
status: public
title: Partially Reconfigurable Cores for Xilinx Virtex
type: conference
user_id: '24135'
volume: 2438
year: '2002'
...