[{"publication":"Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)","citation":{"chicago":"Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” In <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–80. New York, NY, USA: ACM, 2011. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>.","short":"T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.","ama":"Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. In: <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>. ACM; 2011:177-180. doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>","bibtex":"@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY, USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures}, DOI={<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>}, booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM}, author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke, Michael}, year={2011}, pages={177–180} }","mla":"Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.” <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, ACM, 2011, pp. 177–80, doi:<a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>.","apa":"Kenter, T., Platzner, M., Plessl, C., &#38; Kauschke, M. (2011). Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures. <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 177–180. <a href=\"https://doi.org/10.1145/1950413.1950448\">https://doi.org/10.1145/1950413.1950448</a>","ieee":"T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures,” in <i>Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)</i>, 2011, pp. 177–180, doi: <a href=\"https://doi.org/10.1145/1950413.1950448\">10.1145/1950413.1950448</a>."},"quality_controlled":"1","date_created":"2018-04-03T15:08:13Z","place":"New York, NY, USA","type":"conference","keyword":["design space exploration","LLVM","partitioning","performance","estimation","funding-intel"],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"year":"2011","title":"Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures","status":"public","author":[{"id":"3145","last_name":"Kenter","first_name":"Tobias","full_name":"Kenter, Tobias"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","first_name":"Christian","last_name":"Plessl","id":"16153"},{"full_name":"Kauschke, Michael","first_name":"Michael","last_name":"Kauschke"}],"publication_identifier":{"isbn":["978-1-4503-0554-9"]},"date_updated":"2023-09-26T13:45:04Z","page":"177-180","language":[{"iso":"eng"}],"_id":"2200","publisher":"ACM","user_id":"15278","doi":"10.1145/1950413.1950448"},{"author":[{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"},{"full_name":"Thiele, Lothar","first_name":"Lothar","last_name":"Thiele"}],"year":"2006","title":"Optimal Temporal Partitioning based on Slowdown and Retiming","status":"public","date_updated":"2022-01-06T06:56:05Z","_id":"2401","publisher":"IEEE Computer Society","page":"345-348","user_id":"24135","doi":"10.1109/FPT.2006.270344","citation":{"short":"C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.","chicago":"Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 345–48. IEEE Computer Society, 2006. <a href=\"https://doi.org/10.1109/FPT.2006.270344\">https://doi.org/10.1109/FPT.2006.270344</a>.","apa":"Plessl, C., Platzner, M., &#38; Thiele, L. (2006). Optimal Temporal Partitioning based on Slowdown and Retiming. In <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i> (pp. 345–348). IEEE Computer Society. <a href=\"https://doi.org/10.1109/FPT.2006.270344\">https://doi.org/10.1109/FPT.2006.270344</a>","ieee":"C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based on Slowdown and Retiming,” in <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, 2006, pp. 345–348.","ama":"Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown and Retiming. In: <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>. IEEE Computer Society; 2006:345-348. doi:<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>","bibtex":"@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning based on Slowdown and Retiming}, DOI={<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>}, booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar}, year={2006}, pages={345–348} }","mla":"Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown and Retiming.” <i>Proc. Int. Conf. on Field Programmable Technology (ICFPT)</i>, IEEE Computer Society, 2006, pp. 345–48, doi:<a href=\"https://doi.org/10.1109/FPT.2006.270344\">10.1109/FPT.2006.270344</a>."},"publication":"Proc. Int. Conf. on Field Programmable Technology (ICFPT)","abstract":[{"lang":"eng","text":" This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. "}],"date_created":"2018-04-17T13:43:21Z","department":[{"_id":"518"},{"_id":"78"}],"type":"conference","keyword":["temporal partitioning","retiming","ILP"]}]