TY - CONF AU - Kenter, Tobias AU - Platzner, Marco AU - Plessl, Christian AU - Kauschke, Michael ID - 2200 KW - design space exploration KW - LLVM KW - partitioning KW - performance KW - estimation KW - funding-intel SN - 978-1-4503-0554-9 T2 - Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA) TI - Performance Estimation Framework for Automated Exploration of CPU-Accelerator Architectures ER - TY - CONF AB - This paper presents a novel method for optimal temporal partitioning of sequential circuits for time-multiplexed reconfigurable architectures. The method bases on slowdown and retiming and maximizes the circuit's performance during execution while restricting the size of the partitions to respect the resource constraints of the reconfigurable architecture. We provide a mixed integer linear program (MILP) formulation of the problem, which can be solved exactly. In contrast to related work, our approach optimizes performance directly, takes structural modifications of the circuit into account, and is extensible. We present the application of the new method to temporal partitioning for a coarse-grained reconfigurable architecture. AU - Plessl, Christian AU - Platzner, Marco AU - Thiele, Lothar ID - 2401 KW - temporal partitioning KW - retiming KW - ILP T2 - Proc. Int. Conf. on Field Programmable Technology (ICFPT) TI - Optimal Temporal Partitioning based on Slowdown and Retiming ER -