---
_id: '2200'
author:
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Michael
full_name: Kauschke, Michael
last_name: Kauschke
citation:
ama: 'Kenter T, Platzner M, Plessl C, Kauschke M. Performance Estimation Framework
for Automated Exploration of CPU-Accelerator Architectures. In: Proc. Int.
Symp. on Field-Programmable Gate Arrays (FPGA). ACM; 2011:177-180. doi:10.1145/1950413.1950448'
apa: Kenter, T., Platzner, M., Plessl, C., & Kauschke, M. (2011). Performance
Estimation Framework for Automated Exploration of CPU-Accelerator Architectures.
Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA), 177–180. https://doi.org/10.1145/1950413.1950448
bibtex: '@inproceedings{Kenter_Platzner_Plessl_Kauschke_2011, place={New York, NY,
USA}, title={Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures}, DOI={10.1145/1950413.1950448},
booktitle={Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)}, publisher={ACM},
author={Kenter, Tobias and Platzner, Marco and Plessl, Christian and Kauschke,
Michael}, year={2011}, pages={177–180} }'
chicago: 'Kenter, Tobias, Marco Platzner, Christian Plessl, and Michael Kauschke.
“Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures.” In Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA),
177–80. New York, NY, USA: ACM, 2011. https://doi.org/10.1145/1950413.1950448.'
ieee: 'T. Kenter, M. Platzner, C. Plessl, and M. Kauschke, “Performance Estimation
Framework for Automated Exploration of CPU-Accelerator Architectures,” in Proc.
Int. Symp. on Field-Programmable Gate Arrays (FPGA), 2011, pp. 177–180, doi:
10.1145/1950413.1950448.'
mla: Kenter, Tobias, et al. “Performance Estimation Framework for Automated Exploration
of CPU-Accelerator Architectures.” Proc. Int. Symp. on Field-Programmable Gate
Arrays (FPGA), ACM, 2011, pp. 177–80, doi:10.1145/1950413.1950448.
short: 'T. Kenter, M. Platzner, C. Plessl, M. Kauschke, in: Proc. Int. Symp. on
Field-Programmable Gate Arrays (FPGA), ACM, New York, NY, USA, 2011, pp. 177–180.'
date_created: 2018-04-03T15:08:13Z
date_updated: 2023-09-26T13:45:04Z
department:
- _id: '27'
- _id: '518'
- _id: '78'
doi: 10.1145/1950413.1950448
keyword:
- design space exploration
- LLVM
- partitioning
- performance
- estimation
- funding-intel
language:
- iso: eng
page: 177-180
place: New York, NY, USA
publication: Proc. Int. Symp. on Field-Programmable Gate Arrays (FPGA)
publication_identifier:
isbn:
- 978-1-4503-0554-9
publisher: ACM
quality_controlled: '1'
status: public
title: Performance Estimation Framework for Automated Exploration of CPU-Accelerator
Architectures
type: conference
user_id: '15278'
year: '2011'
...
---
_id: '2401'
abstract:
- lang: eng
text: ' This paper presents a novel method for optimal temporal partitioning of
sequential circuits for time-multiplexed reconfigurable architectures. The method
bases on slowdown and retiming and maximizes the circuit''s performance during
execution while restricting the size of the partitions to respect the resource
constraints of the reconfigurable architecture. We provide a mixed integer linear
program (MILP) formulation of the problem, which can be solved exactly. In contrast
to related work, our approach optimizes performance directly, takes structural
modifications of the circuit into account, and is extensible. We present the application
of the new method to temporal partitioning for a coarse-grained reconfigurable
architecture. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Plessl C, Platzner M, Thiele L. Optimal Temporal Partitioning based on Slowdown
and Retiming. In: Proc. Int. Conf. on Field Programmable Technology (ICFPT).
IEEE Computer Society; 2006:345-348. doi:10.1109/FPT.2006.270344'
apa: Plessl, C., Platzner, M., & Thiele, L. (2006). Optimal Temporal Partitioning
based on Slowdown and Retiming. In Proc. Int. Conf. on Field Programmable Technology
(ICFPT) (pp. 345–348). IEEE Computer Society. https://doi.org/10.1109/FPT.2006.270344
bibtex: '@inproceedings{Plessl_Platzner_Thiele_2006, title={Optimal Temporal Partitioning
based on Slowdown and Retiming}, DOI={10.1109/FPT.2006.270344},
booktitle={Proc. Int. Conf. on Field Programmable Technology (ICFPT)}, publisher={IEEE
Computer Society}, author={Plessl, Christian and Platzner, Marco and Thiele, Lothar},
year={2006}, pages={345–348} }'
chicago: Plessl, Christian, Marco Platzner, and Lothar Thiele. “Optimal Temporal
Partitioning Based on Slowdown and Retiming.” In Proc. Int. Conf. on Field
Programmable Technology (ICFPT), 345–48. IEEE Computer Society, 2006. https://doi.org/10.1109/FPT.2006.270344.
ieee: C. Plessl, M. Platzner, and L. Thiele, “Optimal Temporal Partitioning based
on Slowdown and Retiming,” in Proc. Int. Conf. on Field Programmable Technology
(ICFPT), 2006, pp. 345–348.
mla: Plessl, Christian, et al. “Optimal Temporal Partitioning Based on Slowdown
and Retiming.” Proc. Int. Conf. on Field Programmable Technology (ICFPT),
IEEE Computer Society, 2006, pp. 345–48, doi:10.1109/FPT.2006.270344.
short: 'C. Plessl, M. Platzner, L. Thiele, in: Proc. Int. Conf. on Field Programmable
Technology (ICFPT), IEEE Computer Society, 2006, pp. 345–348.'
date_created: 2018-04-17T13:43:21Z
date_updated: 2022-01-06T06:56:05Z
department:
- _id: '518'
- _id: '78'
doi: 10.1109/FPT.2006.270344
keyword:
- temporal partitioning
- retiming
- ILP
page: 345-348
publication: Proc. Int. Conf. on Field Programmable Technology (ICFPT)
publisher: IEEE Computer Society
status: public
title: Optimal Temporal Partitioning based on Slowdown and Retiming
type: conference
user_id: '24135'
year: '2006'
...