@inproceedings{10676,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{2017 International Conference on Field Programmable Technology (ICFPT)}},
  keywords     = {{Linux, cache storage, microprocessor chips, multiprocessing systems, LEON3-Linux based multicore processor, MiBench suite, block sizes, cache adaptation, evolvable caches, memory-to-cache-index mapping function, processor caches, reconfigurable cache mapping optimization, reconfigurable hardware technology, replacement strategies, standard Linux OS, time a complete hardware implementation, Hardware, Indexes, Linux, Measurement, Multicore processing, Optimization, Training}},
  pages        = {{215--218}},
  title        = {{{Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}}},
  doi          = {{10.1109/FPT.2017.8280144}},
  year         = {{2017}},
}

@inproceedings{48856,
  abstract     = {{There exist many optimal or heuristic priority rules for machine scheduling problems, which can easily be integrated into single-objective evolutionary algorithms via mutation operators. However, in the multi-objective case, simultaneously applying different priorities for different objectives may cause severe disruptions in the genome and may lead to inferior solutions. In this paper, we combine an existing mutation operator concept with new insights from detailed observation of the structure of solutions for multi-objective machine scheduling problems. This allows the comprehensive integration of priority rules to produce better Pareto-front approximations. We evaluate the extended operator concept compared to standard swap mutation and the stand-alone components of our hybrid scheme, which performs best in all evaluated cases.}},
  author       = {{Bossek, Jakob and Grimme, Christian}},
  booktitle    = {{2017 IEEE Symposium Series on Computational Intelligence (SSCI)}},
  keywords     = {{Evolutionary computation, Processor scheduling, Schedules, Scheduling, Sociology, Standards, Statistics}},
  pages        = {{1–8}},
  title        = {{{An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling}}},
  doi          = {{10.1109/SSCI.2017.8285224}},
  year         = {{2017}},
}

@inproceedings{10673,
  author       = {{Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}},
  keywords     = {{cache storage, field programmable gate arrays, multiprocessing systems, parallel architectures, reconfigurable architectures, FPGA, dynamic reconfiguration, evolvable cache mapping, many-core architecture, memory-to-cache address mapping function, microarchitectural optimization, multicore architecture, nature-inspired optimization, parallelization degrees, processor, reconfigurable cache mapping, reconfigurable computing, Field programmable gate arrays, Software, Tuning}},
  pages        = {{1--7}},
  title        = {{{Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}}},
  doi          = {{10.1109/AHS.2015.7231178}},
  year         = {{2015}},
}

@inproceedings{10677,
  author       = {{Ho, Nam and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}},
  keywords     = {{Linux, cache storage, embedded systems, granular computing, multiprocessing systems, reconfigurable architectures, Leon3 SPARe processor, custom logic events, evolvable-self-adaptable processor cache, fine granular profiling, integer unit events, measurement infrastructure, microarchitectural events, multicore embedded system, perf_event standard Linux performance measurement interface, processor properties, run-time reconfigurable memory-to-cache address mapping engine, run-time reconfigurable multicore infrastructure, split-level caching, Field programmable gate arrays, Frequency locked loops, Irrigation, Phasor measurement units, Registers, Weaving}},
  pages        = {{31--37}},
  title        = {{{Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}}},
  doi          = {{10.1109/ICES.2014.7008719}},
  year         = {{2014}},
}

@inproceedings{36920,
  abstract     = {{In the electronic system development, energy consumption is clearly becoming one of the most important design concerns. From the system level point of view, Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS) are two mostly applied techniques to adjust the tradeoff between the performance and power dissipation at runtime. In this paper, we study the problem of combined application of both techniques with regard to hard real-time systems running on cluster-based multi-core processors. To optimize the processor energy consumption, a heuristic based on simulated annealing with efficient termination criterion is proposed. The experiment results show that the proposed algorithm outperforms the existing approaches in terms of the energy reduction. }},
  author       = {{He, Da and Müller, Wolfgang}},
  booktitle    = {{Proceedings of the International Conference on Applied Computing (AC)}},
  editor       = {{Weghorn, Hans}},
  isbn         = {{978-989-8533-20-3 }},
  keywords     = {{Dynamic Power Management, Dynamic Voltage and Frequency Scaling, Hard Real-Time, Multi-core Processor}},
  title        = {{{An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors}}},
  year         = {{2013}},
}

@inproceedings{37009,
  abstract     = {{Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties.}},
  author       = {{Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}},
  booktitle    = {{Proceedings of DATE’10}},
  keywords     = {{Operating systems, Real time systems, Timing, Hardware, Analytical models, Embedded software, Software systems, Processor scheduling, Software performance, Performance analysis}},
  location     = {{Dresden}},
  publisher    = {{IEEE}},
  title        = {{{Assertion-Based Verification of RTOS Properties}}},
  doi          = {{10.1109/DATE.2010.5457130}},
  year         = {{2010}},
}

@inproceedings{39526,
  abstract     = {{The main goal of the article is to evaluate the suitability of visual programming languages, i.e., Pictorial Janus (K. Kahn and V. Saraswat, 1990), for the modeling of complex systems and their control strategies. These systems can be seen as networks of communicating objects. Objects select strategies for suitable actions based on incoming messages. Our field of investigation is in computer integrated manufacturing considering the example of a car manufacturing cell. This color sorting assembly buffer (CSAB) schedules jobs in queues. The jobs represent car bodies scheduled in feeder lines for the enameling. Feeder lines collect raw bodies to blocks. Blocks are bodies which are to be enameled by the same color. This organization decreases the cost of expensive change-over-times when changing colors at the enamelling. Blocks of bodies are dislocated from the queue and enameled successively. Contradictory system goals, such as minimizing color changes and preserving the sequence of incoming jobs, have to be regarded by appropriate control strategies. Due to the complexity of this (NP complete) problem and to real time requirements for online control there are no optimal strategies on hand. Consequently, suitable heuristics have to be developed. Often they are designed applying a trial-and-error method. A modeling framework has to support the rapid prototyping of these systems as well as an expressive end user oriented representation. Both are essential requirements since end users need other visualization techniques than experienced designers due to their different knowledge and interests.}},
  author       = {{Geiger, Christian and Hunstock, R. and Lehrenfeld, Georg and Müller, Wolfgang and Quintanilla, J.  and Tahedl, C.  and Weber, A.}},
  booktitle    = {{Proceedings of the 1996 IEEE Symposium on Visual Languages}},
  isbn         = {{0-8186-7508-X}},
  keywords     = {{Computer integrated manufacturing, Job shop scheduling, Processor scheduling, Computer languages, Control system synthesis, Computer aided manufacturing, Sorting, Assembly, Costs, Control systems}},
  title        = {{{Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing}}},
  doi          = {{10.1109/VL.1996.545302}},
  year         = {{1996}},
}