TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10676 KW - Linux KW - cache storage KW - microprocessor chips KW - multiprocessing systems KW - LEON3-Linux based multicore processor KW - MiBench suite KW - block sizes KW - cache adaptation KW - evolvable caches KW - memory-to-cache-index mapping function KW - processor caches KW - reconfigurable cache mapping optimization KW - reconfigurable hardware technology KW - replacement strategies KW - standard Linux OS KW - time a complete hardware implementation KW - Hardware KW - Indexes KW - Linux KW - Measurement KW - Multicore processing KW - Optimization KW - Training T2 - 2017 International Conference on Field Programmable Technology (ICFPT) TI - Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor ER - TY - CONF AB - There exist many optimal or heuristic priority rules for machine scheduling problems, which can easily be integrated into single-objective evolutionary algorithms via mutation operators. However, in the multi-objective case, simultaneously applying different priorities for different objectives may cause severe disruptions in the genome and may lead to inferior solutions. In this paper, we combine an existing mutation operator concept with new insights from detailed observation of the structure of solutions for multi-objective machine scheduling problems. This allows the comprehensive integration of priority rules to produce better Pareto-front approximations. We evaluate the extended operator concept compared to standard swap mutation and the stand-alone components of our hybrid scheme, which performs best in all evaluated cases. AU - Bossek, Jakob AU - Grimme, Christian ID - 48856 KW - Evolutionary computation KW - Processor scheduling KW - Schedules KW - Scheduling KW - Sociology KW - Standards KW - Statistics T2 - 2017 IEEE Symposium Series on Computational Intelligence (SSCI) TI - An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling ER - TY - CONF AU - Ho, Nam AU - Ahmed, Abdullah Fathi AU - Kaufmann, Paul AU - Platzner, Marco ID - 10673 KW - cache storage KW - field programmable gate arrays KW - multiprocessing systems KW - parallel architectures KW - reconfigurable architectures KW - FPGA KW - dynamic reconfiguration KW - evolvable cache mapping KW - many-core architecture KW - memory-to-cache address mapping function KW - microarchitectural optimization KW - multicore architecture KW - nature-inspired optimization KW - parallelization degrees KW - processor KW - reconfigurable cache mapping KW - reconfigurable computing KW - Field programmable gate arrays KW - Software KW - Tuning T2 - Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) TI - Microarchitectural optimization by means of reconfigurable and evolvable cache mappings ER - TY - CONF AU - Ho, Nam AU - Kaufmann, Paul AU - Platzner, Marco ID - 10677 KW - Linux KW - cache storage KW - embedded systems KW - granular computing KW - multiprocessing systems KW - reconfigurable architectures KW - Leon3 SPARe processor KW - custom logic events KW - evolvable-self-adaptable processor cache KW - fine granular profiling KW - integer unit events KW - measurement infrastructure KW - microarchitectural events KW - multicore embedded system KW - perf_event standard Linux performance measurement interface KW - processor properties KW - run-time reconfigurable memory-to-cache address mapping engine KW - run-time reconfigurable multicore infrastructure KW - split-level caching KW - Field programmable gate arrays KW - Frequency locked loops KW - Irrigation KW - Phasor measurement units KW - Registers KW - Weaving T2 - 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) TI - Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure ER - TY - CONF AB - In the electronic system development, energy consumption is clearly becoming one of the most important design concerns. From the system level point of view, Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS) are two mostly applied techniques to adjust the tradeoff between the performance and power dissipation at runtime. In this paper, we study the problem of combined application of both techniques with regard to hard real-time systems running on cluster-based multi-core processors. To optimize the processor energy consumption, a heuristic based on simulated annealing with efficient termination criterion is proposed. The experiment results show that the proposed algorithm outperforms the existing approaches in terms of the energy reduction. AU - He, Da AU - Müller, Wolfgang ED - Weghorn, Hans ID - 36920 KW - Dynamic Power Management KW - Dynamic Voltage and Frequency Scaling KW - Hard Real-Time KW - Multi-core Processor SN - 978-989-8533-20-3 T2 - Proceedings of the International Conference on Applied Computing (AC) TI - An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors ER - TY - CONF AB - Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties. AU - Oliveira, Marcio F. S. AU - Zabel, Henning AU - Müller, Wolfgang ID - 37009 KW - Operating systems KW - Real time systems KW - Timing KW - Hardware KW - Analytical models KW - Embedded software KW - Software systems KW - Processor scheduling KW - Software performance KW - Performance analysis T2 - Proceedings of DATE’10 TI - Assertion-Based Verification of RTOS Properties ER - TY - CONF AB - The main goal of the article is to evaluate the suitability of visual programming languages, i.e., Pictorial Janus (K. Kahn and V. Saraswat, 1990), for the modeling of complex systems and their control strategies. These systems can be seen as networks of communicating objects. Objects select strategies for suitable actions based on incoming messages. Our field of investigation is in computer integrated manufacturing considering the example of a car manufacturing cell. This color sorting assembly buffer (CSAB) schedules jobs in queues. The jobs represent car bodies scheduled in feeder lines for the enameling. Feeder lines collect raw bodies to blocks. Blocks are bodies which are to be enameled by the same color. This organization decreases the cost of expensive change-over-times when changing colors at the enamelling. Blocks of bodies are dislocated from the queue and enameled successively. Contradictory system goals, such as minimizing color changes and preserving the sequence of incoming jobs, have to be regarded by appropriate control strategies. Due to the complexity of this (NP complete) problem and to real time requirements for online control there are no optimal strategies on hand. Consequently, suitable heuristics have to be developed. Often they are designed applying a trial-and-error method. A modeling framework has to support the rapid prototyping of these systems as well as an expressive end user oriented representation. Both are essential requirements since end users need other visualization techniques than experienced designers due to their different knowledge and interests. AU - Geiger, Christian AU - Hunstock, R. AU - Lehrenfeld, Georg AU - Müller, Wolfgang AU - Quintanilla, J. AU - Tahedl, C. AU - Weber, A. ID - 39526 KW - Computer integrated manufacturing KW - Job shop scheduling KW - Processor scheduling KW - Computer languages KW - Control system synthesis KW - Computer aided manufacturing KW - Sorting KW - Assembly KW - Costs KW - Control systems SN - 0-8186-7508-X T2 - Proceedings of the 1996 IEEE Symposium on Visual Languages TI - Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing ER -