--- _id: '10676' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: 2017 International Conference on Field Programmable Technology (ICFPT). ; 2017:215-218. doi:10.1109/FPT.2017.8280144' apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In 2017 International Conference on Field Programmable Technology (ICFPT) (pp. 215–218). https://doi.org/10.1109/FPT.2017.8280144' bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={10.1109/FPT.2017.8280144}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }' chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In 2017 International Conference on Field Programmable Technology (ICFPT), 215–18, 2017. https://doi.org/10.1109/FPT.2017.8280144.' ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.' mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–18, doi:10.1109/FPT.2017.8280144.' short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.' date_created: 2019-07-10T11:22:59Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1109/FPT.2017.8280144 keyword: - Linux - cache storage - microprocessor chips - multiprocessing systems - LEON3-Linux based multicore processor - MiBench suite - block sizes - cache adaptation - evolvable caches - memory-to-cache-index mapping function - processor caches - reconfigurable cache mapping optimization - reconfigurable hardware technology - replacement strategies - standard Linux OS - time a complete hardware implementation - Hardware - Indexes - Linux - Measurement - Multicore processing - Optimization - Training language: - iso: eng page: 215-218 publication: 2017 International Conference on Field Programmable Technology (ICFPT) status: public title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor' type: conference user_id: '398' year: '2017' ... --- _id: '48856' abstract: - lang: eng text: There exist many optimal or heuristic priority rules for machine scheduling problems, which can easily be integrated into single-objective evolutionary algorithms via mutation operators. However, in the multi-objective case, simultaneously applying different priorities for different objectives may cause severe disruptions in the genome and may lead to inferior solutions. In this paper, we combine an existing mutation operator concept with new insights from detailed observation of the structure of solutions for multi-objective machine scheduling problems. This allows the comprehensive integration of priority rules to produce better Pareto-front approximations. We evaluate the extended operator concept compared to standard swap mutation and the stand-alone components of our hybrid scheme, which performs best in all evaluated cases. author: - first_name: Jakob full_name: Bossek, Jakob id: '102979' last_name: Bossek orcid: 0000-0002-4121-4668 - first_name: Christian full_name: Grimme, Christian last_name: Grimme citation: ama: 'Bossek J, Grimme C. An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling. In: 2017 IEEE Symposium Series on Computational Intelligence (SSCI). ; 2017:1–8. doi:10.1109/SSCI.2017.8285224' apa: Bossek, J., & Grimme, C. (2017). An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling. 2017 IEEE Symposium Series on Computational Intelligence (SSCI), 1–8. https://doi.org/10.1109/SSCI.2017.8285224 bibtex: '@inproceedings{Bossek_Grimme_2017, title={An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling}, DOI={10.1109/SSCI.2017.8285224}, booktitle={2017 IEEE Symposium Series on Computational Intelligence (SSCI)}, author={Bossek, Jakob and Grimme, Christian}, year={2017}, pages={1–8} }' chicago: Bossek, Jakob, and Christian Grimme. “An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling.” In 2017 IEEE Symposium Series on Computational Intelligence (SSCI), 1–8, 2017. https://doi.org/10.1109/SSCI.2017.8285224. ieee: 'J. Bossek and C. Grimme, “An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling,” in 2017 IEEE Symposium Series on Computational Intelligence (SSCI), 2017, pp. 1–8, doi: 10.1109/SSCI.2017.8285224.' mla: Bossek, Jakob, and Christian Grimme. “An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling.” 2017 IEEE Symposium Series on Computational Intelligence (SSCI), 2017, pp. 1–8, doi:10.1109/SSCI.2017.8285224. short: 'J. Bossek, C. Grimme, in: 2017 IEEE Symposium Series on Computational Intelligence (SSCI), 2017, pp. 1–8.' date_created: 2023-11-14T15:58:54Z date_updated: 2023-12-13T10:44:36Z department: - _id: '819' doi: 10.1109/SSCI.2017.8285224 extern: '1' keyword: - Evolutionary computation - Processor scheduling - Schedules - Scheduling - Sociology - Standards - Statistics language: - iso: eng page: 1–8 publication: 2017 IEEE Symposium Series on Computational Intelligence (SSCI) publication_status: published status: public title: An Extended Mutation-Based Priority-Rule Integration Concept for Multi-Objective Machine Scheduling type: conference user_id: '102979' year: '2017' ... --- _id: '10673' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Abdullah Fathi full_name: Ahmed, Abdullah Fathi last_name: Ahmed - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178' apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178 bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }' chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178. ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7. mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178. short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.' date_created: 2019-07-10T11:18:00Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1109/AHS.2015.7231178 keyword: - cache storage - field programmable gate arrays - multiprocessing systems - parallel architectures - reconfigurable architectures - FPGA - dynamic reconfiguration - evolvable cache mapping - many-core architecture - memory-to-cache address mapping function - microarchitectural optimization - multicore architecture - nature-inspired optimization - parallelization degrees - processor - reconfigurable cache mapping - reconfigurable computing - Field programmable gate arrays - Software - Tuning language: - iso: eng page: 1-7 project: - _id: '31' grant_number: '257906' name: Engineering Proprioception in Computing Systems publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) status: public title: Microarchitectural optimization by means of reconfigurable and evolvable cache mappings type: conference user_id: '3118' year: '2015' ... --- _id: '10677' author: - first_name: Nam full_name: Ho, Nam last_name: Ho - first_name: Paul full_name: Kaufmann, Paul last_name: Kaufmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES). ; 2014:31-37. doi:10.1109/ICES.2014.7008719' apa: 'Ho, N., Kaufmann, P., & Platzner, M. (2014). Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure. In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) (pp. 31–37). https://doi.org/10.1109/ICES.2014.7008719' bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure}, DOI={10.1109/ICES.2014.7008719}, booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }' chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” In 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 31–37, 2014. https://doi.org/10.1109/ICES.2014.7008719.' ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure,” in 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.' mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core Infrastructure.” 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37, doi:10.1109/ICES.2014.7008719.' short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES), 2014, pp. 31–37.' date_created: 2019-07-10T11:23:00Z date_updated: 2022-01-06T06:50:49Z department: - _id: '78' doi: 10.1109/ICES.2014.7008719 keyword: - Linux - cache storage - embedded systems - granular computing - multiprocessing systems - reconfigurable architectures - Leon3 SPARe processor - custom logic events - evolvable-self-adaptable processor cache - fine granular profiling - integer unit events - measurement infrastructure - microarchitectural events - multicore embedded system - perf_event standard Linux performance measurement interface - processor properties - run-time reconfigurable memory-to-cache address mapping engine - run-time reconfigurable multicore infrastructure - split-level caching - Field programmable gate arrays - Frequency locked loops - Irrigation - Phasor measurement units - Registers - Weaving language: - iso: eng page: 31-37 publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES) status: public title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure' type: conference user_id: '3118' year: '2014' ... --- _id: '36920' abstract: - lang: eng text: 'In the electronic system development, energy consumption is clearly becoming one of the most important design concerns. From the system level point of view, Dynamic Power Management (DPM) and Dynamic Voltage and Frequency Scaling (DVFS) are two mostly applied techniques to adjust the tradeoff between the performance and power dissipation at runtime. In this paper, we study the problem of combined application of both techniques with regard to hard real-time systems running on cluster-based multi-core processors. To optimize the processor energy consumption, a heuristic based on simulated annealing with efficient termination criterion is proposed. The experiment results show that the proposed algorithm outperforms the existing approaches in terms of the energy reduction. ' author: - first_name: Da full_name: He, Da last_name: He - first_name: Wolfgang full_name: Müller, Wolfgang id: '16243' last_name: Müller citation: ama: 'He D, Müller W. An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In: Weghorn H, ed. Proceedings of the International Conference on Applied Computing (AC). ; 2013.' apa: He, D., & Müller, W. (2013). An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors. In H. Weghorn (Ed.), Proceedings of the International Conference on Applied Computing (AC). bibtex: '@inproceedings{He_Müller_2013, place={Fort Worth, Texas, USA}, title={An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors}, booktitle={Proceedings of the International Conference on Applied Computing (AC)}, author={He, Da and Müller, Wolfgang}, editor={Weghorn, Hans}, year={2013} }' chicago: He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” In Proceedings of the International Conference on Applied Computing (AC), edited by Hans Weghorn. Fort Worth, Texas, USA, 2013. ieee: D. He and W. Müller, “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors,” in Proceedings of the International Conference on Applied Computing (AC), 2013. mla: He, Da, and Wolfgang Müller. “An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors.” Proceedings of the International Conference on Applied Computing (AC), edited by Hans Weghorn, 2013. short: 'D. He, W. Müller, in: H. Weghorn (Ed.), Proceedings of the International Conference on Applied Computing (AC), Fort Worth, Texas, USA, 2013.' date_created: 2023-01-16T12:12:58Z date_updated: 2023-01-16T12:15:44Z department: - _id: '672' editor: - first_name: Hans full_name: Weghorn, Hans last_name: Weghorn keyword: - Dynamic Power Management - Dynamic Voltage and Frequency Scaling - Hard Real-Time - Multi-core Processor language: - iso: eng place: Fort Worth, Texas, USA publication: Proceedings of the International Conference on Applied Computing (AC) publication_identifier: isbn: - '978-989-8533-20-3 ' status: public title: An Energy-Efficient Heuristic for Hard Real-Time System on Multi-Core Processors type: conference user_id: '5786' year: '2013' ... --- _id: '37009' abstract: - lang: eng text: Today, mobile and embedded real time systems have to cope with the migration and allocation of multiple software tasks running on top of a real time operating system (RTOS) residing on one or several processors. For scaling of each task set and processor configuration, instruction set simulation and worst case timing analysis are typically applied. This paper presents a complementary approach for the verification of RTOS properties based on an abstract RTOS-Model in SystemC. We apply IEEE P1850 PSL for which we present an approach and first experiences for the assertion-based verification of RTOS properties. author: - first_name: Marcio F. S. full_name: Oliveira, Marcio F. S. last_name: Oliveira - first_name: Henning full_name: Zabel, Henning last_name: Zabel - first_name: Wolfgang full_name: Müller, Wolfgang id: '16243' last_name: Müller citation: ama: 'Oliveira MFS, Zabel H, Müller W. Assertion-Based Verification of RTOS Properties. In: Proceedings of DATE’10. IEEE; 2010. doi:10.1109/DATE.2010.5457130' apa: Oliveira, M. F. S., Zabel, H., & Müller, W. (2010). Assertion-Based Verification of RTOS Properties. Proceedings of DATE’10. 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden. https://doi.org/10.1109/DATE.2010.5457130 bibtex: '@inproceedings{Oliveira_Zabel_Müller_2010, place={Dresden}, title={Assertion-Based Verification of RTOS Properties}, DOI={10.1109/DATE.2010.5457130}, booktitle={Proceedings of DATE’10}, publisher={IEEE}, author={Oliveira, Marcio F. S. and Zabel, Henning and Müller, Wolfgang}, year={2010} }' chicago: 'Oliveira, Marcio F. S., Henning Zabel, and Wolfgang Müller. “Assertion-Based Verification of RTOS Properties.” In Proceedings of DATE’10. Dresden: IEEE, 2010. https://doi.org/10.1109/DATE.2010.5457130.' ieee: 'M. F. S. Oliveira, H. Zabel, and W. Müller, “Assertion-Based Verification of RTOS Properties,” presented at the 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), Dresden, 2010, doi: 10.1109/DATE.2010.5457130.' mla: Oliveira, Marcio F. S., et al. “Assertion-Based Verification of RTOS Properties.” Proceedings of DATE’10, IEEE, 2010, doi:10.1109/DATE.2010.5457130. short: 'M.F.S. Oliveira, H. Zabel, W. Müller, in: Proceedings of DATE’10, IEEE, Dresden, 2010.' conference: location: Dresden name: 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) date_created: 2023-01-17T09:15:10Z date_updated: 2023-01-17T09:15:18Z department: - _id: '672' doi: 10.1109/DATE.2010.5457130 keyword: - Operating systems - Real time systems - Timing - Hardware - Analytical models - Embedded software - Software systems - Processor scheduling - Software performance - Performance analysis language: - iso: eng place: Dresden publication: Proceedings of DATE’10 publisher: IEEE status: public title: Assertion-Based Verification of RTOS Properties type: conference user_id: '5786' year: '2010' ... --- _id: '39526' abstract: - lang: eng text: The main goal of the article is to evaluate the suitability of visual programming languages, i.e., Pictorial Janus (K. Kahn and V. Saraswat, 1990), for the modeling of complex systems and their control strategies. These systems can be seen as networks of communicating objects. Objects select strategies for suitable actions based on incoming messages. Our field of investigation is in computer integrated manufacturing considering the example of a car manufacturing cell. This color sorting assembly buffer (CSAB) schedules jobs in queues. The jobs represent car bodies scheduled in feeder lines for the enameling. Feeder lines collect raw bodies to blocks. Blocks are bodies which are to be enameled by the same color. This organization decreases the cost of expensive change-over-times when changing colors at the enamelling. Blocks of bodies are dislocated from the queue and enameled successively. Contradictory system goals, such as minimizing color changes and preserving the sequence of incoming jobs, have to be regarded by appropriate control strategies. Due to the complexity of this (NP complete) problem and to real time requirements for online control there are no optimal strategies on hand. Consequently, suitable heuristics have to be developed. Often they are designed applying a trial-and-error method. A modeling framework has to support the rapid prototyping of these systems as well as an expressive end user oriented representation. Both are essential requirements since end users need other visualization techniques than experienced designers due to their different knowledge and interests. author: - first_name: Christian full_name: Geiger, Christian last_name: Geiger - first_name: R. full_name: Hunstock, R. last_name: Hunstock - first_name: Georg full_name: Lehrenfeld, Georg last_name: Lehrenfeld - first_name: Wolfgang full_name: Müller, Wolfgang id: '16243' last_name: Müller - first_name: 'J. ' full_name: 'Quintanilla, J. ' last_name: Quintanilla - first_name: 'C. ' full_name: 'Tahedl, C. ' last_name: Tahedl - first_name: A. full_name: Weber, A. last_name: Weber citation: ama: 'Geiger C, Hunstock R, Lehrenfeld G, et al. Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing. In: Proceedings of the 1996 IEEE Symposium on Visual Languages. ; 1996. doi:10.1109/VL.1996.545302' apa: Geiger, C., Hunstock, R., Lehrenfeld, G., Müller, W., Quintanilla, J., Tahedl, C., & Weber, A. (1996). Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing. Proceedings of the 1996 IEEE Symposium on Visual Languages. https://doi.org/10.1109/VL.1996.545302 bibtex: '@inproceedings{Geiger_Hunstock_Lehrenfeld_Müller_Quintanilla_Tahedl_Weber_1996, place={Boulder, CO, USA}, title={Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing}, DOI={10.1109/VL.1996.545302}, booktitle={Proceedings of the 1996 IEEE Symposium on Visual Languages}, author={Geiger, Christian and Hunstock, R. and Lehrenfeld, Georg and Müller, Wolfgang and Quintanilla, J. and Tahedl, C. and Weber, A.}, year={1996} }' chicago: Geiger, Christian, R. Hunstock, Georg Lehrenfeld, Wolfgang Müller, J. Quintanilla, C. Tahedl, and A. Weber. “Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing.” In Proceedings of the 1996 IEEE Symposium on Visual Languages. Boulder, CO, USA, 1996. https://doi.org/10.1109/VL.1996.545302. ieee: 'C. Geiger et al., “Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing,” 1996, doi: 10.1109/VL.1996.545302.' mla: Geiger, Christian, et al. “Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing.” Proceedings of the 1996 IEEE Symposium on Visual Languages, 1996, doi:10.1109/VL.1996.545302. short: 'C. Geiger, R. Hunstock, G. Lehrenfeld, W. Müller, J. Quintanilla, C. Tahedl, A. Weber, in: Proceedings of the 1996 IEEE Symposium on Visual Languages, Boulder, CO, USA, 1996.' date_created: 2023-01-24T11:58:56Z date_updated: 2023-01-24T11:59:01Z department: - _id: '672' doi: 10.1109/VL.1996.545302 keyword: - Computer integrated manufacturing - Job shop scheduling - Processor scheduling - Computer languages - Control system synthesis - Computer aided manufacturing - Sorting - Assembly - Costs - Control systems language: - iso: eng place: Boulder, CO, USA publication: Proceedings of the 1996 IEEE Symposium on Visual Languages publication_identifier: isbn: - 0-8186-7508-X status: public title: Visual Modeling and 3D-Representation with a Complete Visual Programming Language --- A Case Study in Manufacturing type: conference user_id: '5786' year: '1996' ...