---
_id: '10673'
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
- first_name: Abdullah Fathi
  full_name: Ahmed, Abdullah Fathi
  last_name: Ahmed
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by
    means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf.
    Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href="https://doi.org/10.1109/AHS.2015.7231178">10.1109/AHS.2015.7231178</a>'
  apa: Ho, N., Ahmed, A. F., Kaufmann, P., &#38; Platzner, M. (2015). Microarchitectural
    optimization by means of reconfigurable and evolvable cache mappings. In <i>Proc.
    NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i> (pp. 1–7). <a href="https://doi.org/10.1109/AHS.2015.7231178">https://doi.org/10.1109/AHS.2015.7231178</a>
  bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural
    optimization by means of reconfigurable and evolvable cache mappings}, DOI={<a
    href="https://doi.org/10.1109/AHS.2015.7231178">10.1109/AHS.2015.7231178</a>},
    booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho,
    Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015},
    pages={1–7} }'
  chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural
    Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In <i>Proc.
    NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 1–7, 2015. <a href="https://doi.org/10.1109/AHS.2015.7231178">https://doi.org/10.1109/AHS.2015.7231178</a>.
  ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization
    by means of reconfigurable and evolvable cache mappings,” in <i>Proc. NASA/ESA
    Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7.
  mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable
    and Evolvable Cache Mappings.” <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems
    (AHS)</i>, 2015, pp. 1–7, doi:<a href="https://doi.org/10.1109/AHS.2015.7231178">10.1109/AHS.2015.7231178</a>.
  short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive
    Hardware and Systems (AHS), 2015, pp. 1–7.'
date_created: 2019-07-10T11:18:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/AHS.2015.7231178
keyword:
- cache storage
- field programmable gate arrays
- multiprocessing systems
- parallel architectures
- reconfigurable architectures
- FPGA
- dynamic reconfiguration
- evolvable cache mapping
- many-core architecture
- memory-to-cache address mapping function
- microarchitectural optimization
- multicore architecture
- nature-inspired optimization
- parallelization degrees
- processor
- reconfigurable cache mapping
- reconfigurable computing
- Field programmable gate arrays
- Software
- Tuning
language:
- iso: eng
page: 1-7
project:
- _id: '31'
  grant_number: '257906'
  name: Engineering Proprioception in Computing Systems
publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)
status: public
title: Microarchitectural optimization by means of reconfigurable and evolvable cache
  mappings
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10677'
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Ho N, Kaufmann P, Platzner M. Towards self-adaptive caches: A run-time reconfigurable
    multi-core infrastructure. In: <i>2014 {IEEE} Intl. Conf. on Evolvable Systems
    (ICES)</i>. ; 2014:31-37. doi:<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>'
  apa: 'Ho, N., Kaufmann, P., &#38; Platzner, M. (2014). Towards self-adaptive caches:
    A run-time reconfigurable multi-core infrastructure. In <i>2014 {IEEE} Intl. Conf.
    on Evolvable Systems (ICES)</i> (pp. 31–37). <a href="https://doi.org/10.1109/ICES.2014.7008719">https://doi.org/10.1109/ICES.2014.7008719</a>'
  bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2014, title={Towards self-adaptive
    caches: A run-time reconfigurable multi-core infrastructure}, DOI={<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>},
    booktitle={2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)}, author={Ho, Nam
    and Kaufmann, Paul and Platzner, Marco}, year={2014}, pages={31–37} }'
  chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Towards Self-Adaptive Caches:
    A Run-Time Reconfigurable Multi-Core Infrastructure.” In <i>2014 {IEEE} Intl.
    Conf. on Evolvable Systems (ICES)</i>, 31–37, 2014. <a href="https://doi.org/10.1109/ICES.2014.7008719">https://doi.org/10.1109/ICES.2014.7008719</a>.'
  ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Towards self-adaptive caches: A run-time
    reconfigurable multi-core infrastructure,” in <i>2014 {IEEE} Intl. Conf. on Evolvable
    Systems (ICES)</i>, 2014, pp. 31–37.'
  mla: 'Ho, Nam, et al. “Towards Self-Adaptive Caches: A Run-Time Reconfigurable Multi-Core
    Infrastructure.” <i>2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)</i>, 2014,
    pp. 31–37, doi:<a href="https://doi.org/10.1109/ICES.2014.7008719">10.1109/ICES.2014.7008719</a>.'
  short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2014 {IEEE} Intl. Conf. on Evolvable
    Systems (ICES), 2014, pp. 31–37.'
date_created: 2019-07-10T11:23:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/ICES.2014.7008719
keyword:
- Linux
- cache storage
- embedded systems
- granular computing
- multiprocessing systems
- reconfigurable architectures
- Leon3 SPARe processor
- custom logic events
- evolvable-self-adaptable processor cache
- fine granular profiling
- integer unit events
- measurement infrastructure
- microarchitectural events
- multicore embedded system
- perf_event standard Linux performance measurement interface
- processor properties
- run-time reconfigurable memory-to-cache address mapping engine
- run-time reconfigurable multicore infrastructure
- split-level caching
- Field programmable gate arrays
- Frequency locked loops
- Irrigation
- Phasor measurement units
- Registers
- Weaving
language:
- iso: eng
page: 31-37
publication: 2014 {IEEE} Intl. Conf. on Evolvable Systems (ICES)
status: public
title: 'Towards self-adaptive caches: A run-time reconfigurable multi-core infrastructure'
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10646'
author:
- first_name: Klaus
  full_name: Danne, Klaus
  last_name: Danne
- first_name: Roland
  full_name: Mühlenbernd, Roland
  last_name: Mühlenbernd
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: Danne K, Mühlenbernd R, Platzner M. Server-based execution of periodic tasks
    on dynamically reconfigurable hardware. <i>IET Computers Digital Techniques</i>.
    2007;1(4):295-302. doi:<a href="https://doi.org/10.1049/iet-cdt:20060186">10.1049/iet-cdt:20060186</a>
  apa: Danne, K., Mühlenbernd, R., &#38; Platzner, M. (2007). Server-based execution
    of periodic tasks on dynamically reconfigurable hardware. <i>IET Computers Digital
    Techniques</i>, <i>1</i>(4), 295–302. <a href="https://doi.org/10.1049/iet-cdt:20060186">https://doi.org/10.1049/iet-cdt:20060186</a>
  bibtex: '@article{Danne_Mühlenbernd_Platzner_2007, title={Server-based execution
    of periodic tasks on dynamically reconfigurable hardware}, volume={1}, DOI={<a
    href="https://doi.org/10.1049/iet-cdt:20060186">10.1049/iet-cdt:20060186</a>},
    number={4}, journal={IET Computers Digital Techniques}, author={Danne, Klaus and
    Mühlenbernd, Roland and Platzner, Marco}, year={2007}, pages={295–302} }'
  chicago: 'Danne, Klaus, Roland Mühlenbernd, and Marco Platzner. “Server-Based Execution
    of Periodic Tasks on Dynamically Reconfigurable Hardware.” <i>IET Computers Digital
    Techniques</i> 1, no. 4 (2007): 295–302. <a href="https://doi.org/10.1049/iet-cdt:20060186">https://doi.org/10.1049/iet-cdt:20060186</a>.'
  ieee: K. Danne, R. Mühlenbernd, and M. Platzner, “Server-based execution of periodic
    tasks on dynamically reconfigurable hardware,” <i>IET Computers Digital Techniques</i>,
    vol. 1, no. 4, pp. 295–302, 2007.
  mla: Danne, Klaus, et al. “Server-Based Execution of Periodic Tasks on Dynamically
    Reconfigurable Hardware.” <i>IET Computers Digital Techniques</i>, vol. 1, no.
    4, 2007, pp. 295–302, doi:<a href="https://doi.org/10.1049/iet-cdt:20060186">10.1049/iet-cdt:20060186</a>.
  short: K. Danne, R. Mühlenbernd, M. Platzner, IET Computers Digital Techniques 1
    (2007) 295–302.
date_created: 2019-07-10T11:10:54Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1049/iet-cdt:20060186
intvolume: '         1'
issue: '4'
keyword:
- reconfigurable architectures
- resource allocation
- device reconfiguration time
- dynamic hardware reconfiguration
- dynamically reconfigurable hardware
- light-weight runtime system
- merge server distribute load
- periodic real-time tasks
- runtime system overheads
- schedulability analysis
- scheduling technique
- server-based execution
- synthesis tool flow
language:
- iso: eng
page: 295-302
publication: IET Computers Digital Techniques
publication_identifier:
  issn:
  - 1751-8601
status: public
title: Server-based execution of periodic tasks on dynamically reconfigurable hardware
type: journal_article
user_id: '3118'
volume: 1
year: '2007'
...