[{"date_created":"2019-07-10T11:22:59Z","department":[{"_id":"78"}],"type":"conference","keyword":["Linux","cache storage","microprocessor chips","multiprocessing systems","LEON3-Linux based multicore processor","MiBench suite","block sizes","cache adaptation","evolvable caches","memory-to-cache-index mapping function","processor caches","reconfigurable cache mapping optimization","reconfigurable hardware technology","replacement strategies","standard Linux OS","time a complete hardware implementation","Hardware","Indexes","Linux","Measurement","Multicore processing","Optimization","Training"],"citation":{"mla":"Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–18, doi:<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>.","apa":"Ho, N., Kaufmann, P., &#38; Platzner, M. (2017). Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i> (pp. 215–218). <a href=\"https://doi.org/10.1109/FPT.2017.8280144\">https://doi.org/10.1109/FPT.2017.8280144</a>","ieee":"N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor,” in <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–218.","short":"N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field Programmable Technology (ICFPT), 2017, pp. 215–218.","ama":"Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor. In: <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>. ; 2017:215-218. doi:<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>","chicago":"Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.” In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>, 215–18, 2017. <a href=\"https://doi.org/10.1109/FPT.2017.8280144\">https://doi.org/10.1109/FPT.2017.8280144</a>.","bibtex":"@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor}, DOI={<a href=\"https://doi.org/10.1109/FPT.2017.8280144\">10.1109/FPT.2017.8280144</a>}, booktitle={2017 International Conference on Field Programmable Technology (ICFPT)}, author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218} }"},"publication":"2017 International Conference on Field Programmable Technology (ICFPT)","language":[{"iso":"eng"}],"_id":"10676","page":"215-218","user_id":"398","doi":"10.1109/FPT.2017.8280144","author":[{"first_name":"Nam","last_name":"Ho","full_name":"Ho, Nam"},{"full_name":"Kaufmann, Paul","last_name":"Kaufmann","first_name":"Paul"},{"id":"398","full_name":"Platzner, Marco","first_name":"Marco","last_name":"Platzner"}],"title":"Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor","status":"public","year":"2017","date_updated":"2022-01-06T06:50:49Z"},{"keyword":["cache storage","field programmable gate arrays","multiprocessing systems","parallel architectures","reconfigurable architectures","FPGA","dynamic reconfiguration","evolvable cache mapping","many-core architecture","memory-to-cache address mapping function","microarchitectural optimization","multicore architecture","nature-inspired optimization","parallelization degrees","processor","reconfigurable cache mapping","reconfigurable computing","Field programmable gate arrays","Software","Tuning"],"type":"conference","department":[{"_id":"78"}],"date_created":"2019-07-10T11:18:00Z","project":[{"name":"Engineering Proprioception in Computing Systems","_id":"31","grant_number":"257906"}],"publication":"Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)","citation":{"short":"N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 1–7, 2015. <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>.","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7.","apa":"Ho, N., Ahmed, A. F., Kaufmann, P., &#38; Platzner, M. (2015). Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i> (pp. 1–7). <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>","bibtex":"@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}, DOI={<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>}, booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015}, pages={1–7} }","ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>","mla":"Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7, doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>."},"user_id":"3118","doi":"10.1109/AHS.2015.7231178","page":"1-7","_id":"10673","language":[{"iso":"eng"}],"date_updated":"2022-01-06T06:50:49Z","year":"2015","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","status":"public","author":[{"full_name":"Ho, Nam","first_name":"Nam","last_name":"Ho"},{"first_name":"Abdullah Fathi","last_name":"Ahmed","full_name":"Ahmed, Abdullah Fathi"},{"last_name":"Kaufmann","first_name":"Paul","full_name":"Kaufmann, Paul"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}]}]