---
_id: '10676'
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Ho N, Kaufmann P, Platzner M. Evolvable caches: Optimization of reconfigurable
    cache mappings for a LEON3/Linux-based multi-core processor. In: <i>2017 International
    Conference on Field Programmable Technology (ICFPT)</i>. ; 2017:215-218. doi:<a
    href="https://doi.org/10.1109/FPT.2017.8280144">10.1109/FPT.2017.8280144</a>'
  apa: 'Ho, N., Kaufmann, P., &#38; Platzner, M. (2017). Evolvable caches: Optimization
    of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor.
    In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>
    (pp. 215–218). <a href="https://doi.org/10.1109/FPT.2017.8280144">https://doi.org/10.1109/FPT.2017.8280144</a>'
  bibtex: '@inproceedings{Ho_Kaufmann_Platzner_2017, title={Evolvable caches: Optimization
    of reconfigurable cache mappings for a LEON3/Linux-based multi-core processor},
    DOI={<a href="https://doi.org/10.1109/FPT.2017.8280144">10.1109/FPT.2017.8280144</a>},
    booktitle={2017 International Conference on Field Programmable Technology (ICFPT)},
    author={Ho, Nam and Kaufmann, Paul and Platzner, Marco}, year={2017}, pages={215–218}
    }'
  chicago: 'Ho, Nam, Paul Kaufmann, and Marco Platzner. “Evolvable Caches: Optimization
    of Reconfigurable Cache Mappings for a LEON3/Linux-Based Multi-Core Processor.”
    In <i>2017 International Conference on Field Programmable Technology (ICFPT)</i>,
    215–18, 2017. <a href="https://doi.org/10.1109/FPT.2017.8280144">https://doi.org/10.1109/FPT.2017.8280144</a>.'
  ieee: 'N. Ho, P. Kaufmann, and M. Platzner, “Evolvable caches: Optimization of reconfigurable
    cache mappings for a LEON3/Linux-based multi-core processor,” in <i>2017 International
    Conference on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–218.'
  mla: 'Ho, Nam, et al. “Evolvable Caches: Optimization of Reconfigurable Cache Mappings
    for a LEON3/Linux-Based Multi-Core Processor.” <i>2017 International Conference
    on Field Programmable Technology (ICFPT)</i>, 2017, pp. 215–18, doi:<a href="https://doi.org/10.1109/FPT.2017.8280144">10.1109/FPT.2017.8280144</a>.'
  short: 'N. Ho, P. Kaufmann, M. Platzner, in: 2017 International Conference on Field
    Programmable Technology (ICFPT), 2017, pp. 215–218.'
date_created: 2019-07-10T11:22:59Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/FPT.2017.8280144
keyword:
- Linux
- cache storage
- microprocessor chips
- multiprocessing systems
- LEON3-Linux based multicore processor
- MiBench suite
- block sizes
- cache adaptation
- evolvable caches
- memory-to-cache-index mapping function
- processor caches
- reconfigurable cache mapping optimization
- reconfigurable hardware technology
- replacement strategies
- standard Linux OS
- time a complete hardware implementation
- Hardware
- Indexes
- Linux
- Measurement
- Multicore processing
- Optimization
- Training
language:
- iso: eng
page: 215-218
publication: 2017 International Conference on Field Programmable Technology (ICFPT)
status: public
title: 'Evolvable caches: Optimization of reconfigurable cache mappings for a LEON3/Linux-based
  multi-core processor'
type: conference
user_id: '398'
year: '2017'
...
---
_id: '10673'
author:
- first_name: Nam
  full_name: Ho, Nam
  last_name: Ho
- first_name: Abdullah Fathi
  full_name: Ahmed, Abdullah Fathi
  last_name: Ahmed
- first_name: Paul
  full_name: Kaufmann, Paul
  last_name: Kaufmann
- first_name: Marco
  full_name: Platzner, Marco
  id: '398'
  last_name: Platzner
citation:
  ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by
    means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf.
    Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href="https://doi.org/10.1109/AHS.2015.7231178">10.1109/AHS.2015.7231178</a>'
  apa: Ho, N., Ahmed, A. F., Kaufmann, P., &#38; Platzner, M. (2015). Microarchitectural
    optimization by means of reconfigurable and evolvable cache mappings. In <i>Proc.
    NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i> (pp. 1–7). <a href="https://doi.org/10.1109/AHS.2015.7231178">https://doi.org/10.1109/AHS.2015.7231178</a>
  bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural
    optimization by means of reconfigurable and evolvable cache mappings}, DOI={<a
    href="https://doi.org/10.1109/AHS.2015.7231178">10.1109/AHS.2015.7231178</a>},
    booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho,
    Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015},
    pages={1–7} }'
  chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural
    Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In <i>Proc.
    NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 1–7, 2015. <a href="https://doi.org/10.1109/AHS.2015.7231178">https://doi.org/10.1109/AHS.2015.7231178</a>.
  ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization
    by means of reconfigurable and evolvable cache mappings,” in <i>Proc. NASA/ESA
    Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7.
  mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable
    and Evolvable Cache Mappings.” <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems
    (AHS)</i>, 2015, pp. 1–7, doi:<a href="https://doi.org/10.1109/AHS.2015.7231178">10.1109/AHS.2015.7231178</a>.
  short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive
    Hardware and Systems (AHS), 2015, pp. 1–7.'
date_created: 2019-07-10T11:18:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/AHS.2015.7231178
keyword:
- cache storage
- field programmable gate arrays
- multiprocessing systems
- parallel architectures
- reconfigurable architectures
- FPGA
- dynamic reconfiguration
- evolvable cache mapping
- many-core architecture
- memory-to-cache address mapping function
- microarchitectural optimization
- multicore architecture
- nature-inspired optimization
- parallelization degrees
- processor
- reconfigurable cache mapping
- reconfigurable computing
- Field programmable gate arrays
- Software
- Tuning
language:
- iso: eng
page: 1-7
project:
- _id: '31'
  grant_number: '257906'
  name: Engineering Proprioception in Computing Systems
publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)
status: public
title: Microarchitectural optimization by means of reconfigurable and evolvable cache
  mappings
type: conference
user_id: '3118'
year: '2015'
...