@inproceedings{10673,
  author       = {{Ho, Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}},
  keywords     = {{cache storage, field programmable gate arrays, multiprocessing systems, parallel architectures, reconfigurable architectures, FPGA, dynamic reconfiguration, evolvable cache mapping, many-core architecture, memory-to-cache address mapping function, microarchitectural optimization, multicore architecture, nature-inspired optimization, parallelization degrees, processor, reconfigurable cache mapping, reconfigurable computing, Field programmable gate arrays, Software, Tuning}},
  pages        = {{1--7}},
  title        = {{{Microarchitectural optimization by means of reconfigurable and evolvable cache mappings}}},
  doi          = {{10.1109/AHS.2015.7231178}},
  year         = {{2015}},
}

@article{10703,
  author       = {{Lübbers, Enno and Platzner, Marco}},
  issn         = {{1539-9087}},
  journal      = {{ACM Transactions on Embedded Computing Systems}},
  keywords     = {{Reconfigurable computing, multithreading, operating systems}},
  number       = {{1}},
  pages        = {{8:1--8:33}},
  title        = {{{ReconOS: Multithreaded Programming for Reconfigurable Computers}}},
  doi          = {{10.1145/1596532.1596540}},
  volume       = {{9}},
  year         = {{2009}},
}

@article{2412,
  abstract     = {{ Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.}},
  author       = {{Enzler, Rolf and Plessl, Christian and Platzner, Marco}},
  journal      = {{Microprocessors and Microsystems}},
  keywords     = {{FPGA, reconfigurable computing, co-simulation, Zippy}},
  number       = {{2-3}},
  pages        = {{63--73}},
  publisher    = {{Elsevier}},
  title        = {{{System-level performance evaluation of reconfigurable processors}}},
  doi          = {{10.1016/j.micpro.2004.06.004}},
  volume       = {{29}},
  year         = {{2005}},
}

@article{2420,
  abstract     = {{ This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. }},
  author       = {{Plessl, Christian and Platzner, Marco}},
  issn         = {{0920-8542}},
  journal      = {{Journal of Supercomputing}},
  keywords     = {{reconfigurable computing, instance-specific acceleration, minimum covering}},
  number       = {{2}},
  pages        = {{109--129}},
  publisher    = {{Kluwer Academic Publishers}},
  title        = {{{Instance-Specific Accelerators for Minimum Covering}}},
  doi          = {{10.1023/a:1024443416592}},
  volume       = {{26}},
  year         = {{2003}},
}