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Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i> (pp. 1–7). <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>","ieee":"N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization by means of reconfigurable and evolvable cache mappings,” in <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 2015, pp. 1–7.","chicago":"Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>, 1–7, 2015. <a href=\"https://doi.org/10.1109/AHS.2015.7231178\">https://doi.org/10.1109/AHS.2015.7231178</a>.","ama":"Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by means of reconfigurable and evolvable cache mappings. In: <i>Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)</i>. ; 2015:1-7. doi:<a href=\"https://doi.org/10.1109/AHS.2015.7231178\">10.1109/AHS.2015.7231178</a>"},"year":"2015","date_created":"2019-07-10T11:18:00Z","author":[{"first_name":"Nam","full_name":"Ho, Nam","last_name":"Ho"},{"first_name":"Abdullah Fathi","last_name":"Ahmed","full_name":"Ahmed, Abdullah Fathi"},{"first_name":"Paul","last_name":"Kaufmann","full_name":"Kaufmann, Paul"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_updated":"2022-01-06T06:50:49Z","doi":"10.1109/AHS.2015.7231178","title":"Microarchitectural optimization by means of reconfigurable and evolvable cache mappings","publication":"Proc. NASA/ESA Conf. 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Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable Computers,” <i>ACM Transactions on Embedded Computing Systems</i>, vol. 9, no. 1, pp. 8:1-8:33, 2009.","ama":"Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable Computers. <i>ACM Transactions on Embedded Computing Systems</i>. 2009;9(1):8:1-8:33. doi:<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>","apa":"Lübbers, E., &#38; Platzner, M. (2009). ReconOS: Multithreaded Programming for Reconfigurable Computers. <i>ACM Transactions on Embedded Computing Systems</i>, <i>9</i>(1), 8:1-8:33. <a href=\"https://doi.org/10.1145/1596532.1596540\">https://doi.org/10.1145/1596532.1596540</a>","short":"E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9 (2009) 8:1-8:33.","mla":"Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for Reconfigurable Computers.” <i>ACM Transactions on Embedded Computing Systems</i>, vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>.","bibtex":"@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming for Reconfigurable Computers}, volume={9}, DOI={<a href=\"https://doi.org/10.1145/1596532.1596540\">10.1145/1596532.1596540</a>}, number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers, Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }"},"year":"2009","issue":"1","publication_identifier":{"issn":["1539-9087"]},"doi":"10.1145/1596532.1596540","title":"ReconOS: Multithreaded Programming for Reconfigurable Computers","volume":9,"author":[{"first_name":"Enno","last_name":"Lübbers","full_name":"Lübbers, Enno"},{"first_name":"Marco","id":"398","full_name":"Platzner, Marco","last_name":"Platzner"}],"date_created":"2019-07-10T11:41:17Z","date_updated":"2022-01-06T06:50:50Z"},{"issue":"2-3","citation":{"bibtex":"@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation of reconfigurable processors}, volume={29}, DOI={<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>}, number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier}, author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005}, pages={63–73} }","short":"R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005) 63–73.","mla":"Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, Elsevier, 2005, pp. 63–73, doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>.","apa":"Enzler, R., Plessl, C., &#38; Platzner, M. (2005). System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>, <i>29</i>(2–3), 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>","ieee":"R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation of reconfigurable processors,” <i>Microprocessors and Microsystems</i>, vol. 29, no. 2–3, pp. 63–73, 2005.","chicago":"Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance Evaluation of Reconfigurable Processors.” <i>Microprocessors and Microsystems</i> 29, no. 2–3 (2005): 63–73. <a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">https://doi.org/10.1016/j.micpro.2004.06.004</a>.","ama":"Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable processors. <i>Microprocessors and Microsystems</i>. 2005;29(2-3):63-73. doi:<a href=\"https://doi.org/10.1016/j.micpro.2004.06.004\">10.1016/j.micpro.2004.06.004</a>"},"page":"63-73","intvolume":"        29","year":"2005","date_created":"2018-04-17T14:36:10Z","author":[{"first_name":"Rolf","last_name":"Enzler","full_name":"Enzler, Rolf"},{"id":"16153","full_name":"Plessl, Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"id":"398","full_name":"Platzner, Marco","last_name":"Platzner","first_name":"Marco"}],"volume":29,"date_updated":"2022-01-06T06:56:07Z","publisher":"Elsevier","doi":"10.1016/j.micpro.2004.06.004","title":"System-level performance evaluation of reconfigurable processors","type":"journal_article","publication":"Microprocessors and Microsystems","status":"public","abstract":[{"text":" Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors.","lang":"eng"}],"user_id":"24135","department":[{"_id":"518"},{"_id":"78"}],"_id":"2412","keyword":["FPGA","reconfigurable computing","co-simulation","Zippy"]},{"date_created":"2018-04-17T15:10:00Z","publisher":"Kluwer Academic Publishers","title":"Instance-Specific Accelerators for Minimum Covering","issue":"2","year":"2003","language":[{"iso":"eng"}],"keyword":["reconfigurable computing","instance-specific acceleration","minimum covering"],"publication":"Journal of Supercomputing","abstract":[{"text":" This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \\& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \\& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. ","lang":"eng"}],"volume":26,"author":[{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"last_name":"Platzner","id":"398","full_name":"Platzner, Marco","first_name":"Marco"}],"date_updated":"2022-01-06T06:56:10Z","doi":"10.1023/a:1024443416592","publication_identifier":{"issn":["0920-8542"]},"page":"109-129","intvolume":"        26","citation":{"short":"C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.","mla":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Journal of Supercomputing</i>, vol. 26, no. 2, Kluwer Academic Publishers, 2003, pp. 109–29, doi:<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>.","bibtex":"@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for Minimum Covering}, volume={26}, DOI={<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>}, number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers}, author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }","apa":"Plessl, C., &#38; Platzner, M. (2003). Instance-Specific Accelerators for Minimum Covering. <i>Journal of Supercomputing</i>, <i>26</i>(2), 109–129. <a href=\"https://doi.org/10.1023/a:1024443416592\">https://doi.org/10.1023/a:1024443416592</a>","ama":"Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering. <i>Journal of Supercomputing</i>. 2003;26(2):109-129. doi:<a href=\"https://doi.org/10.1023/a:1024443416592\">10.1023/a:1024443416592</a>","ieee":"C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,” <i>Journal of Supercomputing</i>, vol. 26, no. 2, pp. 109–129, 2003.","chicago":"Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for Minimum Covering.” <i>Journal of Supercomputing</i> 26, no. 2 (2003): 109–29. <a href=\"https://doi.org/10.1023/a:1024443416592\">https://doi.org/10.1023/a:1024443416592</a>."},"department":[{"_id":"518"},{"_id":"78"}],"user_id":"398","_id":"2420","extern":"1","type":"journal_article","status":"public"}]