TY - CONF AU - Ho, Nam AU - Ahmed, Abdullah Fathi AU - Kaufmann, Paul AU - Platzner, Marco ID - 10673 KW - cache storage KW - field programmable gate arrays KW - multiprocessing systems KW - parallel architectures KW - reconfigurable architectures KW - FPGA KW - dynamic reconfiguration KW - evolvable cache mapping KW - many-core architecture KW - memory-to-cache address mapping function KW - microarchitectural optimization KW - multicore architecture KW - nature-inspired optimization KW - parallelization degrees KW - processor KW - reconfigurable cache mapping KW - reconfigurable computing KW - Field programmable gate arrays KW - Software KW - Tuning T2 - Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS) TI - Microarchitectural optimization by means of reconfigurable and evolvable cache mappings ER - TY - JOUR AU - Lübbers, Enno AU - Platzner, Marco ID - 10703 IS - 1 JF - ACM Transactions on Embedded Computing Systems KW - Reconfigurable computing KW - multithreading KW - operating systems SN - 1539-9087 TI - ReconOS: Multithreaded Programming for Reconfigurable Computers VL - 9 ER - TY - JOUR AB - Reconfigurable architectures that tightly integrate a standard CPU core with a field-programmable hardware structure have recently been receiving impact of these design decisions on the overall system performance is a challenging task. In this paper, we first present a framework for the cycle-accurate performance evaluation of hybrid reconfigurable processors on the system level. Then, we discuss a reconfigurable processor for data-streaming applications, which attaches a coarse-grained reconfigurable unit to the coprocessor interface of a standard embedded CPU core. By means of a case study we evaluate the system-level impact of certain design features for the reconfigurable unit, such as multiple contexts, register replication, and hardware context scheduling. The results illustrate that a system-level evaluation framework is of paramount importance for studying the architectural trade-offs and optimizing design parameters for reconfigurable processors. AU - Enzler, Rolf AU - Plessl, Christian AU - Platzner, Marco ID - 2412 IS - 2-3 JF - Microprocessors and Microsystems KW - FPGA KW - reconfigurable computing KW - co-simulation KW - Zippy TI - System-level performance evaluation of reconfigurable processors VL - 29 ER - TY - JOUR AB - This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch \& bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups. AU - Plessl, Christian AU - Platzner, Marco ID - 2420 IS - 2 JF - Journal of Supercomputing KW - reconfigurable computing KW - instance-specific acceleration KW - minimum covering SN - 0920-8542 TI - Instance-Specific Accelerators for Minimum Covering VL - 26 ER -