---
_id: '10673'
author:
- first_name: Nam
full_name: Ho, Nam
last_name: Ho
- first_name: Abdullah Fathi
full_name: Ahmed, Abdullah Fathi
last_name: Ahmed
- first_name: Paul
full_name: Kaufmann, Paul
last_name: Kaufmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Ho N, Ahmed AF, Kaufmann P, Platzner M. Microarchitectural optimization by
means of reconfigurable and evolvable cache mappings. In: Proc. NASA/ESA Conf.
Adaptive Hardware and Systems (AHS). ; 2015:1-7. doi:10.1109/AHS.2015.7231178'
apa: Ho, N., Ahmed, A. F., Kaufmann, P., & Platzner, M. (2015). Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings. In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS) (pp. 1–7). https://doi.org/10.1109/AHS.2015.7231178
bibtex: '@inproceedings{Ho_Ahmed_Kaufmann_Platzner_2015, title={Microarchitectural
optimization by means of reconfigurable and evolvable cache mappings}, DOI={10.1109/AHS.2015.7231178},
booktitle={Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)}, author={Ho,
Nam and Ahmed, Abdullah Fathi and Kaufmann, Paul and Platzner, Marco}, year={2015},
pages={1–7} }'
chicago: Ho, Nam, Abdullah Fathi Ahmed, Paul Kaufmann, and Marco Platzner. “Microarchitectural
Optimization by Means of Reconfigurable and Evolvable Cache Mappings.” In Proc.
NASA/ESA Conf. Adaptive Hardware and Systems (AHS), 1–7, 2015. https://doi.org/10.1109/AHS.2015.7231178.
ieee: N. Ho, A. F. Ahmed, P. Kaufmann, and M. Platzner, “Microarchitectural optimization
by means of reconfigurable and evolvable cache mappings,” in Proc. NASA/ESA
Conf. Adaptive Hardware and Systems (AHS), 2015, pp. 1–7.
mla: Ho, Nam, et al. “Microarchitectural Optimization by Means of Reconfigurable
and Evolvable Cache Mappings.” Proc. NASA/ESA Conf. Adaptive Hardware and Systems
(AHS), 2015, pp. 1–7, doi:10.1109/AHS.2015.7231178.
short: 'N. Ho, A.F. Ahmed, P. Kaufmann, M. Platzner, in: Proc. NASA/ESA Conf. Adaptive
Hardware and Systems (AHS), 2015, pp. 1–7.'
date_created: 2019-07-10T11:18:00Z
date_updated: 2022-01-06T06:50:49Z
department:
- _id: '78'
doi: 10.1109/AHS.2015.7231178
keyword:
- cache storage
- field programmable gate arrays
- multiprocessing systems
- parallel architectures
- reconfigurable architectures
- FPGA
- dynamic reconfiguration
- evolvable cache mapping
- many-core architecture
- memory-to-cache address mapping function
- microarchitectural optimization
- multicore architecture
- nature-inspired optimization
- parallelization degrees
- processor
- reconfigurable cache mapping
- reconfigurable computing
- Field programmable gate arrays
- Software
- Tuning
language:
- iso: eng
page: 1-7
project:
- _id: '31'
grant_number: '257906'
name: Engineering Proprioception in Computing Systems
publication: Proc. NASA/ESA Conf. Adaptive Hardware and Systems (AHS)
status: public
title: Microarchitectural optimization by means of reconfigurable and evolvable cache
mappings
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10703'
author:
- first_name: Enno
full_name: Lübbers, Enno
last_name: Lübbers
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Lübbers E, Platzner M. ReconOS: Multithreaded Programming for Reconfigurable
Computers. ACM Transactions on Embedded Computing Systems. 2009;9(1):8:1-8:33.
doi:10.1145/1596532.1596540'
apa: 'Lübbers, E., & Platzner, M. (2009). ReconOS: Multithreaded Programming
for Reconfigurable Computers. ACM Transactions on Embedded Computing Systems,
9(1), 8:1-8:33. https://doi.org/10.1145/1596532.1596540'
bibtex: '@article{Lübbers_Platzner_2009, title={ReconOS: Multithreaded Programming
for Reconfigurable Computers}, volume={9}, DOI={10.1145/1596532.1596540},
number={1}, journal={ACM Transactions on Embedded Computing Systems}, author={Lübbers,
Enno and Platzner, Marco}, year={2009}, pages={8:1-8:33} }'
chicago: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming
for Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems
9, no. 1 (2009): 8:1-8:33. https://doi.org/10.1145/1596532.1596540.'
ieee: 'E. Lübbers and M. Platzner, “ReconOS: Multithreaded Programming for Reconfigurable
Computers,” ACM Transactions on Embedded Computing Systems, vol. 9, no.
1, pp. 8:1-8:33, 2009.'
mla: 'Lübbers, Enno, and Marco Platzner. “ReconOS: Multithreaded Programming for
Reconfigurable Computers.” ACM Transactions on Embedded Computing Systems,
vol. 9, no. 1, 2009, pp. 8:1-8:33, doi:10.1145/1596532.1596540.'
short: E. Lübbers, M. Platzner, ACM Transactions on Embedded Computing Systems 9
(2009) 8:1-8:33.
date_created: 2019-07-10T11:41:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1145/1596532.1596540
intvolume: ' 9'
issue: '1'
keyword:
- Reconfigurable computing
- multithreading
- operating systems
language:
- iso: eng
page: 8:1-8:33
publication: ACM Transactions on Embedded Computing Systems
publication_identifier:
issn:
- 1539-9087
status: public
title: 'ReconOS: Multithreaded Programming for Reconfigurable Computers'
type: journal_article
user_id: '3118'
volume: 9
year: '2009'
...
---
_id: '2412'
abstract:
- lang: eng
text: ' Reconfigurable architectures that tightly integrate a standard CPU core
with a field-programmable hardware structure have recently been receiving impact
of these design decisions on the overall system performance is a challenging task.
In this paper, we first present a framework for the cycle-accurate performance
evaluation of hybrid reconfigurable processors on the system level. Then, we discuss
a reconfigurable processor for data-streaming applications, which attaches a coarse-grained
reconfigurable unit to the coprocessor interface of a standard embedded CPU core.
By means of a case study we evaluate the system-level impact of certain design
features for the reconfigurable unit, such as multiple contexts, register replication,
and hardware context scheduling. The results illustrate that a system-level evaluation
framework is of paramount importance for studying the architectural trade-offs
and optimizing design parameters for reconfigurable processors.'
author:
- first_name: Rolf
full_name: Enzler, Rolf
last_name: Enzler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Enzler R, Plessl C, Platzner M. System-level performance evaluation of reconfigurable
processors. Microprocessors and Microsystems. 2005;29(2-3):63-73. doi:10.1016/j.micpro.2004.06.004
apa: Enzler, R., Plessl, C., & Platzner, M. (2005). System-level performance
evaluation of reconfigurable processors. Microprocessors and Microsystems,
29(2–3), 63–73. https://doi.org/10.1016/j.micpro.2004.06.004
bibtex: '@article{Enzler_Plessl_Platzner_2005, title={System-level performance evaluation
of reconfigurable processors}, volume={29}, DOI={10.1016/j.micpro.2004.06.004},
number={2–3}, journal={Microprocessors and Microsystems}, publisher={Elsevier},
author={Enzler, Rolf and Plessl, Christian and Platzner, Marco}, year={2005},
pages={63–73} }'
chicago: 'Enzler, Rolf, Christian Plessl, and Marco Platzner. “System-Level Performance
Evaluation of Reconfigurable Processors.” Microprocessors and Microsystems
29, no. 2–3 (2005): 63–73. https://doi.org/10.1016/j.micpro.2004.06.004.'
ieee: R. Enzler, C. Plessl, and M. Platzner, “System-level performance evaluation
of reconfigurable processors,” Microprocessors and Microsystems, vol. 29,
no. 2–3, pp. 63–73, 2005.
mla: Enzler, Rolf, et al. “System-Level Performance Evaluation of Reconfigurable
Processors.” Microprocessors and Microsystems, vol. 29, no. 2–3, Elsevier,
2005, pp. 63–73, doi:10.1016/j.micpro.2004.06.004.
short: R. Enzler, C. Plessl, M. Platzner, Microprocessors and Microsystems 29 (2005)
63–73.
date_created: 2018-04-17T14:36:10Z
date_updated: 2022-01-06T06:56:07Z
department:
- _id: '518'
- _id: '78'
doi: 10.1016/j.micpro.2004.06.004
intvolume: ' 29'
issue: 2-3
keyword:
- FPGA
- reconfigurable computing
- co-simulation
- Zippy
page: 63-73
publication: Microprocessors and Microsystems
publisher: Elsevier
status: public
title: System-level performance evaluation of reconfigurable processors
type: journal_article
user_id: '24135'
volume: 29
year: '2005'
...
---
_id: '2420'
abstract:
- lang: eng
text: ' This paper presents the acceleration of minimum-cost covering problems by
instance-specific hardware. First, we formulate the minimum-cost covering problem
and discuss a branch \& bound algorithm to solve it. Then we describe instance-specific
hardware architectures that implement branch \& bound in 3-valued logic and use
reduction techniques similar to those found in software solvers. We further present
prototypical accelerator implementations and a corresponding design tool flow.
Our experiments reveal significant raw speedups up to five orders of magnitude
for a set of smaller unate covering problems. Provided that hardware compilation
times can be reduced, we conclude that instance-specific acceleration of hard
minimum-cost covering problems will lead to substantial overall speedups. '
author:
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Plessl C, Platzner M. Instance-Specific Accelerators for Minimum Covering.
Journal of Supercomputing. 2003;26(2):109-129. doi:10.1023/a:1024443416592
apa: Plessl, C., & Platzner, M. (2003). Instance-Specific Accelerators for Minimum
Covering. Journal of Supercomputing, 26(2), 109–129. https://doi.org/10.1023/a:1024443416592
bibtex: '@article{Plessl_Platzner_2003, title={Instance-Specific Accelerators for
Minimum Covering}, volume={26}, DOI={10.1023/a:1024443416592},
number={2}, journal={Journal of Supercomputing}, publisher={Kluwer Academic Publishers},
author={Plessl, Christian and Platzner, Marco}, year={2003}, pages={109–129} }'
chicago: 'Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators
for Minimum Covering.” Journal of Supercomputing 26, no. 2 (2003): 109–29.
https://doi.org/10.1023/a:1024443416592.'
ieee: C. Plessl and M. Platzner, “Instance-Specific Accelerators for Minimum Covering,”
Journal of Supercomputing, vol. 26, no. 2, pp. 109–129, 2003.
mla: Plessl, Christian, and Marco Platzner. “Instance-Specific Accelerators for
Minimum Covering.” Journal of Supercomputing, vol. 26, no. 2, Kluwer Academic
Publishers, 2003, pp. 109–29, doi:10.1023/a:1024443416592.
short: C. Plessl, M. Platzner, Journal of Supercomputing 26 (2003) 109–129.
date_created: 2018-04-17T15:10:00Z
date_updated: 2022-01-06T06:56:10Z
department:
- _id: '518'
- _id: '78'
doi: 10.1023/a:1024443416592
extern: '1'
intvolume: ' 26'
issue: '2'
keyword:
- reconfigurable computing
- instance-specific acceleration
- minimum covering
language:
- iso: eng
page: 109-129
publication: Journal of Supercomputing
publication_identifier:
issn:
- 0920-8542
publisher: Kluwer Academic Publishers
status: public
title: Instance-Specific Accelerators for Minimum Covering
type: journal_article
user_id: '398'
volume: 26
year: '2003'
...