---
_id: '61057'
abstract:
- lang: eng
text: Verification and Validation (V&V) are essential processes in engineering Cyber-Physical
Systems. However, the role of V&V engineers is often not given sufficient attention.
Based on a systematic literature analysis and practical observations, a four-step
method for Test-oriented Resilient Requirements Engineering (ToRRE) is developed.
The steps are planning V&V, executing V&V activities, documenting V&V activities
and analyzing results of V&V activities. Applying ToRRE ensures continuous information
flow and traceability. Engineers are enabled to analyze requirements using engineering
artifacts connected through Model-Based Systems Engineering. Adopting methods
for Model-Based Effect Chain analysis to evaluated test cases and test scenarios,
conclusions on requirements engineering and change management are enabled. The
method is evaluated in an EU research project.
author:
- first_name: Iris
full_name: Gräßler, Iris
id: '47565'
last_name: Gräßler
orcid: 0000-0001-5765-971X
- first_name: Marcel
full_name: Ebel, Marcel
id: '81788'
last_name: Ebel
orcid: https://orcid.org/0009-0007-5400-4436
citation:
ama: 'Gräßler I, Ebel M. Test-oriented Resilient Requirements Engineering (ToRRE):
extending model-based effect chain analysis to verification objectives. In: Proceedings
of the Design Society. Vol 5. Cambridge University Press (CUP); 2025:3031-3040.
doi:10.1017/pds.2025.10317'
apa: 'Gräßler, I., & Ebel, M. (2025). Test-oriented Resilient Requirements Engineering
(ToRRE): extending model-based effect chain analysis to verification objectives.
Proceedings of the Design Society, 5, 3031–3040. https://doi.org/10.1017/pds.2025.10317'
bibtex: '@inproceedings{Gräßler_Ebel_2025, title={Test-oriented Resilient Requirements
Engineering (ToRRE): extending model-based effect chain analysis to verification
objectives}, volume={5}, DOI={10.1017/pds.2025.10317},
booktitle={Proceedings of the Design Society}, publisher={Cambridge University
Press (CUP)}, author={Gräßler, Iris and Ebel, Marcel}, year={2025}, pages={3031–3040}
}'
chicago: 'Gräßler, Iris, and Marcel Ebel. “Test-Oriented Resilient Requirements
Engineering (ToRRE): Extending Model-Based Effect Chain Analysis to Verification
Objectives.” In Proceedings of the Design Society, 5:3031–40. Cambridge
University Press (CUP), 2025. https://doi.org/10.1017/pds.2025.10317.'
ieee: 'I. Gräßler and M. Ebel, “Test-oriented Resilient Requirements Engineering
(ToRRE): extending model-based effect chain analysis to verification objectives,”
in Proceedings of the Design Society, Dallas, Texas, USA, 2025, vol. 5,
pp. 3031–3040, doi: 10.1017/pds.2025.10317.'
mla: 'Gräßler, Iris, and Marcel Ebel. “Test-Oriented Resilient Requirements Engineering
(ToRRE): Extending Model-Based Effect Chain Analysis to Verification Objectives.”
Proceedings of the Design Society, vol. 5, Cambridge University Press (CUP),
2025, pp. 3031–40, doi:10.1017/pds.2025.10317.'
short: 'I. Gräßler, M. Ebel, in: Proceedings of the Design Society, Cambridge University
Press (CUP), 2025, pp. 3031–3040.'
conference:
end_date: 2025-08-14
location: Dallas, Texas, USA
name: 25th International Conference on Engineering Design
start_date: 2025-08-11
date_created: 2025-08-28T12:53:19Z
date_updated: 2025-08-28T13:14:46Z
ddc:
- '620'
department:
- _id: '152'
doi: 10.1017/pds.2025.10317
has_accepted_license: '1'
intvolume: ' 5'
keyword:
- systems engineering (SE)
- product modelling/models
- design methods
- verification & validation
- test cases & test scenarios
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://www.cambridge.org/core/journals/proceedings-of-the-design-society/article/testoriented-resilient-requirements-engineering-torre-extending-modelbased-effect-chain-analysis-to-verification-objectives/F1D33C094BAAF635E4E03519E15A4C08
oa: '1'
page: 3031-3040
project:
- _id: '516'
name: 'CREXDATA: Kritische Maßnahmenplanung über extreme Datenmengen'
publication: Proceedings of the Design Society
publication_identifier:
issn:
- 2732-527X
publication_status: published
publisher: Cambridge University Press (CUP)
quality_controlled: '1'
status: public
title: 'Test-oriented Resilient Requirements Engineering (ToRRE): extending model-based
effect chain analysis to verification objectives'
type: conference
user_id: '81788'
volume: 5
year: '2025'
...
---
_id: '61339'
author:
- first_name: Marius
full_name: Protte, Marius
id: '44549'
last_name: Protte
- first_name: Behnud Mir
full_name: Djawadi, Behnud Mir
last_name: Djawadi
citation:
ama: 'Protte M, Djawadi BM. Human vs. Algorithmic Auditors: The Impact of Entity
Type and Ambiguity on Human Dishonesty. Frontiers in Behavioral Economics.
2025;4:1645749. doi:10.3389/frbhe.2025.1645749'
apa: 'Protte, M., & Djawadi, B. M. (2025). Human vs. Algorithmic Auditors: The
Impact of Entity Type and Ambiguity on Human Dishonesty. Frontiers in Behavioral
Economics, 4, 1645749. https://doi.org/10.3389/frbhe.2025.1645749'
bibtex: '@article{Protte_Djawadi_2025, title={Human vs. Algorithmic Auditors: The
Impact of Entity Type and Ambiguity on Human Dishonesty}, volume={4}, DOI={10.3389/frbhe.2025.1645749},
journal={Frontiers in Behavioral Economics}, author={Protte, Marius and Djawadi,
Behnud Mir}, year={2025}, pages={1645749} }'
chicago: 'Protte, Marius, and Behnud Mir Djawadi. “Human vs. Algorithmic Auditors:
The Impact of Entity Type and Ambiguity on Human Dishonesty.” Frontiers in
Behavioral Economics 4 (2025): 1645749. https://doi.org/10.3389/frbhe.2025.1645749.'
ieee: 'M. Protte and B. M. Djawadi, “Human vs. Algorithmic Auditors: The Impact
of Entity Type and Ambiguity on Human Dishonesty,” Frontiers in Behavioral
Economics, vol. 4, p. 1645749, 2025, doi: 10.3389/frbhe.2025.1645749.'
mla: 'Protte, Marius, and Behnud Mir Djawadi. “Human vs. Algorithmic Auditors: The
Impact of Entity Type and Ambiguity on Human Dishonesty.” Frontiers in Behavioral
Economics, vol. 4, 2025, p. 1645749, doi:10.3389/frbhe.2025.1645749.'
short: M. Protte, B.M. Djawadi, Frontiers in Behavioral Economics 4 (2025) 1645749.
date_created: 2025-09-18T07:52:40Z
date_updated: 2025-09-29T09:31:38Z
doi: 10.3389/frbhe.2025.1645749
intvolume: ' 4'
keyword:
- cheating
- human-machine interaction
- ambiguity
- verification process
- algorithm aversion
- algorithm appreciation
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://www.frontiersin.org/journals/behavioral-economics/articles/10.3389/frbhe.2025.1645749/full
oa: '1'
page: '1645749'
publication: Frontiers in Behavioral Economics
status: public
title: 'Human vs. Algorithmic Auditors: The Impact of Entity Type and Ambiguity on
Human Dishonesty'
type: journal_article
user_id: '44549'
volume: 4
year: '2025'
...
---
_id: '61103'
abstract:
- lang: eng
text: Verification planning for engineering complex systems lacks a systematic procedure
for creating test scenarios. Test scenarios can be generated by combining test
cases, or by integrating test cases into pre-specified scenarios. Based on a systematic
literature analysis a method is developed to simplify verification planning by
creating new test scenarios and enriching existing ones. To assist the V&V engineer
in planning test scenarios, a catalogue of combination premises is created to
support the method. The method is evaluated in the development of a platform for
emergency management. Evaluation proves that the method makes modelling of test
scenarios more efficient.
author:
- first_name: Iris
full_name: Gräßler, Iris
id: '47565'
last_name: Gräßler
orcid: 0000-0001-5765-971X
- first_name: Marcel
full_name: Ebel, Marcel
id: '81788'
last_name: Ebel
orcid: https://orcid.org/0009-0007-5400-4436
- first_name: Jens
full_name: Pottebaum, Jens
id: '405'
last_name: Pottebaum
orcid: http://orcid.org/0000-0001-8778-2989
citation:
ama: 'Gräßler I, Ebel M, Pottebaum J. Method for systematic creation of test scenarios
for early customer involvement. In: Procedia CIRP. Vol 136. Elsevier BV;
2025:213-218. doi:https://doi.org/10.1016/j.procir.2025.08.038'
apa: Gräßler, I., Ebel, M., & Pottebaum, J. (2025). Method for systematic creation
of test scenarios for early customer involvement. Procedia CIRP, 136,
213–218. https://doi.org/10.1016/j.procir.2025.08.038
bibtex: '@inproceedings{Gräßler_Ebel_Pottebaum_2025, title={Method for systematic
creation of test scenarios for early customer involvement}, volume={136}, DOI={https://doi.org/10.1016/j.procir.2025.08.038},
booktitle={Procedia CIRP}, publisher={Elsevier BV}, author={Gräßler, Iris and
Ebel, Marcel and Pottebaum, Jens}, year={2025}, pages={213–218} }'
chicago: Gräßler, Iris, Marcel Ebel, and Jens Pottebaum. “Method for Systematic
Creation of Test Scenarios for Early Customer Involvement.” In Procedia CIRP,
136:213–18. Elsevier BV, 2025. https://doi.org/10.1016/j.procir.2025.08.038.
ieee: 'I. Gräßler, M. Ebel, and J. Pottebaum, “Method for systematic creation of
test scenarios for early customer involvement,” in Procedia CIRP, Patras,
Greece, 2025, vol. 136, pp. 213–218, doi: https://doi.org/10.1016/j.procir.2025.08.038.'
mla: Gräßler, Iris, et al. “Method for Systematic Creation of Test Scenarios for
Early Customer Involvement.” Procedia CIRP, vol. 136, Elsevier BV, 2025,
pp. 213–18, doi:https://doi.org/10.1016/j.procir.2025.08.038.
short: 'I. Gräßler, M. Ebel, J. Pottebaum, in: Procedia CIRP, Elsevier BV, 2025,
pp. 213–218.'
conference:
end_date: 2025-04-04
location: Patras, Greece
name: 35th CIRP Design Conference
start_date: 2025-04-02
date_created: 2025-09-01T07:17:50Z
date_updated: 2026-03-30T11:38:22Z
department:
- _id: '152'
doi: https://doi.org/10.1016/j.procir.2025.08.038
intvolume: ' 136'
keyword:
- Systems Engineering
- test scenario creation
- verification
- customer involvement
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://www.sciencedirect.com/science/article/pii/S2212827125007905
oa: '1'
page: 213-218
project:
- _id: '516'
name: 'CREXDATA: Kritische Maßnahmenplanung über extreme Datenmengen'
publication: Procedia CIRP
publication_identifier:
issn:
- 2212-8271
publication_status: published
publisher: Elsevier BV
quality_controlled: '1'
status: public
title: Method for systematic creation of test scenarios for early customer involvement
type: conference
user_id: '81788'
volume: 136
year: '2025'
...
---
_id: '62149'
abstract:
- lang: eng
text: The increasing complexity of technical systems requires early, structured
verification and validation (V&V). Existing metadata models only map parts of
the engineering process and do not enable a continuous chain of effects from requirements
to test results. The aim of this publication is to develop a holistic V&V metadata
model for the consistent, transparent and machine-processable description and
linking of relevant engineering artifacts. In a five-stage research approach,
essential model components are derived from literature and are integrated into
a holistic model. Initial applications as part of a European research project
show the potential of the model for a well-founded effect chain analysis and decision-supporting
V&V processes.
author:
- first_name: Iris
full_name: Gräßler, Iris
id: '47565'
last_name: Gräßler
orcid: 0000-0001-5765-971X
- first_name: Marcel
full_name: Ebel, Marcel
id: '81788'
last_name: Ebel
orcid: https://orcid.org/0009-0007-5400-4436
citation:
ama: 'Gräßler I, Ebel M. Ganzheitliches Metadatenmodel für die Verifikation und
Validierung in der Entwicklung komplexer technischer Systeme. In: DS 140: Proceedings
of the 36th Symposium Design for X (DFX2025). The Design Society; 2025. doi:10.35199/dfx2025.09'
apa: 'Gräßler, I., & Ebel, M. (2025). Ganzheitliches Metadatenmodel für die
Verifikation und Validierung in der Entwicklung komplexer technischer Systeme.
DS 140: Proceedings of the 36th Symposium Design for X (DFX2025). 36th
Design for X Symposium (DFX 2025), Hamburg. https://doi.org/10.35199/dfx2025.09'
bibtex: '@inproceedings{Gräßler_Ebel_2025, title={Ganzheitliches Metadatenmodel
für die Verifikation und Validierung in der Entwicklung komplexer technischer
Systeme}, DOI={10.35199/dfx2025.09},
booktitle={DS 140: Proceedings of the 36th Symposium Design for X (DFX2025)},
publisher={The Design Society}, author={Gräßler, Iris and Ebel, Marcel}, year={2025}
}'
chicago: 'Gräßler, Iris, and Marcel Ebel. “Ganzheitliches Metadatenmodel Für Die
Verifikation Und Validierung in Der Entwicklung Komplexer Technischer Systeme.”
In DS 140: Proceedings of the 36th Symposium Design for X (DFX2025). The
Design Society, 2025. https://doi.org/10.35199/dfx2025.09.'
ieee: 'I. Gräßler and M. Ebel, “Ganzheitliches Metadatenmodel für die Verifikation
und Validierung in der Entwicklung komplexer technischer Systeme,” presented at
the 36th Design for X Symposium (DFX 2025), Hamburg, 2025, doi: 10.35199/dfx2025.09.'
mla: 'Gräßler, Iris, and Marcel Ebel. “Ganzheitliches Metadatenmodel Für Die Verifikation
Und Validierung in Der Entwicklung Komplexer Technischer Systeme.” DS 140:
Proceedings of the 36th Symposium Design for X (DFX2025), The Design Society,
2025, doi:10.35199/dfx2025.09.'
short: 'I. Gräßler, M. Ebel, in: DS 140: Proceedings of the 36th Symposium Design
for X (DFX2025), The Design Society, 2025.'
conference:
end_date: 2025-09-12
location: Hamburg
name: 36th Design for X Symposium (DFX 2025)
start_date: 2025-09-11
date_created: 2025-11-10T08:37:55Z
date_updated: 2026-03-30T11:41:01Z
department:
- _id: '152'
doi: 10.35199/dfx2025.09
keyword:
- verification
- metadata model
- Systems Engineering
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
publication: 'DS 140: Proceedings of the 36th Symposium Design for X (DFX2025)'
publication_status: published
publisher: The Design Society
quality_controlled: '1'
status: public
title: Ganzheitliches Metadatenmodel für die Verifikation und Validierung in der Entwicklung
komplexer technischer Systeme
type: conference
user_id: '81788'
year: '2025'
...
---
_id: '57300'
abstract:
- lang: eng
text: Engineering methodologies for Cyber-Physical Systems (CPS) call for planning
simulations and physical testing in early phases of product creation. Even in
Model-Based Systems Engineering, there is a lack of systematic support that results
in avoidable costs and iterations in the engineering process. Planning test cases
and test scenarios along the product engineering process is not sufficiently integrated
in terms of support especially for verification and validation engineers. Based
on a systematic literature review, concepts for model-based planning of testing
are developed. Characteristics of test cases and test scenarios of CPS are systematically
identified. Generic templates for the creation of test cases and scenarios are
derived. Based on the templates, a System Modeling Language (SysML) profile extension
is developed which enables intuitive modelling of test cases and scenarios. The
SysML profile is evaluated in a sample System-of-Systems in Disaster Response.
It subsumes various types of sensor systems like rescue robotics, data science
algorithms and visualization technologies like Augmented Reality to support decisions
in extreme weather events. The templates and SysML profile significantly add value
for engineers in the early and systematic planning of verification and validation.
author:
- first_name: Iris
full_name: Gräßler, Iris
id: '47565'
last_name: Gräßler
orcid: 0000-0001-5765-971X
- first_name: Marcel
full_name: Ebel, Marcel
id: '81788'
last_name: Ebel
orcid: https://orcid.org/0009-0007-5400-4436
- first_name: Jens
full_name: Pottebaum, Jens
id: '405'
last_name: Pottebaum
orcid: http://orcid.org/0000-0001-8778-2989
citation:
ama: 'Gräßler I, Ebel M, Pottebaum J. Model-based planning of test cases and test
scenarios to support engineering of Cyber-Physical Systems. In: 2024 IEEE International
Symposium on Systems Engineering (ISSE). IEEE; 2024. doi:10.1109/isse63315.2024.10741135'
apa: Gräßler, I., Ebel, M., & Pottebaum, J. (2024). Model-based planning of
test cases and test scenarios to support engineering of Cyber-Physical Systems.
2024 IEEE International Symposium on Systems Engineering (ISSE). IEEE
International Symposium on Systems Engineering 2024, Perugia. https://doi.org/10.1109/isse63315.2024.10741135
bibtex: '@inproceedings{Gräßler_Ebel_Pottebaum_2024, title={Model-based planning
of test cases and test scenarios to support engineering of Cyber-Physical Systems},
DOI={10.1109/isse63315.2024.10741135},
booktitle={2024 IEEE International Symposium on Systems Engineering (ISSE)}, publisher={IEEE},
author={Gräßler, Iris and Ebel, Marcel and Pottebaum, Jens}, year={2024} }'
chicago: Gräßler, Iris, Marcel Ebel, and Jens Pottebaum. “Model-Based Planning of
Test Cases and Test Scenarios to Support Engineering of Cyber-Physical Systems.”
In 2024 IEEE International Symposium on Systems Engineering (ISSE). IEEE,
2024. https://doi.org/10.1109/isse63315.2024.10741135.
ieee: 'I. Gräßler, M. Ebel, and J. Pottebaum, “Model-based planning of test cases
and test scenarios to support engineering of Cyber-Physical Systems,” presented
at the IEEE International Symposium on Systems Engineering 2024, Perugia, 2024,
doi: 10.1109/isse63315.2024.10741135.'
mla: Gräßler, Iris, et al. “Model-Based Planning of Test Cases and Test Scenarios
to Support Engineering of Cyber-Physical Systems.” 2024 IEEE International
Symposium on Systems Engineering (ISSE), IEEE, 2024, doi:10.1109/isse63315.2024.10741135.
short: 'I. Gräßler, M. Ebel, J. Pottebaum, in: 2024 IEEE International Symposium
on Systems Engineering (ISSE), IEEE, 2024.'
conference:
end_date: 2024-10-18
location: Perugia
name: ' IEEE International Symposium on Systems Engineering 2024'
start_date: 2024-10-16
date_created: 2024-11-20T20:06:22Z
date_updated: 2025-01-17T16:20:14Z
department:
- _id: '152'
doi: 10.1109/isse63315.2024.10741135
has_accepted_license: '1'
keyword:
- Systems Engineering
- Systems verification
- System testing
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10741135&tag=1
oa: '1'
project:
- _id: '516'
grant_number: '101092749'
name: 'CREXDATA: CREXDATA: Kritische Maßnahmenplanung über extreme Datenmengen'
publication: 2024 IEEE International Symposium on Systems Engineering (ISSE)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Model-based planning of test cases and test scenarios to support engineering
of Cyber-Physical Systems
type: conference
user_id: '405'
year: '2024'
...
---
_id: '29769'
abstract:
- lang: eng
text: 'Wettstreit zwischen der Entwicklung neuer Hardwaretrojaner und entsprechender
Gegenmaßnahmen beschreiten Widersacher immer raffiniertere Wege um Schaltungsentwürfe
zu infizieren und dabei selbst fortgeschrittene Test- und Verifikationsmethoden
zu überlisten. Abgesehen von den konventionellen Methoden um einen Trojaner in
eine Schaltung für ein Field-programmable Gate Array (FPGA) einzuschleusen, können
auch die Entwurfswerkzeuge heimlich kompromittiert werden um einen Angreifer dabei
zu unterstützen einen erfolgreichen Angriff durchzuführen, der zum Beispiel Fehlfunktionen
oder ungewollte Informationsabflüsse bewirken kann. Diese Dissertation beschäftigt
sich hauptsächlich mit den beiden Blickwinkeln auf Hardwaretrojaner in rekonfigurierbaren
Systemen, einerseits der Perspektive des Verteidigers mit einer Methode zur Erkennung
von Trojanern auf der Bitstromebene, und andererseits derjenigen des Angreifers
mit einer neuartigen Angriffsmethode für FPGA Trojaner. Für die Verteidigung gegen
den Trojaner ``Heimtückische LUT'''' stellen wir die allererste erfolgreiche Gegenmaßnahme
vor, die durch Verifikation mittels Proof-carrying Hardware (PCH) auf der Bitstromebene
direkt vor der Konfiguration der Hardware angewendet werden kann, und präsentieren
ein vollständiges Schema für den Entwurf und die Verifikation von Schaltungen
für iCE40 FPGAs. Für die Gegenseite führen wir einen neuen Angriff ein, welcher
bösartiges Routing im eingefügten Trojaner ausnutzt um selbst im fertigen Bitstrom
in einem inaktiven Zustand zu verbleiben: Hierdurch kann dieser neuartige Angriff
zur Zeit weder von herkömmlichen Test- und Verifikationsmethoden, noch von unserer
vorher vorgestellten Verifikation auf der Bitstromebene entdeckt werden.'
- lang: eng
text: The battle of developing hardware Trojans and corresponding countermeasures
has taken adversaries towards ingenious ways of compromising hardware designs
by circumventing even advanced testing and verification methods. Besides conventional
methods of inserting Trojans into a design by a malicious entity, the design flow
for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised
to assist the attacker to perform a successful malfunctioning or information leakage
attack. This thesis mainly focuses on the two aspects of hardware Trojans in reconfigurable
systems, the defenders perspective which corresponds to the bitstream-level Trojan
detection technique, and the attackers perspective which corresponds to a novel
FPGA Trojan attack. From the defender's perspective, we introduce a first-ever
successful pre-configuration countermeasure against the ``Malicious LUT''-hardware
Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH) and present
the complete design-and-verification flow for iCE40 FPGAs. Likewise, from an attackers
perspective, we present a novel attack that leverages malicious routing of the
inserted Trojan circuit to acquire a dormant state even in the generated and transmitted
bitstream. Since the Trojan is injected in a post-synthesis step and remains unconnected
in the bitstream, the presented attack can currently neither be prevented by conventional
testing and verification methods nor by bitstream-level verification techniques.
author:
- first_name: Qazi Arbab
full_name: Ahmed, Qazi Arbab
id: '72764'
last_name: Ahmed
orcid: 0000-0002-1837-2254
citation:
ama: Ahmed QA. Hardware Trojans in Reconfigurable Computing. Paderborn University,
Paderborn, Germany; 2022. doi:10.17619/UNIPB/1-1271
apa: Ahmed, Q. A. (2022). Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany. https://doi.org/10.17619/UNIPB/1-1271
bibtex: '@book{Ahmed_2022, place={Paderborn}, title={Hardware Trojans in Reconfigurable
Computing}, DOI={10.17619/UNIPB/1-1271},
publisher={ Paderborn University, Paderborn, Germany}, author={Ahmed, Qazi Arbab},
year={2022} }'
chicago: 'Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing.
Paderborn: Paderborn University, Paderborn, Germany, 2022. https://doi.org/10.17619/UNIPB/1-1271.'
ieee: 'Q. A. Ahmed, Hardware Trojans in Reconfigurable Computing. Paderborn: Paderborn
University, Paderborn, Germany, 2022.'
mla: Ahmed, Qazi Arbab. Hardware Trojans in Reconfigurable Computing. Paderborn
University, Paderborn, Germany, 2022, doi:10.17619/UNIPB/1-1271.
short: Q.A. Ahmed, Hardware Trojans in Reconfigurable Computing, Paderborn University,
Paderborn, Germany, Paderborn, 2022.
date_created: 2022-02-07T14:02:36Z
date_updated: 2022-11-30T13:39:01Z
ddc:
- '004'
department:
- _id: '78'
doi: 10.17619/UNIPB/1-1271
has_accepted_license: '1'
keyword:
- FPGA Security
- Hardware Trojans
- Bitstream-level Trojans
- Bitstream Verification
language:
- iso: eng
main_file_link:
- open_access: '1'
url: "\turn:nbn:de:hbz:466:2-40303"
oa: '1'
place: Paderborn
project:
- _id: '1'
name: 'SFB 901: SFB 901'
- _id: '4'
name: 'SFB 901 - C: SFB 901 - Project Area C'
- _id: '14'
name: 'SFB 901 - C2: SFB 901 - Subproject C2'
publication_status: published
publisher: ' Paderborn University, Paderborn, Germany'
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Hardware Trojans in Reconfigurable Computing
type: dissertation
user_id: '477'
year: '2022'
...
---
_id: '26746'
abstract:
- lang: eng
text: "Previous research in proof-carrying hardware has established the feasibility
and utility of the approach, and provided a concrete solution for employing it
for the certification of functional equivalence checking against a specification,
but fell short in connecting it to state-of-the-art formal verification insights,
methods and tools. Due to the immense complexity of modern circuits, and verification
challenges such as the state explosion problem for sequential circuits, this restriction
of readily-available verification solutions severely limited the applicability
of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the
PCH approach and current advances in formal hardware verification, provides methods
and tools to express and certify a wide range of circuit properties, both functional
and non-functional, and presents for the first time prototypes in which circuits
that are implemented on actual reconfigurable hardware are verified with PCH methods.
Using these results, designers can now apply PCH to establish trust in more complex
circuits, by using more diverse properties which they can express using modern,
efficient property specification techniques."
- lang: ger
text: "Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit
und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen
Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen,
Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund
der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der
Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung
sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem
größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen
PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden
und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite
von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale.
Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels
PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert
sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen
in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt
von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt
werden können."
author:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University; 2021.
apa: Wiersema, T. (2021). Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn University.
bibtex: '@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties
of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn
University}, author={Wiersema, Tobias}, year={2021} }'
chicago: 'Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware
Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
ieee: 'T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.'
mla: Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware. Paderborn University, 2021.
short: T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits
with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021.
date_created: 2021-10-25T06:35:41Z
date_updated: 2022-01-06T06:57:26Z
ddc:
- '006'
department:
- _id: '78'
keyword:
- Proof-Carrying Hardware
- Formal Verification
- Sequential Circuits
- Non-Functional Properties
- Functional Properties
language:
- iso: eng
main_file_link:
- open_access: '1'
url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800
oa: '1'
page: '293'
place: Paderborn
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication_status: published
publisher: Paderborn University
status: public
supervisor:
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying
Hardware
type: dissertation
user_id: '3118'
year: '2021'
...
---
_id: '27841'
abstract:
- lang: eng
text: Verification of software and processor hardware usually proceeds separately,
software analysis relying on the correctness of processors executing machine instructions.
This assumption is valid as long as the software runs on standard CPUs that have
been extensively validated and are in wide use. However, for processors exploiting
custom instruction set extensions to meet performance and energy constraints the
validation might be less extensive, challenging the correctness assumption. In
this paper we present a novel formal approach for hardware/software co-verification
targeting processors with custom instruction set extensions. We detail two different
approaches for checking whether the hardware fulfills the requirements expected
by the software analysis. The approaches are designed to explore a trade-off between
generality of the verification and computational effort. Then, we describe the
integration of software and hardware analyses for both techniques and describe
a fully automated tool chain implementing the approaches. Finally, we demonstrate
and compare the two approaches on example source code with custom instructions,
using state-of-the-art software analysis and hardware verification techniques.
author:
- first_name: Marie-Christine
full_name: Jakobs, Marie-Christine
last_name: Jakobs
- first_name: Felix
full_name: Pauck, Felix
id: '22398'
last_name: Pauck
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Heike
full_name: Wehrheim, Heike
id: '573'
last_name: Wehrheim
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
citation:
ama: Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware
Co-Verification for Custom Instruction Set Processors. IEEE Access. Published
online 2021. doi:10.1109/ACCESS.2021.3131213
apa: Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., & Wiersema, T. (2021).
Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE
Access. https://doi.org/10.1109/ACCESS.2021.3131213
bibtex: '@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware
Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213},
journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck,
Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021}
}'
chicago: Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and
Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set
Processors.” IEEE Access, 2021. https://doi.org/10.1109/ACCESS.2021.3131213.
ieee: 'M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware
Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021,
doi: 10.1109/ACCESS.2021.3131213.'
mla: Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom
Instruction Set Processors.” IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213.
short: M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access
(2021).
date_created: 2021-11-25T14:12:22Z
date_updated: 2023-01-18T08:34:50Z
department:
- _id: '78'
doi: 10.1109/ACCESS.2021.3131213
funded_apc: '1'
keyword:
- Software Analysis
- Abstract Interpretation
- Custom Instruction
- Hardware Verification
language:
- iso: eng
project:
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '12'
name: SFB 901 - Subproject B4
publication: IEEE Access
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Software/Hardware Co-Verification for Custom Instruction Set Processors
type: journal_article
user_id: '22398'
year: '2021'
...
---
_id: '17358'
abstract:
- lang: eng
text: 'Approximate circuits trade-off computational accuracy against improvements
in hardware area, delay, or energy consumption. IP core vendors who wish to create
such circuits need to convince consumers of the resulting approximation quality.
As a solution we propose proof-carrying approximate circuits: The vendor creates
an approximate IP core together with a certificate that proves the approximation
quality. The proof certificate is bundled with the approximate IP core and sent
off to the consumer. The consumer can formally verify the approximation quality
of the IP core at a fraction of the typical computational cost for formal verification.
In this paper, we first make the case for proof-carrying approximate circuits
and then demonstrate the feasibility of the approach by a set of synthesis experiments
using an exemplary approximation framework.'
article_type: original
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE
Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088.
doi:10.1109/TVLSI.2020.3008061
apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate
Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9),
2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061
bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate
Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061},
number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems},
publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner,
Marco}, year={2020}, pages={2084–2088} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying
Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems
28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.'
ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate
Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol.
28, no. 9, pp. 2084–2088, 2020.
mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE
Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE,
2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061.
short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large
Scale Integration Systems 28 (2020) 2084–2088.
date_created: 2020-07-06T11:21:30Z
date_updated: 2022-01-06T06:53:09Z
department:
- _id: '78'
doi: 10.1109/TVLSI.2020.3008061
funded_apc: '1'
intvolume: ' 28'
issue: '9'
keyword:
- Approximate circuit synthesis
- approximate computing
- error metrics
- formal verification
- proof-carrying hardware
language:
- iso: eng
page: 2084 - 2088
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '3'
name: SFB 901 - Project Area B
- _id: '1'
name: SFB 901
publication: IEEE Transactions On Very Large Scale Integration Systems
publication_identifier:
eissn:
- 1557-9999
issn:
- 1063-8210
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Proof-carrying Approximate Circuits
type: journal_article
user_id: '49051'
volume: 28
year: '2020'
...
---
_id: '16853'
abstract:
- lang: eng
text: State-of-the-art frameworks for generating approximate circuits usually rely
on information gained through circuit synthesis and/or verification to explore
the search space and to find an optimal solution. Throughout the process, a large
number of circuits may be subject to processing, leading to considerable runtimes.
In this work, we propose a search which takes error bounds and pre-computed impact
factors into account to reduce the number of invoked synthesis and verification
processes. In our experimental results, we achieved speed-ups of up to 76x while
area savings remain comparable to the reference search method, simulated annealing.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop
on Approximate Computing (AxC 2019).'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
Fourth Workshop on Approximate Computing (AxC 2019).'
bibtex: '@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop
on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh
Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth
Workshop on Approximate Computing (AxC 2019). .'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).'
short: L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth
Workshop on Approximate Computing (AxC 2019) (n.d.).
date_created: 2020-04-25T08:02:07Z
date_updated: 2022-01-06T06:52:57Z
ddc:
- '006'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-04-25T08:00:35Z
date_updated: 2020-04-25T08:00:35Z
file_id: '16854'
file_name: AxC19_paper_3.pdf
file_size: 152806
relation: main_file
success: 1
file_date_updated: 2020-04-25T08:00:35Z
has_accepted_license: '1'
keyword:
- Approximate computing
- parameter selection
- search space exploration
- verification
- circuit synthesis
language:
- iso: eng
page: '2'
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Fourth Workshop on Approximate Computing (AxC 2019)
publication_status: accepted
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: preprint
user_id: '49051'
year: '2019'
...
---
_id: '1097'
author:
- first_name: Felix Paul
full_name: Jentzsch, Felix Paul
last_name: Jentzsch
citation:
ama: Jentzsch FP. Enforcing IP Core Connection Properties with Verifiable Security
Monitors. Universität Paderborn; 2018.
apa: Jentzsch, F. P. (2018). Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn.
bibtex: '@book{Jentzsch_2018, title={Enforcing IP Core Connection Properties with
Verifiable Security Monitors}, publisher={Universität Paderborn}, author={Jentzsch,
Felix Paul}, year={2018} }'
chicago: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
ieee: F. P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
mla: Jentzsch, Felix Paul. Enforcing IP Core Connection Properties with Verifiable
Security Monitors. Universität Paderborn, 2018.
short: F.P. Jentzsch, Enforcing IP Core Connection Properties with Verifiable Security
Monitors, Universität Paderborn, 2018.
date_created: 2018-01-15T16:48:05Z
date_updated: 2022-01-06T06:50:54Z
department:
- _id: '78'
keyword:
- Approximate Computing
- Proof-Carrying Hardware
- Formal Verification
language:
- iso: eng
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
title: Enforcing IP Core Connection Properties with Verifiable Security Monitors
type: bachelorsthesis
user_id: '477'
year: '2018'
...
---
_id: '36917'
abstract:
- lang: eng
text: The ever-increasing complexity of heterogeneous electronic systems demand
for intensified abstraction and automation efforts to improve design, verification
and validation productivity, especially in earlier phases of system engineering.
Within the verification activity various metrics can be applied to determine functional
correctness or the overall progress. Here, a supporting verification methodology
defining high-level verification planning down to the actual metric code development
is essential. Moreover, an advanced assistance for the designer, such as a tooling
infrastructure to automatize and accelerate the metric code implementation, is
needed to minimize the influence of errorprone manual coding. In this article
we present a single-source verification metric code-generation methodology for
improved coverage automation. We determine (i) a suitable metric model for model-based
capture of verification metrics as well as (ii) an assisted model-based processing
and generation flow of the verification environment and metric skeletons. We apply
our method to a SystemC case-study, in doing so, targeting metric code implementation
productivity and consistency enhancement.
author:
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Gilles Bertrand
full_name: Defo, Gilles Bertrand
last_name: Defo
citation:
ama: 'Kuznik C, Müller W, Defo GB. An Assisted Single Source Verification Metric
Model Code Generation Methodology. In: ; 2014.'
apa: Kuznik, C., Müller, W., & Defo, G. B. (2014). An Assisted Single Source
Verification Metric Model Code Generation Methodology. Proceedings of the
Electronic System Level Synthesis Conference (ESLSyn).
bibtex: '@inproceedings{Kuznik_Müller_Defo_2014, place={San Francisco, USA}, title={An
Assisted Single Source Verification Metric Model Code Generation Methodology},
author={Kuznik, Christoph and Müller, Wolfgang and Defo, Gilles Bertrand}, year={2014}
}'
chicago: Kuznik, Christoph, Wolfgang Müller, and Gilles Bertrand Defo. “An Assisted
Single Source Verification Metric Model Code Generation Methodology.” San Francisco,
USA, 2014.
ieee: C. Kuznik, W. Müller, and G. B. Defo, “An Assisted Single Source Verification
Metric Model Code Generation Methodology,” presented at the Proceedings of the
Electronic System Level Synthesis Conference (ESLSyn), 2014.
mla: Kuznik, Christoph, et al. An Assisted Single Source Verification Metric
Model Code Generation Methodology. 2014.
short: 'C. Kuznik, W. Müller, G.B. Defo, in: San Francisco, USA, 2014.'
conference:
name: Proceedings of the Electronic System Level Synthesis Conference (ESLSyn)
date_created: 2023-01-16T11:43:50Z
date_updated: 2023-01-16T11:44:06Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: San Francisco, USA
status: public
title: An Assisted Single Source Verification Metric Model Code Generation Methodology
type: conference
user_id: '5786'
year: '2014'
...
---
_id: '34585'
abstract:
- lang: eng
text: In this paper, we present an efficient approach to virtual platform modeling
for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666
Standard SystemC simulation. For evaluation we consider Infineon's recently introduced
AURIX processor family as a target platform, which utilizes multiple CPU cores
operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals.
For SoC prototyping, we integrate the fast and open instruction accurate QEMU
software emulator with the TLMu library for SystemC co-verification. This article
reports our most recent efforts of the implementation of the TriCore instruction
set for QEMU. The experimental results demonstrate the functional correctness
and performance of our TriCore implementation.
author:
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Bernd
full_name: Messidat, Bernd
last_name: Messidat
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Koppelmann B, Messidat B, Becker M, Müller W, Scheytt JC. Fast and Open Virtual
Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of the Design
and Verification Conference Europe (DVCON Europe). ; 2014.'
apa: Koppelmann, B., Messidat, B., Becker, M., Müller, W., & Scheytt, J. C.
(2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU. Proceedings
of the Design and Verification Conference Europe (DVCON Europe).
bibtex: '@inproceedings{Koppelmann_Messidat_Becker_Müller_Scheytt_2014, place={München},
title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings
of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann,
Bastian and Messidat, Bernd and Becker, Markus and Müller, Wolfgang and Scheytt,
J. Christoph}, year={2014} }'
chicago: Koppelmann, Bastian, Bernd Messidat, Markus Becker, Wolfgang Müller, and
J. Christoph Scheytt. “Fast and Open Virtual Platforms for TriCore-Based SoCs
Using QEMU.” In Proceedings of the Design and Verification Conference Europe
(DVCON Europe). München, 2014.
ieee: B. Koppelmann, B. Messidat, M. Becker, W. Müller, and J. C. Scheytt, “Fast
and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.
mla: Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based
SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe
(DVCON Europe), 2014.
short: 'B. Koppelmann, B. Messidat, M. Becker, W. Müller, J.C. Scheytt, in: Proceedings
of the Design and Verification Conference Europe (DVCON Europe), München, 2014.'
date_created: 2022-12-20T10:48:25Z
date_updated: 2023-02-01T08:12:02Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: München
publication: Proceedings of the Design and Verification Conference Europe (DVCON Europe)
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: conference
user_id: '15931'
year: '2014'
...
---
_id: '34583'
abstract:
- lang: eng
text: In this paper, we present an efficient approach to virtual platform modeling
for TriCore-based SoCs by combining fast and open software emulation with IEEE-1666
Standard SystemC simulation. For evaluation we consider Infineon's recently introduced
AURIX processor family as a target platform, which utilizes multiple CPU cores
operating in lockstep mode, memories, hierarchical buses, and a rich set of peripherals.
For SoC prototyping, we integrate the fast and open instruction accurate QEMU
software emulator with the TLMu library for SystemC co-verification. This article
reports our most recent efforts of the implementation of the TriCore instruction
set for QEMU. The experimental results demonstrate the functional correctness
and performance of our TriCore implementation.
author:
- first_name: Bastian
full_name: Koppelmann, Bastian
id: '25260'
last_name: Koppelmann
- first_name: Bernd
full_name: Messidat, Bernd
last_name: Messidat
- first_name: Christoph
full_name: Kuznik, Christoph
last_name: Kuznik
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Koppelmann B, Messidat B, Kuznik C, Müller W, Becker M, Scheytt JC. Fast and
Open Virtual Platforms for TriCore-based SoCs Using QEMU. In: Proceedings of
the Design and Verification Conference Europe (DVCON Europe). ; 2014.'
apa: Koppelmann, B., Messidat, B., Kuznik, C., Müller, W., Becker, M., & Scheytt,
J. C. (2014). Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU.
Proceedings of the Design and Verification Conference Europe (DVCON Europe).
bibtex: '@inproceedings{Koppelmann_Messidat_Kuznik_Müller_Becker_Scheytt_2014, place={München},
title={Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU}, booktitle={Proceedings
of the Design and Verification Conference Europe (DVCON Europe)}, author={Koppelmann,
Bastian and Messidat, Bernd and Kuznik, Christoph and Müller, Wolfgang and Becker,
Markus and Scheytt, J. Christoph}, year={2014} }'
chicago: Koppelmann, Bastian, Bernd Messidat, Christoph Kuznik, Wolfgang Müller,
Markus Becker, and J. Christoph Scheytt. “Fast and Open Virtual Platforms for
TriCore-Based SoCs Using QEMU.” In Proceedings of the Design and Verification
Conference Europe (DVCON Europe). München, 2014.
ieee: B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, and J. C. Scheytt,
“Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU,” 2014.
mla: Koppelmann, Bastian, et al. “Fast and Open Virtual Platforms for TriCore-Based
SoCs Using QEMU.” Proceedings of the Design and Verification Conference Europe
(DVCON Europe), 2014.
short: 'B. Koppelmann, B. Messidat, C. Kuznik, W. Müller, M. Becker, J.C. Scheytt,
in: Proceedings of the Design and Verification Conference Europe (DVCON Europe),
München, 2014.'
date_created: 2022-12-20T10:45:38Z
date_updated: 2025-02-26T14:42:18Z
department:
- _id: '58'
keyword:
- System Design
- Verification
language:
- iso: eng
place: München
publication: Proceedings of the Design and Verification Conference Europe (DVCON Europe)
status: public
title: Fast and Open Virtual Platforms for TriCore-based SoCs Using QEMU
type: conference
user_id: '16243'
year: '2014'
...
---
_id: '2370'
author:
- first_name: Matthias
full_name: Woehrle, Matthias
last_name: Woehrle
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Roman
full_name: Lim, Roman
last_name: Lim
- first_name: Jan
full_name: Beutel, Jan
last_name: Beutel
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Woehrle M, Plessl C, Lim R, Beutel J, Thiele L. EvAnT: Analysis and Checking
of event traces for Wireless Sensor Networks. In: IEEE Int. Conf. on Sensor
Networks, Ubiquitous, and Trustworthy Computing (SUTC). IEEE Computer Society;
2008:201-208. doi:10.1109/SUTC.2008.24'
apa: 'Woehrle, M., Plessl, C., Lim, R., Beutel, J., & Thiele, L. (2008). EvAnT:
Analysis and Checking of event traces for Wireless Sensor Networks. IEEE Int.
Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), 201–208.
https://doi.org/10.1109/SUTC.2008.24'
bibtex: '@inproceedings{Woehrle_Plessl_Lim_Beutel_Thiele_2008, place={Los Alamitos,
CA, USA}, title={EvAnT: Analysis and Checking of event traces for Wireless Sensor
Networks}, DOI={10.1109/SUTC.2008.24},
booktitle={IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing
(SUTC)}, publisher={IEEE Computer Society}, author={Woehrle, Matthias and Plessl,
Christian and Lim, Roman and Beutel, Jan and Thiele, Lothar}, year={2008}, pages={201–208}
}'
chicago: 'Woehrle, Matthias, Christian Plessl, Roman Lim, Jan Beutel, and Lothar
Thiele. “EvAnT: Analysis and Checking of Event Traces for Wireless Sensor Networks.”
In IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing
(SUTC), 201–8. Los Alamitos, CA, USA: IEEE Computer Society, 2008. https://doi.org/10.1109/SUTC.2008.24.'
ieee: 'M. Woehrle, C. Plessl, R. Lim, J. Beutel, and L. Thiele, “EvAnT: Analysis
and Checking of event traces for Wireless Sensor Networks,” in IEEE Int. Conf.
on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), 2008, pp.
201–208, doi: 10.1109/SUTC.2008.24.'
mla: 'Woehrle, Matthias, et al. “EvAnT: Analysis and Checking of Event Traces for
Wireless Sensor Networks.” IEEE Int. Conf. on Sensor Networks, Ubiquitous,
and Trustworthy Computing (SUTC), IEEE Computer Society, 2008, pp. 201–08,
doi:10.1109/SUTC.2008.24.'
short: 'M. Woehrle, C. Plessl, R. Lim, J. Beutel, L. Thiele, in: IEEE Int. Conf.
on Sensor Networks, Ubiquitous, and Trustworthy Computing (SUTC), IEEE Computer
Society, Los Alamitos, CA, USA, 2008, pp. 201–208.'
date_created: 2018-04-17T12:03:20Z
date_updated: 2023-09-26T13:55:02Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/SUTC.2008.24
keyword:
- WSN
- testing
- verification
language:
- iso: eng
page: 201-208
place: Los Alamitos, CA, USA
publication: IEEE Int. Conf. on Sensor Networks, Ubiquitous, and Trustworthy Computing
(SUTC)
publication_identifier:
isbn:
- 978-0-7695-3158-8
publisher: IEEE Computer Society
quality_controlled: '1'
status: public
title: 'EvAnT: Analysis and Checking of event traces for Wireless Sensor Networks'
type: conference
user_id: '15278'
year: '2008'
...
---
_id: '2393'
author:
- first_name: Jan
full_name: Beutel, Jan
last_name: Beutel
- first_name: Matthias
full_name: Dyer, Matthias
last_name: Dyer
- first_name: Roman
full_name: Lim, Roman
last_name: Lim
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Matthias
full_name: Woehrle, Matthias
last_name: Woehrle
- first_name: Mustafa
full_name: Yuecel, Mustafa
last_name: Yuecel
- first_name: Lothar
full_name: Thiele, Lothar
last_name: Thiele
citation:
ama: 'Beutel J, Dyer M, Lim R, et al. Automated Wireless Sensor Network Testing.
In: Proc. Int. Conf. Networked Sensing Systems (INSS). IEEE; 2007:303-303.
doi:10.1109/INSS.2007.4297445'
apa: Beutel, J., Dyer, M., Lim, R., Plessl, C., Woehrle, M., Yuecel, M., & Thiele,
L. (2007). Automated Wireless Sensor Network Testing. Proc. Int. Conf. Networked
Sensing Systems (INSS), 303–303. https://doi.org/10.1109/INSS.2007.4297445
bibtex: '@inproceedings{Beutel_Dyer_Lim_Plessl_Woehrle_Yuecel_Thiele_2007, place={Piscataway,
NJ, USA}, title={Automated Wireless Sensor Network Testing}, DOI={10.1109/INSS.2007.4297445},
booktitle={Proc. Int. Conf. Networked Sensing Systems (INSS)}, publisher={IEEE},
author={Beutel, Jan and Dyer, Matthias and Lim, Roman and Plessl, Christian and
Woehrle, Matthias and Yuecel, Mustafa and Thiele, Lothar}, year={2007}, pages={303–303}
}'
chicago: 'Beutel, Jan, Matthias Dyer, Roman Lim, Christian Plessl, Matthias Woehrle,
Mustafa Yuecel, and Lothar Thiele. “Automated Wireless Sensor Network Testing.”
In Proc. Int. Conf. Networked Sensing Systems (INSS), 303–303. Piscataway,
NJ, USA: IEEE, 2007. https://doi.org/10.1109/INSS.2007.4297445.'
ieee: 'J. Beutel et al., “Automated Wireless Sensor Network Testing,” in
Proc. Int. Conf. Networked Sensing Systems (INSS), 2007, pp. 303–303, doi:
10.1109/INSS.2007.4297445.'
mla: Beutel, Jan, et al. “Automated Wireless Sensor Network Testing.” Proc. Int.
Conf. Networked Sensing Systems (INSS), IEEE, 2007, pp. 303–303, doi:10.1109/INSS.2007.4297445.
short: 'J. Beutel, M. Dyer, R. Lim, C. Plessl, M. Woehrle, M. Yuecel, L. Thiele,
in: Proc. Int. Conf. Networked Sensing Systems (INSS), IEEE, Piscataway, NJ, USA,
2007, pp. 303–303.'
date_created: 2018-04-17T13:35:55Z
date_updated: 2023-09-26T14:00:58Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/INSS.2007.4297445
keyword:
- WSN
- testing
- verification
language:
- iso: eng
page: 303-303
place: Piscataway, NJ, USA
publication: Proc. Int. Conf. Networked Sensing Systems (INSS)
publication_identifier:
isbn:
- 1-4244-1231-5
publisher: IEEE
quality_controlled: '1'
status: public
title: Automated Wireless Sensor Network Testing
type: conference
user_id: '15278'
year: '2007'
...
---
_id: '39069'
abstract:
- lang: eng
text: We present the syntax and semantics of a past- and future-oriented temporal
extension of the Object Constraint Language (OCL). Our extension supports designers
to express time-bounded properties over a state-oriented UML model of a system
under development. The semantics is formally defined over the system states of
a mathematical object model. Additionally, we present a mapping to Clocked Linear
Temporal Logic (Clocked LTL) formulae, which is the basis for further application
in verification with model checking. We demonstrate the applicability of the approach
by the example of a buffer specification in the context of a production system.
author:
- first_name: Stephan
full_name: Flake, Stephan
last_name: Flake
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Flake S, Müller W. Past- and Future-Oriented Time-Bound Temporal Properties
with OCL. In: Proceedings of SEFM´04. IEEE; 2004. doi:10.1109/SEFM.2004.1347516'
apa: Flake, S., & Müller, W. (2004). Past- and Future-Oriented Time-Bound Temporal
Properties with OCL. Proceedings of SEFM´04. Proceedings of the Second
International Conference on Software Engineering and Formal Methods. https://doi.org/10.1109/SEFM.2004.1347516
bibtex: '@inproceedings{Flake_Müller_2004, place={Beijing, China}, title={Past-
and Future-Oriented Time-Bound Temporal Properties with OCL}, DOI={10.1109/SEFM.2004.1347516},
booktitle={Proceedings of SEFM´04}, publisher={IEEE}, author={Flake, Stephan and
Müller, Wolfgang}, year={2004} }'
chicago: 'Flake, Stephan, and Wolfgang Müller. “Past- and Future-Oriented Time-Bound
Temporal Properties with OCL.” In Proceedings of SEFM´04. Beijing, China:
IEEE, 2004. https://doi.org/10.1109/SEFM.2004.1347516.'
ieee: 'S. Flake and W. Müller, “Past- and Future-Oriented Time-Bound Temporal Properties
with OCL,” presented at the Proceedings of the Second International Conference
on Software Engineering and Formal Methods, 2004, doi: 10.1109/SEFM.2004.1347516.'
mla: Flake, Stephan, and Wolfgang Müller. “Past- and Future-Oriented Time-Bound
Temporal Properties with OCL.” Proceedings of SEFM´04, IEEE, 2004, doi:10.1109/SEFM.2004.1347516.
short: 'S. Flake, W. Müller, in: Proceedings of SEFM´04, IEEE, Beijing, China, 2004.'
conference:
name: ' Proceedings of the Second International Conference on Software Engineering
and Formal Methods'
date_created: 2023-01-24T09:03:36Z
date_updated: 2023-01-24T09:03:41Z
department:
- _id: '672'
doi: 10.1109/SEFM.2004.1347516
keyword:
- Unified modeling language
- Logic
- Clocks
- Boolean functions
- Application software
- Time factors
- Real time systems
- Formal verification
- Buffer storage
- Software packages
language:
- iso: eng
place: Beijing, China
publication: Proceedings of SEFM´04
publication_identifier:
isbn:
- 0-7695-2222-X
publisher: IEEE
status: public
title: Past- and Future-Oriented Time-Bound Temporal Properties with OCL
type: conference
user_id: '5786'
year: '2004'
...
---
_id: '39382'
abstract:
- lang: eng
text: We present a rigorous but transparent semantics definition of the SpecC language
that covers the execution of SpecC behaviors and their interaction with the kernel
process. The semantics include wait, wait for, par, and try statements as they
are introduced in SpecC. We present our definition in form of distributed abstract
state machine (ASM) rules strictly following the lines of the SpecC Language Reference
Manual. We mainly see our formal semantics in three application areas. First,
it is a concise, unambiguous description for documentation and standardization.
Second, it applies as a high-level, pseudo code-oriented specification for the
implementation of a SpecC simulator. Finally, it is a first step for SpecC synthesis
in order to identify similar concepts with other languages like VHDL and SystemC
for the definition of common patterns and language subsets.
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Rainer
full_name: Dömer, Rainer
last_name: Dömer
- first_name: Andreas
full_name: Gerstlauer, Andreas
last_name: Gerstlauer
citation:
ama: 'Müller W, Dömer R, Gerstlauer A. The Formal Execution Semantics of SpecC.
In: Proceedings of the ISSS02. ; 2002. doi:10.1145/581199.581234 '
apa: Müller, W., Dömer, R., & Gerstlauer, A. (2002). The Formal Execution Semantics
of SpecC. Proceedings of the ISSS02. https://doi.org/10.1145/581199.581234
bibtex: '@inproceedings{Müller_Dömer_Gerstlauer_2002, place={Nagoya, Japan}, title={The
Formal Execution Semantics of SpecC}, DOI={10.1145/581199.581234 }, booktitle={Proceedings of the ISSS02}, author={Müller,
Wolfgang and Dömer, Rainer and Gerstlauer, Andreas}, year={2002} }'
chicago: Müller, Wolfgang, Rainer Dömer, and Andreas Gerstlauer. “The Formal Execution
Semantics of SpecC.” In Proceedings of the ISSS02. Nagoya, Japan, 2002.
https://doi.org/10.1145/581199.581234
.
ieee: 'W. Müller, R. Dömer, and A. Gerstlauer, “The Formal Execution Semantics of
SpecC,” 2002, doi: 10.1145/581199.581234
.'
mla: Müller, Wolfgang, et al. “The Formal Execution Semantics of SpecC.” Proceedings
of the ISSS02, 2002, doi:10.1145/581199.581234
.
short: 'W. Müller, R. Dömer, A. Gerstlauer, in: Proceedings of the ISSS02, Nagoya,
Japan, 2002.'
date_created: 2023-01-24T10:10:24Z
date_updated: 2023-01-24T10:10:28Z
department:
- _id: '672'
doi: '10.1145/581199.581234 '
keyword:
- Standardization
- Kernel
- Permission
- Formal verification
- Logic functions
- Documentation
- Reasoning about programs
- Specification languages
- Formal specifications
- Software systems
language:
- iso: eng
place: Nagoya, Japan
publication: Proceedings of the ISSS02
publication_identifier:
isbn:
- 1-58113-576-9
status: public
title: The Formal Execution Semantics of SpecC
type: conference
user_id: '5786'
year: '2002'
...
---
_id: '39403'
abstract:
- lang: eng
text: The Unified Modeling Language (UML) has received wide acceptance as a standard
language in the field of software specification by means of different diagram
types. In a recent version of UML, the textual Object Constraint Language (OCL)
was introduced to support specification of constraints for UML models. But OCL
currently does not provide sufficient means to specify constraints over the dynamic
behavior of a model. This article presents an OCL extension that is consistent
with current OCL and enables modelers to specify state-related time-bounded constraints.
We consider the case study of a flexible manufacturing system and identify typical
real-time constraints. The constraints are presented in our temporal OCL extension
as well as in temporal logic formulae. For general application, we define a semantics
of our OCL extension by means of a time-bounded temporal logic based on Computational
Tree Logic (CTL).
author:
- first_name: Stephan
full_name: Flake, Stephan
last_name: Flake
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
citation:
ama: 'Flake S, Müller W. Specification of Real-Time Properties for UML Models. In:
Proceedings of HICSS-35. ; 2002. doi:10.1109/HICSS.2002.994469'
apa: Flake, S., & Müller, W. (2002). Specification of Real-Time Properties for
UML Models. Proceedings of HICSS-35. Proceedings of the 35th Annual Hawaii
International Conference on System Sciences, Big Island, HI, USA . https://doi.org/10.1109/HICSS.2002.994469
bibtex: '@inproceedings{Flake_Müller_2002, place={Big Island, HI, USA }, title={Specification
of Real-Time Properties for UML Models}, DOI={10.1109/HICSS.2002.994469},
booktitle={Proceedings of HICSS-35}, author={Flake, Stephan and Müller, Wolfgang},
year={2002} }'
chicago: Flake, Stephan, and Wolfgang Müller. “Specification of Real-Time Properties
for UML Models.” In Proceedings of HICSS-35. Big Island, HI, USA , 2002.
https://doi.org/10.1109/HICSS.2002.994469.
ieee: 'S. Flake and W. Müller, “Specification of Real-Time Properties for UML Models,”
presented at the Proceedings of the 35th Annual Hawaii International Conference
on System Sciences, Big Island, HI, USA , 2002, doi: 10.1109/HICSS.2002.994469.'
mla: Flake, Stephan, and Wolfgang Müller. “Specification of Real-Time Properties
for UML Models.” Proceedings of HICSS-35, 2002, doi:10.1109/HICSS.2002.994469.
short: 'S. Flake, W. Müller, in: Proceedings of HICSS-35, Big Island, HI, USA ,
2002.'
conference:
location: 'Big Island, HI, USA '
name: Proceedings of the 35th Annual Hawaii International Conference on System Sciences
date_created: 2023-01-24T10:22:12Z
date_updated: 2023-01-24T10:22:16Z
department:
- _id: '672'
doi: 10.1109/HICSS.2002.994469
keyword:
- Unified modeling language
- Logic
- Formal verification
- Real time systems
- Programming profession
- Vehicle dynamics
- Software standards
- Flexible manufacturing systems
- Electronics industry
- Protocols
language:
- iso: eng
place: 'Big Island, HI, USA '
publication: Proceedings of HICSS-35
publication_identifier:
isbn:
- 0-7695-1435-9
status: public
title: Specification of Real-Time Properties for UML Models
type: conference
user_id: '5786'
year: '2002'
...
---
_id: '39421'
abstract:
- lang: eng
text: We present a rigorous but transparent semantics definition of SystemC that
covers method, thread, and clocked thread behavior as well as their interaction
with the simulation kernel process. The semantics includes watching statements,
signal assignment, and wait statements as they are introduced in SystemC V1.O.
We present our definition in form of distributed Abstract State Machines (ASMs)
rules reflecting the view given in the SystemC User's Manual and the reference
implementation. We mainly see our formal semantics as a concise, unambiguous,
high-level specification for SystemC-based implementations and for standardization.
Additionally, it can be used as a sound basis to investigate SystemC interoperability
with Verilog and VHDL.
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Jürgen
full_name: Ruf, Jürgen
last_name: Ruf
- first_name: D. W.
full_name: Hoffmann, D. W.
last_name: Hoffmann
- first_name: Joachim
full_name: Gerlach, Joachim
last_name: Gerlach
- first_name: Thomas
full_name: Kropf, Thomas
last_name: Kropf
- first_name: W.
full_name: Rosenstiehl, W.
last_name: Rosenstiehl
citation:
ama: 'Müller W, Ruf J, Hoffmann DW, Gerlach J, Kropf T, Rosenstiehl W. The Simulation
Semantics of SystemC. In: Proceedings of the Design, Automation, and Test in
Europe (DATE’01). IEEE; 2001. doi:10.1109/DATE.2001.915002'
apa: Müller, W., Ruf, J., Hoffmann, D. W., Gerlach, J., Kropf, T., & Rosenstiehl,
W. (2001). The Simulation Semantics of SystemC. Proceedings of the Design,
Automation, and Test in Europe (DATE’01). Proceedings Design, Automation
and Test in Europe. Conference and Exhibition 2001. https://doi.org/10.1109/DATE.2001.915002
bibtex: '@inproceedings{Müller_Ruf_Hoffmann_Gerlach_Kropf_Rosenstiehl_2001, place={Munich,
Germany }, title={The Simulation Semantics of SystemC}, DOI={10.1109/DATE.2001.915002},
booktitle={Proceedings of the Design, Automation, and Test in Europe (DATE’01)},
publisher={IEEE}, author={Müller, Wolfgang and Ruf, Jürgen and Hoffmann, D. W.
and Gerlach, Joachim and Kropf, Thomas and Rosenstiehl, W.}, year={2001} }'
chicago: 'Müller, Wolfgang, Jürgen Ruf, D. W. Hoffmann, Joachim Gerlach, Thomas
Kropf, and W. Rosenstiehl. “The Simulation Semantics of SystemC.” In Proceedings
of the Design, Automation, and Test in Europe (DATE’01). Munich, Germany :
IEEE, 2001. https://doi.org/10.1109/DATE.2001.915002.'
ieee: 'W. Müller, J. Ruf, D. W. Hoffmann, J. Gerlach, T. Kropf, and W. Rosenstiehl,
“The Simulation Semantics of SystemC,” presented at the Proceedings Design, Automation
and Test in Europe. Conference and Exhibition 2001, 2001, doi: 10.1109/DATE.2001.915002.'
mla: Müller, Wolfgang, et al. “The Simulation Semantics of SystemC.” Proceedings
of the Design, Automation, and Test in Europe (DATE’01), IEEE, 2001, doi:10.1109/DATE.2001.915002.
short: 'W. Müller, J. Ruf, D.W. Hoffmann, J. Gerlach, T. Kropf, W. Rosenstiehl,
in: Proceedings of the Design, Automation, and Test in Europe (DATE’01), IEEE,
Munich, Germany , 2001.'
conference:
name: ' Proceedings Design, Automation and Test in Europe. Conference and Exhibition
2001'
date_created: 2023-01-24T10:39:33Z
date_updated: 2023-01-24T10:39:38Z
department:
- _id: '672'
doi: 10.1109/DATE.2001.915002
keyword:
- Yarn
- Formal verification
- Kernel
- Hardware design languages
- Electronic design automation and methodology
- Algebra
- Computational modeling
- Logic functions
- Computer languages
- Clocks
language:
- iso: eng
place: 'Munich, Germany '
publication: Proceedings of the Design, Automation, and Test in Europe (DATE’01)
publication_identifier:
isbn:
- 0-7695-0993-2
publisher: IEEE
status: public
title: The Simulation Semantics of SystemC
type: conference
user_id: '5786'
year: '2001'
...