[{"date_created":"2025-11-04T09:37:50Z","publisher":"Springer Science and Business Media LLC","title":"Analyzing performance portability for a SYCL implementation of the 2D shallow water equations","issue":"6","quality_controlled":"1","year":"2025","language":[{"iso":"eng"}],"publication":"The Journal of Supercomputing","abstract":[{"lang":"eng","text":"SYCL is an open standard for targeting heterogeneous hardware from C++. In this work, we evaluate a SYCL implementation for a discontinuous Galerkin discretization of the 2D shallow water equations targeting CPUs, GPUs, and also FPGAs. The discretization uses polynomial orders zero to two on unstructured triangular meshes. Separating memory accesses from the numerical code allow us to optimize data accesses for the target architecture. A performance analysis shows good portability across x86 and ARM CPUs, GPUs from different vendors, and even two variants of Intel Stratix 10 FPGAs. Measuring the energy to solution shows that GPUs yield an up to 10x higher energy efficiency in terms of degrees of freedom per joule compared to CPUs. With custom designed caches, FPGAs offer a meaningful complement to the other architectures with particularly good computational performance on smaller meshes. FPGAs with High Bandwidth Memory are less affected by bandwidth issues and have similar energy efficiency as latest generation CPUs."}],"volume":81,"author":[{"full_name":"Büttner, Markus","last_name":"Büttner","first_name":"Markus"},{"last_name":"Alt","full_name":"Alt, Christoph","id":"100625","first_name":"Christoph"},{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"first_name":"Harald","last_name":"Köstler","full_name":"Köstler, Harald"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Vadym","full_name":"Aizinger, Vadym","last_name":"Aizinger"}],"oa":"1","date_updated":"2025-11-04T09:48:10Z","doi":"10.1007/s11227-025-07063-7","main_file_link":[{"open_access":"1"}],"publication_identifier":{"issn":["1573-0484"]},"publication_status":"published","intvolume":"        81","citation":{"apa":"Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., &#38; Aizinger, V. (2025). Analyzing performance portability for a SYCL implementation of the 2D shallow water equations. <i>The Journal of Supercomputing</i>, <i>81</i>(6), Article 772. <a href=\"https://doi.org/10.1007/s11227-025-07063-7\">https://doi.org/10.1007/s11227-025-07063-7</a>","short":"M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, The Journal of Supercomputing 81 (2025).","bibtex":"@article{Büttner_Alt_Kenter_Köstler_Plessl_Aizinger_2025, title={Analyzing performance portability for a SYCL implementation of the 2D shallow water equations}, volume={81}, DOI={<a href=\"https://doi.org/10.1007/s11227-025-07063-7\">10.1007/s11227-025-07063-7</a>}, number={6772}, journal={The Journal of Supercomputing}, publisher={Springer Science and Business Media LLC}, author={Büttner, Markus and Alt, Christoph and Kenter, Tobias and Köstler, Harald and Plessl, Christian and Aizinger, Vadym}, year={2025} }","mla":"Büttner, Markus, et al. “Analyzing Performance Portability for a SYCL Implementation of the 2D Shallow Water Equations.” <i>The Journal of Supercomputing</i>, vol. 81, no. 6, 772, Springer Science and Business Media LLC, 2025, doi:<a href=\"https://doi.org/10.1007/s11227-025-07063-7\">10.1007/s11227-025-07063-7</a>.","ama":"Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Analyzing performance portability for a SYCL implementation of the 2D shallow water equations. <i>The Journal of Supercomputing</i>. 2025;81(6). doi:<a href=\"https://doi.org/10.1007/s11227-025-07063-7\">10.1007/s11227-025-07063-7</a>","chicago":"Büttner, Markus, Christoph Alt, Tobias Kenter, Harald Köstler, Christian Plessl, and Vadym Aizinger. “Analyzing Performance Portability for a SYCL Implementation of the 2D Shallow Water Equations.” <i>The Journal of Supercomputing</i> 81, no. 6 (2025). <a href=\"https://doi.org/10.1007/s11227-025-07063-7\">https://doi.org/10.1007/s11227-025-07063-7</a>.","ieee":"M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, and V. Aizinger, “Analyzing performance portability for a SYCL implementation of the 2D shallow water equations,” <i>The Journal of Supercomputing</i>, vol. 81, no. 6, Art. no. 772, 2025, doi: <a href=\"https://doi.org/10.1007/s11227-025-07063-7\">10.1007/s11227-025-07063-7</a>."},"department":[{"_id":"27"},{"_id":"518"}],"user_id":"3145","_id":"62064","article_number":"772","type":"journal_article","status":"public"},{"publication":"Proceedings of the 13th International Workshop on OpenCL and SYCL","abstract":[{"lang":"eng","text":"In the context of high-performance computing (HPC) for distributed workloads, individual field-programmable gate arrays (FPGAs) need efficient ways to exchange data, which requires network infrastructure and software abstractions. Dedicated multi-FPGA clusters provide inter-FPGA networks for direct device to device communication. The oneAPI high-level synthesis toolchain offers I/O pipes to allow user kernels to interact with the networking ports of the FPGA board. In this work, we evaluate using oneAPI I/O pipes for direct FPGA-to-FPGA communication by scaling a SYCL implementation of a Jacobi solver on up to 25 FPGAs in the Noctua 2 cluster. We see good results in weak and strong scaling experiments."}],"language":[{"iso":"eng"}],"keyword":["Multi-FPGA","High-level Synthesis","oneAPI","FPGA"],"quality_controlled":"1","year":"2025","date_created":"2025-11-04T09:45:23Z","publisher":"Association for Computing Machinery","title":"Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs","type":"conference","status":"public","department":[{"_id":"27"},{"_id":"518"}],"series_title":"IWOCL ’25","user_id":"3145","_id":"62066","project":[{"_id":"52","name":"Computing Resources Provided by the Paderborn Center for Parallel Computing"}],"publication_identifier":{"isbn":["9798400713606"]},"citation":{"chicago":"Alt, Christoph, Christian Plessl, and Tobias Kenter. “Evaluating OneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to Multiple FPGAs.” In <i>Proceedings of the 13th International Workshop on OpenCL and SYCL</i>. IWOCL ’25. New York, NY, USA: Association for Computing Machinery, 2025. <a href=\"https://doi.org/10.1145/3731125.3731131\">https://doi.org/10.1145/3731125.3731131</a>.","ieee":"C. Alt, C. Plessl, and T. Kenter, “Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs,” 2025, doi: <a href=\"https://doi.org/10.1145/3731125.3731131\">10.1145/3731125.3731131</a>.","ama":"Alt C, Plessl C, Kenter T. Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs. In: <i>Proceedings of the 13th International Workshop on OpenCL and SYCL</i>. IWOCL ’25. Association for Computing Machinery; 2025. doi:<a href=\"https://doi.org/10.1145/3731125.3731131\">10.1145/3731125.3731131</a>","bibtex":"@inproceedings{Alt_Plessl_Kenter_2025, place={New York, NY, USA}, series={IWOCL ’25}, title={Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs}, DOI={<a href=\"https://doi.org/10.1145/3731125.3731131\">10.1145/3731125.3731131</a>}, booktitle={Proceedings of the 13th International Workshop on OpenCL and SYCL}, publisher={Association for Computing Machinery}, author={Alt, Christoph and Plessl, Christian and Kenter, Tobias}, year={2025}, collection={IWOCL ’25} }","mla":"Alt, Christoph, et al. “Evaluating OneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to Multiple FPGAs.” <i>Proceedings of the 13th International Workshop on OpenCL and SYCL</i>, Association for Computing Machinery, 2025, doi:<a href=\"https://doi.org/10.1145/3731125.3731131\">10.1145/3731125.3731131</a>.","short":"C. Alt, C. Plessl, T. Kenter, in: Proceedings of the 13th International Workshop on OpenCL and SYCL, Association for Computing Machinery, New York, NY, USA, 2025.","apa":"Alt, C., Plessl, C., &#38; Kenter, T. (2025). Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs. <i>Proceedings of the 13th International Workshop on OpenCL and SYCL</i>. <a href=\"https://doi.org/10.1145/3731125.3731131\">https://doi.org/10.1145/3731125.3731131</a>"},"place":"New York, NY, USA","author":[{"first_name":"Christoph","id":"100625","full_name":"Alt, Christoph","last_name":"Alt"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"},{"first_name":"Tobias","last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145"}],"oa":"1","date_updated":"2025-11-04T09:47:26Z","doi":"10.1145/3731125.3731131","main_file_link":[{"open_access":"1"}]},{"publication":"2025 IEEE High Performance Extreme Computing Conference (HPEC)","type":"conference","status":"public","_id":"62065","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"3145","language":[{"iso":"eng"}],"quality_controlled":"1","publication_status":"published","year":"2025","citation":{"apa":"Sundriyal, S., Büttner, M., Alt, C., Kenter, T., &#38; Aizinger, V. (2025). Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods. <i>2025 IEEE High Performance Extreme Computing Conference (HPEC)</i>. <a href=\"https://doi.org/10.1109/hpec67600.2025.11196195\">https://doi.org/10.1109/hpec67600.2025.11196195</a>","mla":"Sundriyal, Shivam, et al. “Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods.” <i>2025 IEEE High Performance Extreme Computing Conference (HPEC)</i>, IEEE, 2025, doi:<a href=\"https://doi.org/10.1109/hpec67600.2025.11196195\">10.1109/hpec67600.2025.11196195</a>.","short":"S. Sundriyal, M. Büttner, C. Alt, T. Kenter, V. Aizinger, in: 2025 IEEE High Performance Extreme Computing Conference (HPEC), IEEE, 2025.","bibtex":"@inproceedings{Sundriyal_Büttner_Alt_Kenter_Aizinger_2025, title={Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods}, DOI={<a href=\"https://doi.org/10.1109/hpec67600.2025.11196195\">10.1109/hpec67600.2025.11196195</a>}, booktitle={2025 IEEE High Performance Extreme Computing Conference (HPEC)}, publisher={IEEE}, author={Sundriyal, Shivam and Büttner, Markus and Alt, Christoph and Kenter, Tobias and Aizinger, Vadym}, year={2025} }","chicago":"Sundriyal, Shivam, Markus Büttner, Christoph Alt, Tobias Kenter, and Vadym Aizinger. “Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods.” In <i>2025 IEEE High Performance Extreme Computing Conference (HPEC)</i>. IEEE, 2025. <a href=\"https://doi.org/10.1109/hpec67600.2025.11196195\">https://doi.org/10.1109/hpec67600.2025.11196195</a>.","ieee":"S. Sundriyal, M. Büttner, C. Alt, T. Kenter, and V. Aizinger, “Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods,” 2025, doi: <a href=\"https://doi.org/10.1109/hpec67600.2025.11196195\">10.1109/hpec67600.2025.11196195</a>.","ama":"Sundriyal S, Büttner M, Alt C, Kenter T, Aizinger V. Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods. In: <i>2025 IEEE High Performance Extreme Computing Conference (HPEC)</i>. IEEE; 2025. doi:<a href=\"https://doi.org/10.1109/hpec67600.2025.11196195\">10.1109/hpec67600.2025.11196195</a>"},"publisher":"IEEE","date_updated":"2025-11-04T09:48:46Z","author":[{"full_name":"Sundriyal, Shivam","last_name":"Sundriyal","first_name":"Shivam"},{"full_name":"Büttner, Markus","last_name":"Büttner","first_name":"Markus"},{"last_name":"Alt","id":"100625","full_name":"Alt, Christoph","first_name":"Christoph"},{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"},{"first_name":"Vadym","last_name":"Aizinger","full_name":"Aizinger, Vadym"}],"date_created":"2025-11-04T09:43:18Z","title":"Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods","doi":"10.1109/hpec67600.2025.11196195"},{"language":[{"iso":"eng"}],"user_id":"3145","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"_id":"56605","status":"public","type":"conference","publication":"2024 34th International Conference on Field-Programmable Logic and Applications (FPL)","doi":"10.1109/fpl64840.2024.00023","title":"StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs","date_created":"2024-10-14T07:49:24Z","author":[{"first_name":"Jan-Oliver","orcid":"0000-0003-2314-2784","last_name":"Opdenhövel","full_name":"Opdenhövel, Jan-Oliver","id":"73960"},{"last_name":"Alt","full_name":"Alt, Christoph","id":"100625","first_name":"Christoph"},{"first_name":"Christian","full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982"},{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"}],"date_updated":"2024-10-14T07:56:26Z","publisher":"IEEE","citation":{"ieee":"J.-O. Opdenhövel, C. Alt, C. Plessl, and T. Kenter, “StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs,” 2024, doi: <a href=\"https://doi.org/10.1109/fpl64840.2024.00023\">10.1109/fpl64840.2024.00023</a>.","chicago":"Opdenhövel, Jan-Oliver, Christoph Alt, Christian Plessl, and Tobias Kenter. “StencilStream: A SYCL-Based Stencil Simulation Framework Targeting FPGAs.” In <i>2024 34th International Conference on Field-Programmable Logic and Applications (FPL)</i>. IEEE, 2024. <a href=\"https://doi.org/10.1109/fpl64840.2024.00023\">https://doi.org/10.1109/fpl64840.2024.00023</a>.","ama":"Opdenhövel J-O, Alt C, Plessl C, Kenter T. StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs. In: <i>2024 34th International Conference on Field-Programmable Logic and Applications (FPL)</i>. IEEE; 2024. doi:<a href=\"https://doi.org/10.1109/fpl64840.2024.00023\">10.1109/fpl64840.2024.00023</a>","bibtex":"@inproceedings{Opdenhövel_Alt_Plessl_Kenter_2024, title={StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs}, DOI={<a href=\"https://doi.org/10.1109/fpl64840.2024.00023\">10.1109/fpl64840.2024.00023</a>}, booktitle={2024 34th International Conference on Field-Programmable Logic and Applications (FPL)}, publisher={IEEE}, author={Opdenhövel, Jan-Oliver and Alt, Christoph and Plessl, Christian and Kenter, Tobias}, year={2024} }","mla":"Opdenhövel, Jan-Oliver, et al. “StencilStream: A SYCL-Based Stencil Simulation Framework Targeting FPGAs.” <i>2024 34th International Conference on Field-Programmable Logic and Applications (FPL)</i>, IEEE, 2024, doi:<a href=\"https://doi.org/10.1109/fpl64840.2024.00023\">10.1109/fpl64840.2024.00023</a>.","short":"J.-O. Opdenhövel, C. Alt, C. Plessl, T. Kenter, in: 2024 34th International Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2024.","apa":"Opdenhövel, J.-O., Alt, C., Plessl, C., &#38; Kenter, T. (2024). StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs. <i>2024 34th International Conference on Field-Programmable Logic and Applications (FPL)</i>. <a href=\"https://doi.org/10.1109/fpl64840.2024.00023\">https://doi.org/10.1109/fpl64840.2024.00023</a>"},"year":"2024","publication_status":"published","quality_controlled":"1"},{"publisher":"ACM","date_updated":"2024-11-27T22:50:19Z","author":[{"first_name":"Markus","last_name":"Büttner","full_name":"Büttner, Markus"},{"first_name":"Christoph","id":"100625","full_name":"Alt, Christoph","last_name":"Alt"},{"last_name":"Kenter","full_name":"Kenter, Tobias","id":"3145","first_name":"Tobias"},{"first_name":"Harald","full_name":"Köstler, Harald","last_name":"Köstler"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"last_name":"Aizinger","full_name":"Aizinger, Vadym","first_name":"Vadym"}],"date_created":"2024-05-16T13:24:49Z","title":"Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL","doi":"10.1145/3659914.3659925","quality_controlled":"1","publication_status":"published","year":"2024","citation":{"apa":"Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., &#38; Aizinger, V. (2024). Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL. <i>Proceedings of the Platform for Advanced Scientific Computing Conference (PASC)</i>, Article 11. <a href=\"https://doi.org/10.1145/3659914.3659925\">https://doi.org/10.1145/3659914.3659925</a>","short":"M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, in: Proceedings of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2024.","mla":"Büttner, Markus, et al. “Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL.” <i>Proceedings of the Platform for Advanced Scientific Computing Conference (PASC)</i>, 11, ACM, 2024, doi:<a href=\"https://doi.org/10.1145/3659914.3659925\">10.1145/3659914.3659925</a>.","bibtex":"@inproceedings{Büttner_Alt_Kenter_Köstler_Plessl_Aizinger_2024, title={Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL}, DOI={<a href=\"https://doi.org/10.1145/3659914.3659925\">10.1145/3659914.3659925</a>}, number={11}, booktitle={Proceedings of the Platform for Advanced Scientific Computing Conference (PASC)}, publisher={ACM}, author={Büttner, Markus and Alt, Christoph and Kenter, Tobias and Köstler, Harald and Plessl, Christian and Aizinger, Vadym}, year={2024} }","chicago":"Büttner, Markus, Christoph Alt, Tobias Kenter, Harald Köstler, Christian Plessl, and Vadym Aizinger. “Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL.” In <i>Proceedings of the Platform for Advanced Scientific Computing Conference (PASC)</i>. ACM, 2024. <a href=\"https://doi.org/10.1145/3659914.3659925\">https://doi.org/10.1145/3659914.3659925</a>.","ieee":"M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, and V. Aizinger, “Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL,” 2024, doi: <a href=\"https://doi.org/10.1145/3659914.3659925\">10.1145/3659914.3659925</a>.","ama":"Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL. In: <i>Proceedings of the Platform for Advanced Scientific Computing Conference (PASC)</i>. ACM; 2024. doi:<a href=\"https://doi.org/10.1145/3659914.3659925\">10.1145/3659914.3659925</a>"},"_id":"54312","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"16153","article_number":"11","language":[{"iso":"eng"}],"publication":"Proceedings of the Platform for Advanced Scientific Computing Conference (PASC)","type":"conference","status":"public"},{"date_updated":"2025-06-24T14:04:05Z","publisher":"Wiley","volume":24,"author":[{"first_name":"Jonas","last_name":"Plewinski","full_name":"Plewinski, Jonas"},{"first_name":"Christoph","id":"100625","full_name":"Alt, Christoph","last_name":"Alt"},{"first_name":"Harald","last_name":"Köstler","full_name":"Köstler, Harald"},{"first_name":"Ulrich","full_name":"Rüde, Ulrich","last_name":"Rüde"}],"date_created":"2025-06-24T14:01:15Z","title":"Performance analysis of the free surface lattice Boltzmann implementation in waLBerla","doi":"10.1002/pamm.202400196","publication_identifier":{"issn":["1617-7061","1617-7061"]},"publication_status":"published","issue":"3","year":"2024","intvolume":"        24","citation":{"short":"J. Plewinski, C. Alt, H. Köstler, U. Rüde, in: PAMM, Wiley, 2024.","mla":"Plewinski, Jonas, et al. “Performance Analysis of the Free Surface Lattice Boltzmann Implementation in WaLBerla.” <i>PAMM</i>, vol. 24, no. 3, Wiley, 2024, doi:<a href=\"https://doi.org/10.1002/pamm.202400196\">10.1002/pamm.202400196</a>.","bibtex":"@inproceedings{Plewinski_Alt_Köstler_Rüde_2024, title={Performance analysis of the free surface lattice Boltzmann implementation in waLBerla}, volume={24}, DOI={<a href=\"https://doi.org/10.1002/pamm.202400196\">10.1002/pamm.202400196</a>}, number={3}, booktitle={PAMM}, publisher={Wiley}, author={Plewinski, Jonas and Alt, Christoph and Köstler, Harald and Rüde, Ulrich}, year={2024} }","ama":"Plewinski J, Alt C, Köstler H, Rüde U. Performance analysis of the free surface lattice Boltzmann implementation in waLBerla. In: <i>PAMM</i>. Vol 24. Wiley; 2024. doi:<a href=\"https://doi.org/10.1002/pamm.202400196\">10.1002/pamm.202400196</a>","apa":"Plewinski, J., Alt, C., Köstler, H., &#38; Rüde, U. (2024). Performance analysis of the free surface lattice Boltzmann implementation in waLBerla. <i>PAMM</i>, <i>24</i>(3). <a href=\"https://doi.org/10.1002/pamm.202400196\">https://doi.org/10.1002/pamm.202400196</a>","ieee":"J. Plewinski, C. Alt, H. Köstler, and U. Rüde, “Performance analysis of the free surface lattice Boltzmann implementation in waLBerla,” in <i>PAMM</i>, 2024, vol. 24, no. 3, doi: <a href=\"https://doi.org/10.1002/pamm.202400196\">10.1002/pamm.202400196</a>.","chicago":"Plewinski, Jonas, Christoph Alt, Harald Köstler, and Ulrich Rüde. “Performance Analysis of the Free Surface Lattice Boltzmann Implementation in WaLBerla.” In <i>PAMM</i>, Vol. 24. Wiley, 2024. <a href=\"https://doi.org/10.1002/pamm.202400196\">https://doi.org/10.1002/pamm.202400196</a>."},"_id":"60359","user_id":"100625","language":[{"iso":"eng"}],"publication":"PAMM","type":"conference","abstract":[{"text":"<jats:title>Abstract</jats:title><jats:p>The free‐surface lattice Boltzmann method uses a volume of fluid approach to simulate immiscible two‐fluid flow problems. It divides the simulation domain into three distinct phases—gas, fluid, and interface—where computation within the gas phase is disregarded. The interface delineates a one‐cell‐thick layer between the first two phases, validated physically for implementation in the HPC C++ multiphysics framework <jats:sc>waLBerla</jats:sc> but lacking an exhaustive performance analysis. This paper aims to shed light on node‐level performance on different architectures, employing continuous benchmarking, showing and analyzing weak scaling results on a modern HPC cluster, the Fritz supercomputer, and reporting energy consumption for the current implementation.</jats:p>","lang":"eng"}],"status":"public"},{"author":[{"first_name":"Christoph","last_name":"Alt","full_name":"Alt, Christoph","id":"100625"},{"last_name":"Lanser","full_name":"Lanser, Martin","first_name":"Martin"},{"first_name":"Jonas","full_name":"Plewinski, Jonas","last_name":"Plewinski"},{"last_name":"Janki","full_name":"Janki, Atin","first_name":"Atin"},{"first_name":"Axel","full_name":"Klawonn, Axel","last_name":"Klawonn"},{"last_name":"Köstler","full_name":"Köstler, Harald","first_name":"Harald"},{"full_name":"Selzer, Michael","last_name":"Selzer","first_name":"Michael"},{"last_name":"Rüde","full_name":"Rüde, Ulrich","first_name":"Ulrich"}],"date_created":"2025-06-24T13:58:36Z","volume":39,"publisher":"Informa UK Limited","date_updated":"2025-06-24T14:04:14Z","doi":"10.1080/17445760.2024.2360190","title":"A continuous benchmarking infrastructure for high-performance computing applications","issue":"4","publication_status":"published","publication_identifier":{"issn":["1744-5760","1744-5779"]},"citation":{"ieee":"C. Alt <i>et al.</i>, “A continuous benchmarking infrastructure for high-performance computing applications,” <i>International Journal of Parallel, Emergent and Distributed Systems</i>, vol. 39, no. 4, pp. 501–523, 2024, doi: <a href=\"https://doi.org/10.1080/17445760.2024.2360190\">10.1080/17445760.2024.2360190</a>.","chicago":"Alt, Christoph, Martin Lanser, Jonas Plewinski, Atin Janki, Axel Klawonn, Harald Köstler, Michael Selzer, and Ulrich Rüde. “A Continuous Benchmarking Infrastructure for High-Performance Computing Applications.” <i>International Journal of Parallel, Emergent and Distributed Systems</i> 39, no. 4 (2024): 501–23. <a href=\"https://doi.org/10.1080/17445760.2024.2360190\">https://doi.org/10.1080/17445760.2024.2360190</a>.","ama":"Alt C, Lanser M, Plewinski J, et al. A continuous benchmarking infrastructure for high-performance computing applications. <i>International Journal of Parallel, Emergent and Distributed Systems</i>. 2024;39(4):501-523. doi:<a href=\"https://doi.org/10.1080/17445760.2024.2360190\">10.1080/17445760.2024.2360190</a>","mla":"Alt, Christoph, et al. “A Continuous Benchmarking Infrastructure for High-Performance Computing Applications.” <i>International Journal of Parallel, Emergent and Distributed Systems</i>, vol. 39, no. 4, Informa UK Limited, 2024, pp. 501–23, doi:<a href=\"https://doi.org/10.1080/17445760.2024.2360190\">10.1080/17445760.2024.2360190</a>.","short":"C. Alt, M. Lanser, J. Plewinski, A. Janki, A. Klawonn, H. Köstler, M. Selzer, U. Rüde, International Journal of Parallel, Emergent and Distributed Systems 39 (2024) 501–523.","bibtex":"@article{Alt_Lanser_Plewinski_Janki_Klawonn_Köstler_Selzer_Rüde_2024, title={A continuous benchmarking infrastructure for high-performance computing applications}, volume={39}, DOI={<a href=\"https://doi.org/10.1080/17445760.2024.2360190\">10.1080/17445760.2024.2360190</a>}, number={4}, journal={International Journal of Parallel, Emergent and Distributed Systems}, publisher={Informa UK Limited}, author={Alt, Christoph and Lanser, Martin and Plewinski, Jonas and Janki, Atin and Klawonn, Axel and Köstler, Harald and Selzer, Michael and Rüde, Ulrich}, year={2024}, pages={501–523} }","apa":"Alt, C., Lanser, M., Plewinski, J., Janki, A., Klawonn, A., Köstler, H., Selzer, M., &#38; Rüde, U. (2024). A continuous benchmarking infrastructure for high-performance computing applications. <i>International Journal of Parallel, Emergent and Distributed Systems</i>, <i>39</i>(4), 501–523. <a href=\"https://doi.org/10.1080/17445760.2024.2360190\">https://doi.org/10.1080/17445760.2024.2360190</a>"},"intvolume":"        39","page":"501-523","year":"2024","user_id":"100625","_id":"60358","language":[{"iso":"eng"}],"type":"journal_article","publication":"International Journal of Parallel, Emergent and Distributed Systems","status":"public"},{"type":"book_chapter","publication":"Lecture Notes in Computer Science","status":"public","user_id":"3145","department":[{"_id":"27"},{"_id":"518"}],"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"_id":"46191","language":[{"iso":"eng"}],"publication_status":"published","publication_identifier":{"isbn":["9783031320408","9783031320415"],"issn":["0302-9743","1611-3349"]},"quality_controlled":"1","citation":{"apa":"Alt, C., Kenter, T., Faghih-Naini, S., Faj, J., Opdenhövel, J.-O., Plessl, C., Aizinger, V., Hönig, J., &#38; Köstler, H. (2023). Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline. In <i>Lecture Notes in Computer Science</i>. Springer Nature Switzerland. <a href=\"https://doi.org/10.1007/978-3-031-32041-5_5\">https://doi.org/10.1007/978-3-031-32041-5_5</a>","mla":"Alt, Christoph, et al. “Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline.” <i>Lecture Notes in Computer Science</i>, Springer Nature Switzerland, 2023, doi:<a href=\"https://doi.org/10.1007/978-3-031-32041-5_5\">10.1007/978-3-031-32041-5_5</a>.","short":"C. Alt, T. Kenter, S. Faghih-Naini, J. Faj, J.-O. Opdenhövel, C. Plessl, V. Aizinger, J. Hönig, H. Köstler, in: Lecture Notes in Computer Science, Springer Nature Switzerland, Cham, 2023.","bibtex":"@inbook{Alt_Kenter_Faghih-Naini_Faj_Opdenhövel_Plessl_Aizinger_Hönig_Köstler_2023, place={Cham}, title={Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline}, DOI={<a href=\"https://doi.org/10.1007/978-3-031-32041-5_5\">10.1007/978-3-031-32041-5_5</a>}, booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland}, author={Alt, Christoph and Kenter, Tobias and Faghih-Naini, Sara and Faj, Jennifer and Opdenhövel, Jan-Oliver and Plessl, Christian and Aizinger, Vadym and Hönig, Jan and Köstler, Harald}, year={2023} }","chicago":"Alt, Christoph, Tobias Kenter, Sara Faghih-Naini, Jennifer Faj, Jan-Oliver Opdenhövel, Christian Plessl, Vadym Aizinger, Jan Hönig, and Harald Köstler. “Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline.” In <i>Lecture Notes in Computer Science</i>. Cham: Springer Nature Switzerland, 2023. <a href=\"https://doi.org/10.1007/978-3-031-32041-5_5\">https://doi.org/10.1007/978-3-031-32041-5_5</a>.","ieee":"C. Alt <i>et al.</i>, “Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline,” in <i>Lecture Notes in Computer Science</i>, Cham: Springer Nature Switzerland, 2023.","ama":"Alt C, Kenter T, Faghih-Naini S, et al. Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline. In: <i>Lecture Notes in Computer Science</i>. Springer Nature Switzerland; 2023. doi:<a href=\"https://doi.org/10.1007/978-3-031-32041-5_5\">10.1007/978-3-031-32041-5_5</a>"},"year":"2023","place":"Cham","date_created":"2023-07-28T09:53:21Z","author":[{"full_name":"Alt, Christoph","id":"100625","last_name":"Alt","first_name":"Christoph"},{"first_name":"Tobias","last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias"},{"first_name":"Sara","full_name":"Faghih-Naini, Sara","last_name":"Faghih-Naini"},{"id":"78722","full_name":"Faj, Jennifer","last_name":"Faj","first_name":"Jennifer"},{"first_name":"Jan-Oliver","last_name":"Opdenhövel","orcid":"0000-0003-2314-2784","full_name":"Opdenhövel, Jan-Oliver","id":"73960"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","full_name":"Plessl, Christian","id":"16153"},{"first_name":"Vadym","last_name":"Aizinger","full_name":"Aizinger, Vadym"},{"last_name":"Hönig","full_name":"Hönig, Jan","first_name":"Jan"},{"first_name":"Harald","full_name":"Köstler, Harald","last_name":"Köstler"}],"date_updated":"2025-11-04T09:32:49Z","publisher":"Springer Nature Switzerland","doi":"10.1007/978-3-031-32041-5_5","title":"Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation Pipeline"}]