---
_id: '62064'
abstract:
- lang: eng
text: SYCL is an open standard for targeting heterogeneous hardware from C++. In
this work, we evaluate a SYCL implementation for a discontinuous Galerkin discretization
of the 2D shallow water equations targeting CPUs, GPUs, and also FPGAs. The discretization
uses polynomial orders zero to two on unstructured triangular meshes. Separating
memory accesses from the numerical code allow us to optimize data accesses for
the target architecture. A performance analysis shows good portability across
x86 and ARM CPUs, GPUs from different vendors, and even two variants of Intel
Stratix 10 FPGAs. Measuring the energy to solution shows that GPUs yield an up
to 10x higher energy efficiency in terms of degrees of freedom per joule compared
to CPUs. With custom designed caches, FPGAs offer a meaningful complement to the
other architectures with particularly good computational performance on smaller
meshes. FPGAs with High Bandwidth Memory are less affected by bandwidth issues
and have similar energy efficiency as latest generation CPUs.
article_number: '772'
author:
- first_name: Markus
full_name: Büttner, Markus
last_name: Büttner
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Analyzing performance
portability for a SYCL implementation of the 2D shallow water equations. The
Journal of Supercomputing. 2025;81(6). doi:10.1007/s11227-025-07063-7
apa: Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., & Aizinger,
V. (2025). Analyzing performance portability for a SYCL implementation of the
2D shallow water equations. The Journal of Supercomputing, 81(6),
Article 772. https://doi.org/10.1007/s11227-025-07063-7
bibtex: '@article{Büttner_Alt_Kenter_Köstler_Plessl_Aizinger_2025, title={Analyzing
performance portability for a SYCL implementation of the 2D shallow water equations},
volume={81}, DOI={10.1007/s11227-025-07063-7},
number={6772}, journal={The Journal of Supercomputing}, publisher={Springer Science
and Business Media LLC}, author={Büttner, Markus and Alt, Christoph and Kenter,
Tobias and Köstler, Harald and Plessl, Christian and Aizinger, Vadym}, year={2025}
}'
chicago: Büttner, Markus, Christoph Alt, Tobias Kenter, Harald Köstler, Christian
Plessl, and Vadym Aizinger. “Analyzing Performance Portability for a SYCL Implementation
of the 2D Shallow Water Equations.” The Journal of Supercomputing 81, no.
6 (2025). https://doi.org/10.1007/s11227-025-07063-7.
ieee: 'M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, and V. Aizinger, “Analyzing
performance portability for a SYCL implementation of the 2D shallow water equations,”
The Journal of Supercomputing, vol. 81, no. 6, Art. no. 772, 2025, doi:
10.1007/s11227-025-07063-7.'
mla: Büttner, Markus, et al. “Analyzing Performance Portability for a SYCL Implementation
of the 2D Shallow Water Equations.” The Journal of Supercomputing, vol.
81, no. 6, 772, Springer Science and Business Media LLC, 2025, doi:10.1007/s11227-025-07063-7.
short: M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, The Journal
of Supercomputing 81 (2025).
date_created: 2025-11-04T09:37:50Z
date_updated: 2025-11-04T09:48:10Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/s11227-025-07063-7
intvolume: ' 81'
issue: '6'
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
publication: The Journal of Supercomputing
publication_identifier:
issn:
- 1573-0484
publication_status: published
publisher: Springer Science and Business Media LLC
quality_controlled: '1'
status: public
title: Analyzing performance portability for a SYCL implementation of the 2D shallow
water equations
type: journal_article
user_id: '3145'
volume: 81
year: '2025'
...
---
_id: '62066'
abstract:
- lang: eng
text: In the context of high-performance computing (HPC) for distributed workloads,
individual field-programmable gate arrays (FPGAs) need efficient ways to exchange
data, which requires network infrastructure and software abstractions. Dedicated
multi-FPGA clusters provide inter-FPGA networks for direct device to device communication.
The oneAPI high-level synthesis toolchain offers I/O pipes to allow user kernels
to interact with the networking ports of the FPGA board. In this work, we evaluate
using oneAPI I/O pipes for direct FPGA-to-FPGA communication by scaling a SYCL
implementation of a Jacobi solver on up to 25 FPGAs in the Noctua 2 cluster. We
see good results in weak and strong scaling experiments.
author:
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Alt C, Plessl C, Kenter T. Evaluating oneAPI I/O Pipes in a Case Study of
Scaling a SYCL Jacobi Solver to multiple FPGAs. In: Proceedings of the 13th
International Workshop on OpenCL and SYCL. IWOCL ’25. Association for Computing
Machinery; 2025. doi:10.1145/3731125.3731131'
apa: Alt, C., Plessl, C., & Kenter, T. (2025). Evaluating oneAPI I/O Pipes in
a Case Study of Scaling a SYCL Jacobi Solver to multiple FPGAs. Proceedings
of the 13th International Workshop on OpenCL and SYCL. https://doi.org/10.1145/3731125.3731131
bibtex: '@inproceedings{Alt_Plessl_Kenter_2025, place={New York, NY, USA}, series={IWOCL
’25}, title={Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi
Solver to multiple FPGAs}, DOI={10.1145/3731125.3731131},
booktitle={Proceedings of the 13th International Workshop on OpenCL and SYCL},
publisher={Association for Computing Machinery}, author={Alt, Christoph and Plessl,
Christian and Kenter, Tobias}, year={2025}, collection={IWOCL ’25} }'
chicago: 'Alt, Christoph, Christian Plessl, and Tobias Kenter. “Evaluating OneAPI
I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver to Multiple FPGAs.”
In Proceedings of the 13th International Workshop on OpenCL and SYCL. IWOCL
’25. New York, NY, USA: Association for Computing Machinery, 2025. https://doi.org/10.1145/3731125.3731131.'
ieee: 'C. Alt, C. Plessl, and T. Kenter, “Evaluating oneAPI I/O Pipes in a Case
Study of Scaling a SYCL Jacobi Solver to multiple FPGAs,” 2025, doi: 10.1145/3731125.3731131.'
mla: Alt, Christoph, et al. “Evaluating OneAPI I/O Pipes in a Case Study of Scaling
a SYCL Jacobi Solver to Multiple FPGAs.” Proceedings of the 13th International
Workshop on OpenCL and SYCL, Association for Computing Machinery, 2025, doi:10.1145/3731125.3731131.
short: 'C. Alt, C. Plessl, T. Kenter, in: Proceedings of the 13th International
Workshop on OpenCL and SYCL, Association for Computing Machinery, New York, NY,
USA, 2025.'
date_created: 2025-11-04T09:45:23Z
date_updated: 2025-11-04T09:47:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3731125.3731131
keyword:
- Multi-FPGA
- High-level Synthesis
- oneAPI
- FPGA
language:
- iso: eng
main_file_link:
- open_access: '1'
oa: '1'
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 13th International Workshop on OpenCL and SYCL
publication_identifier:
isbn:
- '9798400713606'
publisher: Association for Computing Machinery
quality_controlled: '1'
series_title: IWOCL ’25
status: public
title: Evaluating oneAPI I/O Pipes in a Case Study of Scaling a SYCL Jacobi Solver
to multiple FPGAs
type: conference
user_id: '3145'
year: '2025'
...
---
_id: '62065'
author:
- first_name: Shivam
full_name: Sundriyal, Shivam
last_name: Sundriyal
- first_name: Markus
full_name: Büttner, Markus
last_name: Büttner
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: 'Sundriyal S, Büttner M, Alt C, Kenter T, Aizinger V. Adaptive Spectral Block
Floating Point for Discontinuous Galerkin Methods. In: 2025 IEEE High Performance
Extreme Computing Conference (HPEC). IEEE; 2025. doi:10.1109/hpec67600.2025.11196195'
apa: Sundriyal, S., Büttner, M., Alt, C., Kenter, T., & Aizinger, V. (2025).
Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods. 2025
IEEE High Performance Extreme Computing Conference (HPEC). https://doi.org/10.1109/hpec67600.2025.11196195
bibtex: '@inproceedings{Sundriyal_Büttner_Alt_Kenter_Aizinger_2025, title={Adaptive
Spectral Block Floating Point for Discontinuous Galerkin Methods}, DOI={10.1109/hpec67600.2025.11196195},
booktitle={2025 IEEE High Performance Extreme Computing Conference (HPEC)}, publisher={IEEE},
author={Sundriyal, Shivam and Büttner, Markus and Alt, Christoph and Kenter, Tobias
and Aizinger, Vadym}, year={2025} }'
chicago: Sundriyal, Shivam, Markus Büttner, Christoph Alt, Tobias Kenter, and Vadym
Aizinger. “Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods.”
In 2025 IEEE High Performance Extreme Computing Conference (HPEC). IEEE,
2025. https://doi.org/10.1109/hpec67600.2025.11196195.
ieee: 'S. Sundriyal, M. Büttner, C. Alt, T. Kenter, and V. Aizinger, “Adaptive Spectral
Block Floating Point for Discontinuous Galerkin Methods,” 2025, doi: 10.1109/hpec67600.2025.11196195.'
mla: Sundriyal, Shivam, et al. “Adaptive Spectral Block Floating Point for Discontinuous
Galerkin Methods.” 2025 IEEE High Performance Extreme Computing Conference
(HPEC), IEEE, 2025, doi:10.1109/hpec67600.2025.11196195.
short: 'S. Sundriyal, M. Büttner, C. Alt, T. Kenter, V. Aizinger, in: 2025 IEEE
High Performance Extreme Computing Conference (HPEC), IEEE, 2025.'
date_created: 2025-11-04T09:43:18Z
date_updated: 2025-11-04T09:48:46Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/hpec67600.2025.11196195
language:
- iso: eng
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2025 IEEE High Performance Extreme Computing Conference (HPEC)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: Adaptive Spectral Block Floating Point for Discontinuous Galerkin Methods
type: conference
user_id: '3145'
year: '2025'
...
---
_id: '56605'
author:
- first_name: Jan-Oliver
full_name: Opdenhövel, Jan-Oliver
id: '73960'
last_name: Opdenhövel
orcid: 0000-0003-2314-2784
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
citation:
ama: 'Opdenhövel J-O, Alt C, Plessl C, Kenter T. StencilStream: A SYCL-based Stencil
Simulation Framework Targeting FPGAs. In: 2024 34th International Conference
on Field-Programmable Logic and Applications (FPL). IEEE; 2024. doi:10.1109/fpl64840.2024.00023'
apa: 'Opdenhövel, J.-O., Alt, C., Plessl, C., & Kenter, T. (2024). StencilStream:
A SYCL-based Stencil Simulation Framework Targeting FPGAs. 2024 34th International
Conference on Field-Programmable Logic and Applications (FPL). https://doi.org/10.1109/fpl64840.2024.00023'
bibtex: '@inproceedings{Opdenhövel_Alt_Plessl_Kenter_2024, title={StencilStream:
A SYCL-based Stencil Simulation Framework Targeting FPGAs}, DOI={10.1109/fpl64840.2024.00023},
booktitle={2024 34th International Conference on Field-Programmable Logic and
Applications (FPL)}, publisher={IEEE}, author={Opdenhövel, Jan-Oliver and Alt,
Christoph and Plessl, Christian and Kenter, Tobias}, year={2024} }'
chicago: 'Opdenhövel, Jan-Oliver, Christoph Alt, Christian Plessl, and Tobias Kenter.
“StencilStream: A SYCL-Based Stencil Simulation Framework Targeting FPGAs.” In
2024 34th International Conference on Field-Programmable Logic and Applications
(FPL). IEEE, 2024. https://doi.org/10.1109/fpl64840.2024.00023.'
ieee: 'J.-O. Opdenhövel, C. Alt, C. Plessl, and T. Kenter, “StencilStream: A SYCL-based
Stencil Simulation Framework Targeting FPGAs,” 2024, doi: 10.1109/fpl64840.2024.00023.'
mla: 'Opdenhövel, Jan-Oliver, et al. “StencilStream: A SYCL-Based Stencil Simulation
Framework Targeting FPGAs.” 2024 34th International Conference on Field-Programmable
Logic and Applications (FPL), IEEE, 2024, doi:10.1109/fpl64840.2024.00023.'
short: 'J.-O. Opdenhövel, C. Alt, C. Plessl, T. Kenter, in: 2024 34th International
Conference on Field-Programmable Logic and Applications (FPL), IEEE, 2024.'
date_created: 2024-10-14T07:49:24Z
date_updated: 2024-10-14T07:56:26Z
department:
- _id: '27'
- _id: '518'
doi: 10.1109/fpl64840.2024.00023
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: 2024 34th International Conference on Field-Programmable Logic and Applications
(FPL)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: 'StencilStream: A SYCL-based Stencil Simulation Framework Targeting FPGAs'
type: conference
user_id: '3145'
year: '2024'
...
---
_id: '54312'
article_number: '11'
author:
- first_name: Markus
full_name: Büttner, Markus
last_name: Büttner
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
citation:
ama: 'Büttner M, Alt C, Kenter T, Köstler H, Plessl C, Aizinger V. Enabling Performance
Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with SYCL. In:
Proceedings of the Platform for Advanced Scientific Computing Conference (PASC).
ACM; 2024. doi:10.1145/3659914.3659925'
apa: Büttner, M., Alt, C., Kenter, T., Köstler, H., Plessl, C., & Aizinger,
V. (2024). Enabling Performance Portability for Shallow Water Equations on CPUs,
GPUs, and FPGAs with SYCL. Proceedings of the Platform for Advanced Scientific
Computing Conference (PASC), Article 11. https://doi.org/10.1145/3659914.3659925
bibtex: '@inproceedings{Büttner_Alt_Kenter_Köstler_Plessl_Aizinger_2024, title={Enabling
Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with
SYCL}, DOI={10.1145/3659914.3659925},
number={11}, booktitle={Proceedings of the Platform for Advanced Scientific Computing
Conference (PASC)}, publisher={ACM}, author={Büttner, Markus and Alt, Christoph
and Kenter, Tobias and Köstler, Harald and Plessl, Christian and Aizinger, Vadym},
year={2024} }'
chicago: Büttner, Markus, Christoph Alt, Tobias Kenter, Harald Köstler, Christian
Plessl, and Vadym Aizinger. “Enabling Performance Portability for Shallow Water
Equations on CPUs, GPUs, and FPGAs with SYCL.” In Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC). ACM, 2024. https://doi.org/10.1145/3659914.3659925.
ieee: 'M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, and V. Aizinger, “Enabling
Performance Portability for Shallow Water Equations on CPUs, GPUs, and FPGAs with
SYCL,” 2024, doi: 10.1145/3659914.3659925.'
mla: Büttner, Markus, et al. “Enabling Performance Portability for Shallow Water
Equations on CPUs, GPUs, and FPGAs with SYCL.” Proceedings of the Platform
for Advanced Scientific Computing Conference (PASC), 11, ACM, 2024, doi:10.1145/3659914.3659925.
short: 'M. Büttner, C. Alt, T. Kenter, H. Köstler, C. Plessl, V. Aizinger, in: Proceedings
of the Platform for Advanced Scientific Computing Conference (PASC), ACM, 2024.'
date_created: 2024-05-16T13:24:49Z
date_updated: 2024-11-27T22:50:19Z
department:
- _id: '27'
- _id: '518'
doi: 10.1145/3659914.3659925
language:
- iso: eng
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Proceedings of the Platform for Advanced Scientific Computing Conference
(PASC)
publication_status: published
publisher: ACM
quality_controlled: '1'
status: public
title: Enabling Performance Portability for Shallow Water Equations on CPUs, GPUs,
and FPGAs with SYCL
type: conference
user_id: '16153'
year: '2024'
...
---
_id: '60359'
abstract:
- lang: eng
text: AbstractThe free‐surface lattice Boltzmann
method uses a volume of fluid approach to simulate immiscible two‐fluid flow problems.
It divides the simulation domain into three distinct phases—gas, fluid, and interface—where
computation within the gas phase is disregarded. The interface delineates a one‐cell‐thick
layer between the first two phases, validated physically for implementation in
the HPC C++ multiphysics framework waLBerla but lacking an
exhaustive performance analysis. This paper aims to shed light on node‐level performance
on different architectures, employing continuous benchmarking, showing and analyzing
weak scaling results on a modern HPC cluster, the Fritz supercomputer, and reporting
energy consumption for the current implementation.
author:
- first_name: Jonas
full_name: Plewinski, Jonas
last_name: Plewinski
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
- first_name: Ulrich
full_name: Rüde, Ulrich
last_name: Rüde
citation:
ama: 'Plewinski J, Alt C, Köstler H, Rüde U. Performance analysis of the free surface
lattice Boltzmann implementation in waLBerla. In: PAMM. Vol 24. Wiley;
2024. doi:10.1002/pamm.202400196'
apa: Plewinski, J., Alt, C., Köstler, H., & Rüde, U. (2024). Performance analysis
of the free surface lattice Boltzmann implementation in waLBerla. PAMM,
24(3). https://doi.org/10.1002/pamm.202400196
bibtex: '@inproceedings{Plewinski_Alt_Köstler_Rüde_2024, title={Performance analysis
of the free surface lattice Boltzmann implementation in waLBerla}, volume={24},
DOI={10.1002/pamm.202400196},
number={3}, booktitle={PAMM}, publisher={Wiley}, author={Plewinski, Jonas and
Alt, Christoph and Köstler, Harald and Rüde, Ulrich}, year={2024} }'
chicago: Plewinski, Jonas, Christoph Alt, Harald Köstler, and Ulrich Rüde. “Performance
Analysis of the Free Surface Lattice Boltzmann Implementation in WaLBerla.” In
PAMM, Vol. 24. Wiley, 2024. https://doi.org/10.1002/pamm.202400196.
ieee: 'J. Plewinski, C. Alt, H. Köstler, and U. Rüde, “Performance analysis of the
free surface lattice Boltzmann implementation in waLBerla,” in PAMM, 2024,
vol. 24, no. 3, doi: 10.1002/pamm.202400196.'
mla: Plewinski, Jonas, et al. “Performance Analysis of the Free Surface Lattice
Boltzmann Implementation in WaLBerla.” PAMM, vol. 24, no. 3, Wiley, 2024,
doi:10.1002/pamm.202400196.
short: 'J. Plewinski, C. Alt, H. Köstler, U. Rüde, in: PAMM, Wiley, 2024.'
date_created: 2025-06-24T14:01:15Z
date_updated: 2025-06-24T14:04:05Z
doi: 10.1002/pamm.202400196
intvolume: ' 24'
issue: '3'
language:
- iso: eng
publication: PAMM
publication_identifier:
issn:
- 1617-7061
- 1617-7061
publication_status: published
publisher: Wiley
status: public
title: Performance analysis of the free surface lattice Boltzmann implementation in
waLBerla
type: conference
user_id: '100625'
volume: 24
year: '2024'
...
---
_id: '60358'
author:
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Martin
full_name: Lanser, Martin
last_name: Lanser
- first_name: Jonas
full_name: Plewinski, Jonas
last_name: Plewinski
- first_name: Atin
full_name: Janki, Atin
last_name: Janki
- first_name: Axel
full_name: Klawonn, Axel
last_name: Klawonn
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
- first_name: Michael
full_name: Selzer, Michael
last_name: Selzer
- first_name: Ulrich
full_name: Rüde, Ulrich
last_name: Rüde
citation:
ama: Alt C, Lanser M, Plewinski J, et al. A continuous benchmarking infrastructure
for high-performance computing applications. International Journal of Parallel,
Emergent and Distributed Systems. 2024;39(4):501-523. doi:10.1080/17445760.2024.2360190
apa: Alt, C., Lanser, M., Plewinski, J., Janki, A., Klawonn, A., Köstler, H., Selzer,
M., & Rüde, U. (2024). A continuous benchmarking infrastructure for high-performance
computing applications. International Journal of Parallel, Emergent and Distributed
Systems, 39(4), 501–523. https://doi.org/10.1080/17445760.2024.2360190
bibtex: '@article{Alt_Lanser_Plewinski_Janki_Klawonn_Köstler_Selzer_Rüde_2024, title={A
continuous benchmarking infrastructure for high-performance computing applications},
volume={39}, DOI={10.1080/17445760.2024.2360190},
number={4}, journal={International Journal of Parallel, Emergent and Distributed
Systems}, publisher={Informa UK Limited}, author={Alt, Christoph and Lanser, Martin
and Plewinski, Jonas and Janki, Atin and Klawonn, Axel and Köstler, Harald and
Selzer, Michael and Rüde, Ulrich}, year={2024}, pages={501–523} }'
chicago: 'Alt, Christoph, Martin Lanser, Jonas Plewinski, Atin Janki, Axel Klawonn,
Harald Köstler, Michael Selzer, and Ulrich Rüde. “A Continuous Benchmarking Infrastructure
for High-Performance Computing Applications.” International Journal of Parallel,
Emergent and Distributed Systems 39, no. 4 (2024): 501–23. https://doi.org/10.1080/17445760.2024.2360190.'
ieee: 'C. Alt et al., “A continuous benchmarking infrastructure for high-performance
computing applications,” International Journal of Parallel, Emergent and Distributed
Systems, vol. 39, no. 4, pp. 501–523, 2024, doi: 10.1080/17445760.2024.2360190.'
mla: Alt, Christoph, et al. “A Continuous Benchmarking Infrastructure for High-Performance
Computing Applications.” International Journal of Parallel, Emergent and Distributed
Systems, vol. 39, no. 4, Informa UK Limited, 2024, pp. 501–23, doi:10.1080/17445760.2024.2360190.
short: C. Alt, M. Lanser, J. Plewinski, A. Janki, A. Klawonn, H. Köstler, M. Selzer,
U. Rüde, International Journal of Parallel, Emergent and Distributed Systems 39
(2024) 501–523.
date_created: 2025-06-24T13:58:36Z
date_updated: 2025-06-24T14:04:14Z
doi: 10.1080/17445760.2024.2360190
intvolume: ' 39'
issue: '4'
language:
- iso: eng
page: 501-523
publication: International Journal of Parallel, Emergent and Distributed Systems
publication_identifier:
issn:
- 1744-5760
- 1744-5779
publication_status: published
publisher: Informa UK Limited
status: public
title: A continuous benchmarking infrastructure for high-performance computing applications
type: journal_article
user_id: '100625'
volume: 39
year: '2024'
...
---
_id: '46191'
author:
- first_name: Christoph
full_name: Alt, Christoph
id: '100625'
last_name: Alt
- first_name: Tobias
full_name: Kenter, Tobias
id: '3145'
last_name: Kenter
- first_name: Sara
full_name: Faghih-Naini, Sara
last_name: Faghih-Naini
- first_name: Jennifer
full_name: Faj, Jennifer
id: '78722'
last_name: Faj
- first_name: Jan-Oliver
full_name: Opdenhövel, Jan-Oliver
id: '73960'
last_name: Opdenhövel
orcid: 0000-0003-2314-2784
- first_name: Christian
full_name: Plessl, Christian
id: '16153'
last_name: Plessl
orcid: 0000-0001-5728-9982
- first_name: Vadym
full_name: Aizinger, Vadym
last_name: Aizinger
- first_name: Jan
full_name: Hönig, Jan
last_name: Hönig
- first_name: Harald
full_name: Köstler, Harald
last_name: Köstler
citation:
ama: 'Alt C, Kenter T, Faghih-Naini S, et al. Shallow Water DG Simulations on FPGAs:
Design and Comparison of a Novel Code Generation Pipeline. In: Lecture Notes
in Computer Science. Springer Nature Switzerland; 2023. doi:10.1007/978-3-031-32041-5_5'
apa: 'Alt, C., Kenter, T., Faghih-Naini, S., Faj, J., Opdenhövel, J.-O., Plessl,
C., Aizinger, V., Hönig, J., & Köstler, H. (2023). Shallow Water DG Simulations
on FPGAs: Design and Comparison of a Novel Code Generation Pipeline. In Lecture
Notes in Computer Science. Springer Nature Switzerland. https://doi.org/10.1007/978-3-031-32041-5_5'
bibtex: '@inbook{Alt_Kenter_Faghih-Naini_Faj_Opdenhövel_Plessl_Aizinger_Hönig_Köstler_2023,
place={Cham}, title={Shallow Water DG Simulations on FPGAs: Design and Comparison
of a Novel Code Generation Pipeline}, DOI={10.1007/978-3-031-32041-5_5},
booktitle={Lecture Notes in Computer Science}, publisher={Springer Nature Switzerland},
author={Alt, Christoph and Kenter, Tobias and Faghih-Naini, Sara and Faj, Jennifer
and Opdenhövel, Jan-Oliver and Plessl, Christian and Aizinger, Vadym and Hönig,
Jan and Köstler, Harald}, year={2023} }'
chicago: 'Alt, Christoph, Tobias Kenter, Sara Faghih-Naini, Jennifer Faj, Jan-Oliver
Opdenhövel, Christian Plessl, Vadym Aizinger, Jan Hönig, and Harald Köstler. “Shallow
Water DG Simulations on FPGAs: Design and Comparison of a Novel Code Generation
Pipeline.” In Lecture Notes in Computer Science. Cham: Springer Nature
Switzerland, 2023. https://doi.org/10.1007/978-3-031-32041-5_5.'
ieee: 'C. Alt et al., “Shallow Water DG Simulations on FPGAs: Design and Comparison
of a Novel Code Generation Pipeline,” in Lecture Notes in Computer Science,
Cham: Springer Nature Switzerland, 2023.'
mla: 'Alt, Christoph, et al. “Shallow Water DG Simulations on FPGAs: Design and Comparison
of a Novel Code Generation Pipeline.” Lecture Notes in Computer Science,
Springer Nature Switzerland, 2023, doi:10.1007/978-3-031-32041-5_5.'
short: 'C. Alt, T. Kenter, S. Faghih-Naini, J. Faj, J.-O. Opdenhövel, C. Plessl,
V. Aizinger, J. Hönig, H. Köstler, in: Lecture Notes in Computer Science, Springer
Nature Switzerland, Cham, 2023.'
date_created: 2023-07-28T09:53:21Z
date_updated: 2025-11-04T09:32:49Z
department:
- _id: '27'
- _id: '518'
doi: 10.1007/978-3-031-32041-5_5
language:
- iso: eng
place: Cham
project:
- _id: '52'
name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing'
publication: Lecture Notes in Computer Science
publication_identifier:
isbn:
- '9783031320408'
- '9783031320415'
issn:
- 0302-9743
- 1611-3349
publication_status: published
publisher: Springer Nature Switzerland
quality_controlled: '1'
status: public
title: 'Shallow Water DG Simulations on FPGAs: Design and Comparison of a Novel Code
Generation Pipeline'
type: book_chapter
user_id: '3145'
year: '2023'
...