TY - JOUR
AB - CP2K is an open source electronic structure and molecular dynamics software package to perform atomistic simulations of solid-state, liquid, molecular, and biological systems. It is especially aimed at massively parallel and linear-scaling electronic structure methods and state-of-theart ab initio molecular dynamics simulations. Excellent performance for electronic structure calculations is achieved using novel algorithms implemented for modern high-performance computing systems. This review revisits the main capabilities of CP2K to perform efficient and accurate electronic structure simulations. The emphasis is put on density functional theory and multiple post–Hartree–Fock methods using the Gaussian and plane wave approach and its augmented all-electron extension.
AU - Kühne, Thomas
AU - Iannuzzi, Marcella
AU - Ben, Mauro Del
AU - Rybkin, Vladimir V.
AU - Seewald, Patrick
AU - Stein, Frederick
AU - Laino, Teodoro
AU - Khaliullin, Rustam Z.
AU - Schütt, Ole
AU - Schiffmann, Florian
AU - Golze, Dorothea
AU - Wilhelm, Jan
AU - Chulkov, Sergey
AU - Mohammad Hossein Bani-Hashemian, Mohammad Hossein Bani-Hashemian
AU - Weber, Valéry
AU - Borstnik, Urban
AU - Taillefumier, Mathieu
AU - Jakobovits, Alice Shoshana
AU - Lazzaro, Alfio
AU - Pabst, Hans
AU - Müller, Tiziano
AU - Schade, Robert
AU - Guidon, Manuel
AU - Andermatt, Samuel
AU - Holmberg, Nico
AU - Schenter, Gregory K.
AU - Hehn, Anna
AU - Bussy, Augustin
AU - Belleflamme, Fabian
AU - Tabacchi, Gloria
AU - Glöß, Andreas
AU - Lass, Michael
AU - Bethune, Iain
AU - Mundy, Christopher J.
AU - Plessl, Christian
AU - Watkins, Matt
AU - VandeVondele, Joost
AU - Krack, Matthias
AU - Hutter, Jürg
ID - 16277
IS - 19
JF - The Journal of Chemical Physics
TI - CP2K: An electronic structure and molecular dynamics software package - Quickstep: Efficient and accurate electronic structure calculations
VL - 152
ER -
TY - CONF
AB - Electronic structure calculations based on density-functional theory (DFT)
represent a significant part of today's HPC workloads and pose high demands on
high-performance computing resources. To perform these quantum-mechanical DFT
calculations on complex large-scale systems, so-called linear scaling methods
instead of conventional cubic scaling methods are required. In this work, we
take up the idea of the submatrix method and apply it to the DFT computations
in the software package CP2K. For that purpose, we transform the underlying
numeric operations on distributed, large, sparse matrices into computations on
local, much smaller and nearly dense matrices. This allows us to exploit the
full floating-point performance of modern CPUs and to make use of dedicated
accelerator hardware, where performance has been limited by memory bandwidth
before. We demonstrate both functionality and performance of our implementation
and show how it can be accelerated with GPUs and FPGAs.
AU - Lass, Michael
AU - Schade, Robert
AU - Kühne, Thomas
AU - Plessl, Christian
ID - 16898
T2 - Proc. International Conference for High Performance Computing, Networking, Storage and Analysis (SC)
TI - A Submatrix-Based Method for Approximate Matrix Function Evaluation in the Quantum Chemistry Code CP2K
ER -
TY - JOUR
AB - In scientific computing, the acceleration of atomistic computer simulations by means of custom hardware is finding ever-growing application. A major limitation, however, is that the high efficiency in terms of performance and low power consumption entails the massive usage of low precision computing units. Here, based on the approximate computing paradigm, we present an algorithmic method to compensate for numerical inaccuracies due to low accuracy arithmetic operations rigorously, yet still obtaining exact expectation values using a properly modified Langevin-type equation.
AU - Rengaraj, Varadarajan
AU - Lass, Michael
AU - Plessl, Christian
AU - Kühne, Thomas
ID - 12878
IS - 2
JF - Computation
TI - Accurate Sampling with Noisy Forces from Approximate Computing
VL - 8
ER -
TY - JOUR
AU - Platzner, Marco
AU - Plessl, Christian
ID - 12871
JF - Informatik Spektrum
SN - 0170-6012
TI - FPGAs im Rechenzentrum
ER -
TY - JOUR
AU - Riebler, Heinrich
AU - Vaz, Gavin Francis
AU - Kenter, Tobias
AU - Plessl, Christian
ID - 7689
IS - 2
JF - ACM Trans. Archit. Code Optim. (TACO)
KW - htrop
TI - Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL
VL - 16
ER -
TY - CONF
AB - Stratix 10 FPGA cards have a good potential for the acceleration of HPC workloads since the Stratix 10 product line introduces devices with a large number of DSP and memory blocks. The high level synthesis of OpenCL codes can play a fundamental role for FPGAs in HPC, because it allows to implement different designs with lower development effort compared to hand optimized HDL. However, Stratix 10 cards are still hard to fully exploit using the Intel FPGA SDK for OpenCL. The implementation of designs with thousands of concurrent arithmetic operations often suffers from place and route problems that limit the maximum frequency or entirely prevent a successful synthesis. In order to overcome these issues for the implementation of the matrix multiplication, we formulate Cannon's matrix multiplication algorithm with regard to its efficient synthesis within the FPGA logic. We obtain a two-level block algorithm, where the lower level sub-matrices are multiplied using our Cannon's algorithm implementation. Following this design approach with multiple compute units, we are able to get maximum frequencies close to and above 300 MHz with high utilization of DSP and memory blocks. This allows for performance results above 1 TeraFLOPS.
AU - Gorlani, Paolo
AU - Kenter, Tobias
AU - Plessl, Christian
ID - 15478
T2 - Proceedings of the International Conference on Field-Programmable Technology (FPT)
TI - OpenCL Implementation of Cannon's Matrix Multiplication Algorithm on Intel Stratix 10 FPGAs
ER -
TY - JOUR
AB - We address the general mathematical problem of computing the inverse p-th
root of a given matrix in an efficient way. A new method to construct iteration
functions that allow calculating arbitrary p-th roots and their inverses of
symmetric positive definite matrices is presented. We show that the order of
convergence is at least quadratic and that adaptively adjusting a parameter q
always leads to an even faster convergence. In this way, a better performance
than with previously known iteration schemes is achieved. The efficiency of the
iterative functions is demonstrated for various matrices with different
densities, condition numbers and spectral radii.
AU - Richters, Dorothee
AU - Lass, Michael
AU - Walther, Andrea
AU - Plessl, Christian
AU - Kühne, Thomas
ID - 21
IS - 2
JF - Communications in Computational Physics
TI - A General Algorithm to Calculate the Inverse Principal p-th Root of Symmetric Positive Definite Matrices
VL - 25
ER -
TY - JOUR
AU - Mertens, Jan Cedric
AU - Boschmann, Alexander
AU - Schmidt, M.
AU - Plessl, Christian
ID - 6516
IS - 4
JF - Sports Engineering
SN - 1369-7072
TI - Sprint diagnostic with GPS and inertial sensor fusion
VL - 21
ER -
TY - JOUR
AB - Approximate computing has shown to provide new ways to improve performance
and power consumption of error-resilient applications. While many of these
applications can be found in image processing, data classification or machine
learning, we demonstrate its suitability to a problem from scientific
computing. Utilizing the self-correcting behavior of iterative algorithms, we
show that approximate computing can be applied to the calculation of inverse
matrix p-th roots which are required in many applications in scientific
computing. Results show great opportunities to reduce the computational effort
and bandwidth required for the execution of the discussed algorithm, especially
when targeting special accelerator hardware.
AU - Lass, Michael
AU - Kühne, Thomas
AU - Plessl, Christian
ID - 20
IS - 2
JF - Embedded Systems Letters
SN - 1943-0663
TI - Using Approximate Computing for the Calculation of Inverse Matrix p-th Roots
VL - 10
ER -
TY - CONF
AU - Riebler, Heinrich
AU - Vaz, Gavin Francis
AU - Kenter, Tobias
AU - Plessl, Christian
ID - 1204
KW - htrop
SN - 9781450349826
T2 - Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)
TI - Automated Code Acceleration Targeting Heterogeneous OpenCL Devices
ER -
TY - CONF
AB - The exploration of FPGAs as accelerators for scientific simulations has so far mostly been focused on small kernels of methods working on regular data structures, for example in the form of stencil computations for finite difference methods. In computational sciences, often more advanced methods are employed that promise better stability, convergence, locality and scaling. Unstructured meshes are shown to be more effective and more accurate, compared to regular grids, in representing computation domains of various shapes. Using unstructured meshes, the discontinuous Galerkin method preserves the ability to perform explicit local update operations for simulations in the time domain. In this work, we investigate FPGAs as target platform for an implementation of the nodal discontinuous Galerkin method to find time-domain solutions of Maxwell's equations in an unstructured mesh. When maximizing data reuse and fitting constant coefficients into suitably partitioned on-chip memory, high computational intensity allows us to implement and feed wide data paths with hundreds of floating point operators. By decoupling off-chip memory accesses from the computations, high memory bandwidth can be sustained, even for the irregular access pattern required by parts of the application. Using the Intel/Altera OpenCL SDK for FPGAs, we present different implementation variants for different polynomial orders of the method. In different phases of the algorithm, either computational or bandwidth limits of the Arria 10 platform are almost reached, thus outperforming a highly multithreaded CPU implementation by around 2x.
AU - Kenter, Tobias
AU - Mahale, Gopinath
AU - Alhaddad, Samer
AU - Grynko, Yevgen
AU - Schmitt, Christian
AU - Afzal, Ayesha
AU - Hannig, Frank
AU - Förstner, Jens
AU - Plessl, Christian
ID - 1588
KW - tet_topic_hpc
T2 - Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM)
TI - OpenCL-based FPGA Design to Accelerate the Nodal Discontinuous Galerkin Method for Unstructured Meshes
ER -
TY - CONF
AB - We present the submatrix method, a highly parallelizable method for the approximate calculation of inverse p-th roots of large sparse symmetric matrices which are required in different scientific applications. Following the idea of Approximate Computing, we allow imprecision in the final result in order to utilize the sparsity of the input matrix and to allow massively parallel execution. For an n x n matrix, the proposed algorithm allows to distribute the calculations over n nodes with only little communication overhead. The result matrix exhibits the same sparsity pattern as the input matrix, allowing for efficient reuse of allocated data structures.
We evaluate the algorithm with respect to the error that it introduces into calculated results, as well as its performance and scalability. We demonstrate that the error is relatively limited for well-conditioned matrices and that results are still valuable for error-resilient applications like preconditioning even for ill-conditioned matrices. We discuss the execution time and scaling of the algorithm on a theoretical level and present a distributed implementation of the algorithm using MPI and OpenMP. We demonstrate the scalability of this implementation by running it on a high-performance compute cluster comprised of 1024 CPU cores, showing a speedup of 665x compared to single-threaded execution.
AU - Lass, Michael
AU - Mohr, Stephan
AU - Wiebeler, Hendrik
AU - Kühne, Thomas
AU - Plessl, Christian
ID - 1590
KW - approximate computing
KW - linear algebra
KW - matrix inversion
KW - matrix p-th roots
KW - numeric algorithm
KW - parallel computing
SN - 978-1-4503-5891-0/18/07
T2 - Proc. Platform for Advanced Scientific Computing (PASC) Conference
TI - A Massively Parallel Algorithm for the Approximate Calculation of Inverse p-th Roots of Large Sparse Matrices
ER -
TY - JOUR
AU - Schumacher, Jörn
AU - Plessl, Christian
AU - Vandelli, Wainer
ID - 1589
JF - Journal of Physics: Conference Series
TI - High-Throughput and Low-Latency Network Communication with NetIO
VL - 898
ER -
TY - CONF
AB - Compared to classical HDL designs, generating FPGA with high-level synthesis from an OpenCL specification promises easier exploration of different design alternatives and, through ready-to-use infrastructure and common abstractions for host and memory interfaces, easier portability between different FPGA families. In this work, we evaluate the extent of this promise. To this end, we present a parameterized FDTD implementation for photonic microcavity simulations. Our design can trade-off different forms of parallelism and works for two independent OpenCL-based FPGA design flows. Hence, we can target FPGAs from different vendors and different FPGA families. We describe how we used pre-processor macros to achieve this flexibility and to work around different shortcomings of the current tools. Choosing the right design configurations, we are able to present two extremely competitive solutions for very different FPGA targets, reaching up to 172 GFLOPS sustained performance. With the portability and flexibility demonstrated, code developers not only avoid vendor lock-in, but can even make best use of real trade-offs between different architectures.
AU - Kenter, Tobias
AU - Förstner, Jens
AU - Plessl, Christian
ID - 1592
KW - tet_topic_hpc
T2 - Proc. Int. Conf. on Field Programmable Logic and Applications (FPL)
TI - Flexible FPGA design for FDTD using OpenCL
ER -
TY - JOUR
AB - Branch and bound (B&B) algorithms structure the search space as a tree and eliminate infeasible solutions early by pruning subtrees that cannot lead to a valid or optimal solution. Custom hardware designs significantly accelerate the execution of these algorithms. In this article, we demonstrate a high-performance B&B implementation on FPGAs. First, we identify general elements of B&B algorithms and describe their implementation as a finite state machine. Then, we introduce workers that autonomously cooperate using work stealing to allow parallel execution and full utilization of the target FPGA. Finally, we explore advantages of instance-specific designs that target a specific problem instance to improve performance.
We evaluate our concepts by applying them to a branch and bound problem, the reconstruction of corrupted AES keys obtained from cold-boot attacks. The evaluation shows that our work stealing approach is scalable with the available resources and provides speedups proportional to the number of workers. Instance-specific designs allow us to achieve an overall speedup of 47 × compared to the fastest implementation of AES key reconstruction so far. Finally, we demonstrate how instance-specific designs can be generated just-in-time such that the provided speedups outweigh the additional time required for design synthesis.
AU - Riebler, Heinrich
AU - Lass, Michael
AU - Mittendorf, Robert
AU - Löcke, Thomas
AU - Plessl, Christian
ID - 18
IS - 3
JF - ACM Transactions on Reconfigurable Technology and Systems (TRETS)
KW - coldboot
SN - 1936-7406
TI - Efficient Branch and Bound on FPGAs Using Work Stealing and Instance-Specific Designs
VL - 10
ER -
TY - CHAP
AB - Many modern compute nodes are heterogeneous multi-cores that integrate several CPU cores with fixed function or reconfigurable hardware cores. Such systems need to adapt task scheduling and mapping to optimise for performance and energy under varying workloads and, increasingly important, for thermal and fault management and are thus relevant targets for self-aware computing. In this chapter, we take up the generic reference architecture for designing self-aware and self-expressive computing systems and refine it for heterogeneous multi-cores. We present ReconOS, an architecture, programming model and execution environment for heterogeneous multi-cores, and show how the components of the reference architecture can be implemented on top of ReconOS. In particular, the unique feature of dynamic partial reconfiguration supports self-expression through starting and terminating reconfigurable hardware cores. We detail a case study that runs two applications on an architecture with one CPU and 12 reconfigurable hardware cores and present self-expression strategies for adapting under performance, temperature and even conflicting constraints. The case study demonstrates that the reference architecture as a model for self-aware computing is highly useful as it allows us to structure and simplify the design process, which will be essential for designing complex future compute nodes. Furthermore, ReconOS is used as a base technology for flexible protocol stacks in Chapter 10, an approach for self-aware computing at the networking level.
AU - Agne, Andreas
AU - Happe, Markus
AU - Lösch, Achim
AU - Plessl, Christian
AU - Platzner, Marco
ID - 156
T2 - Self-aware Computing Systems
TI - Self-aware Compute Nodes
ER -
TY - CONF
AB - The use of heterogeneous computing resources, such as Graphic Processing Units or other specialized coprocessors, has become widespread in recent years because of their per- formance and energy efficiency advantages. Approaches for managing and scheduling tasks to heterogeneous resources are still subject to research. Although queuing systems have recently been extended to support accelerator resources, a general solution that manages heterogeneous resources at the operating system- level to exploit a global view of the system state is still missing.In this paper we present a user space scheduler that enables task scheduling and migration on heterogeneous processing resources in Linux. Using run queues for available resources we perform scheduling decisions based on the system state and on task characterization from earlier measurements. With a pro- gramming pattern that supports the integration of checkpoints into applications, we preempt tasks and migrate them between three very different compute resources. Considering static and dynamic workload scenarios, we show that this approach can gain up to 17% performance, on average 7%, by effectively avoiding idle resources. We demonstrate that a work-conserving strategy without migration is no suitable alternative.
AU - Lösch, Achim
AU - Beisel, Tobias
AU - Kenter, Tobias
AU - Plessl, Christian
AU - Platzner, Marco
ID - 168
T2 - Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition (DATE)
TI - Performance-centric scheduling with task migration for a heterogeneous compute node in the data center
ER -
TY - CONF
AU - Kenter, Tobias
AU - Plessl, Christian
ID - 24
T2 - Proc. Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)
TI - Microdisk Cavity FDTD Simulation on FPGA using OpenCL
ER -
TY - CHAP
AB - In this chapter, we present an introduction to the ReconOS operating system for reconfigurable computing. ReconOS offers a unified multi-threaded programming model and operating system services for threads executing in software and threads mapped to reconfigurable hardware. By supporting standard POSIX operating system functions for both software and hardware threads, ReconOS particularly caters to developers with a software background, because developers can use well-known mechanisms such as semaphores, mutexes, condition variables, and message queues for developing hybrid applications with threads running on the CPU and FPGA concurrently. Through the semantic integration of hardware accelerators into a standard operating system environment, ReconOS allows for rapid design space exploration, supports a structured application development process and improves the portability of applications between different reconfigurable computing systems.
AU - Agne, Andreas
AU - Platzner, Marco
AU - Plessl, Christian
AU - Happe, Markus
AU - Lübbers, Enno
ED - Koch, Dirk
ED - Hannig, Frank
ED - Ziener, Daniel
ID - 29
SN - 978-3-319-26406-6
T2 - FPGAs for Software Programmers
TI - ReconOS
ER -
TY - CONF
AU - Riebler, Heinrich
AU - Vaz, Gavin Francis
AU - Plessl, Christian
AU - Trainiti, Ettore M. G.
AU - Durelli, Gianluca C.
AU - Bolchini, Cristiana
ID - 31
T2 - Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)
TI - Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems
ER -