@inproceedings{63758,
  abstract     = {{Resilient systems require monitoring and prediction of environmental and intrinsic conditions and the ability to adapt to changing circumstances to optimize the trade-off between performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. This paper presents the migration of TETRISC to the Rocket Chip SoC, which is freely scalable to the number of processors through parametrizable Chisel models. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis for the rapid prototyping of resilient, scalable architectures that are online configurable through software for different multicore and lock-step modes.}},
  author       = {{Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}},
  booktitle    = {{38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}},
  keywords     = {{RISC-V, Multicore, Fault Tolerant, TETRISC, Chisel, Chipyard}},
  location     = {{Potsdam}},
  title        = {{{Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations}}},
  year         = {{2026}},
}

@inproceedings{65595,
  abstract     = {{Resilient systems require monitoring and prediction of environmental and intrinsic conditions, as well as the ability to adapt to environmental hazards while optimizing the trade-off among performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. We introduce the migration of TETRISC to the open-source Rocket Chip SoC, targeting scalable TETRISC Chisel implementations. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis, enabling rapid prototyping of resilient, scalable architectures configurable for multicore and lockstep modes.}},
  author       = {{Hannemann, Kai Arne and Luchterhandt, Lars Markus and Müller, Wolfgang and Ulbricht, Markus and Lu, Li and Scheytt, J. Christoph}},
  booktitle    = {{29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)}},
  location     = {{Würzburg}},
  title        = {{{TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture}}},
  year         = {{2026}},
}

@inproceedings{58861,
  author       = {{Luchterhandt, Lars and Govindasamy, Vivek and Wang, Yutong and Dömer, Rainer and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{OSSMPIC - Open Source Solutions for Massively Parallel Integrated Circuits}},
  title        = {{{Case Study on Combining Open-Source Tool Flows for Grids of Processing Cells}}},
  year         = {{2025}},
}

@article{62148,
  author       = {{Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}},
  issn         = {{1063-8210}},
  journal      = {{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
  publisher    = {{IEEE}},
  title        = {{{60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}}},
  doi          = {{10.1109/TVLSI.2025.3625787}},
  year         = {{2025}},
}

@inproceedings{62126,
  author       = {{Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{IEEE Nordic Circuits and Systems Conference (NORCAS)}},
  location     = {{Riga, Latvia}},
  title        = {{{A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology}}},
  doi          = {{10.1109/NorCAS66540.2025.11231203}},
  year         = {{2025}},
}

@inproceedings{58856,
  author       = {{Hannemann, Kai Arne and Bütün, Hüseyin Berke and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{MBMV 2025 - 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen}},
  isbn         = {{978-3-8007-6515-7}},
  publisher    = {{VDE Verlag}},
  title        = {{{Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study}}},
  year         = {{2025}},
}

@inproceedings{53579,
  author       = {{Palomero Bernardo, Paul and Schmid, Patrick and Bringmann, Oliver and Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Koch, Andreas and Jentsch, Eyck and Sauer, Axel and Feldner, Ingo and Ecker, Wolfgang}},
  booktitle    = {{DATE 24 - Design Automation and Test in Europe}},
  location     = {{Valencia, Spain}},
  title        = {{{A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing}}},
  year         = {{2024}},
}

@inproceedings{45778,
  abstract     = {{RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple
RISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core
processors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells
(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.
This paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level
(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based
implementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This
work also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with
different local address spaces.}},
  author       = {{Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}},
  booktitle    = {{MBMV 2024 - 27. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“}},
  location     = {{Germany,  Freiburg}},
  publisher    = {{VDE Verlag}},
  title        = {{{Implementation of Different Communication Structures for a Rocket Chip Based RISC-V Grid of Processing Cells}}},
  year         = {{2024}},
}

@inproceedings{45776,
  author       = {{Ecker, Wolfgang and Krstic, Milos and Ulbricht, Markus and Mauderer, Andreas and Jentzsch, Eyck and Koch, Andreas and Koppelmann, Bastian and Müller, Wolfgang and Sadiye, Babak and Bruns, Niklas and Drechsler, Rolf and Müller-Gritschneder, Daniel and Schlamelcher, Jan and Grüttner, Kim and Bormann, Jörg and Kunz, Wolfgang and Heckmann, Reinhold and Angst, Gerhard and Wimmer, Ralf and Becker, Bernd and Faller, Tobias and Palomero Bernardo, Paul and Brinkmann, Oliver and Partzsch, Johannes and Mayr, Christian}},
  booktitle    = {{RISC-V Summit Europe 2023, Barcelona, Spain, June 2023.}},
  location     = {{ Barcelona, Spain,}},
  title        = {{{Scale4Edge – Scaling RISC-V for Edge Applications}}},
  year         = {{2023}},
}

@inproceedings{48530,
  author       = {{Müller, Wolfgang and Ulbricht, Markus and Li, Lu and Krstic, Milos}},
  booktitle    = {{5. ITG / GMM / GI -Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen }},
  location     = {{Erfurt. Germany}},
  title        = {{{Der TETRISC SoC - Ein resilientes Quad-Core System auf Pulpissimo-Basis}}},
  year         = {{2023}},
}

@inproceedings{48961,
  author       = {{Iftekhar, Mohammed and Gowda, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)}},
  location     = {{Monterey, CA, USA}},
  title        = {{{A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology}}},
  doi          = {{10.1109/BCICTS54660.2023.10310954}},
  year         = {{2023}},
}

@inproceedings{45775,
  abstract     = {{RISC-V has received worldwide acceptance in the industry and by the academic community. As of today, multiple
RISC-V applications and variants are under investigation for embedded IoT systems, from resource-limited single-core
processors up to multi-core systems for High-Performance Computing (HPC). Recently, the Grid of Processing Cells
(GPC) platform has been proposed as a scalable parallel grid-oriented network of processor cores with local memories.
This paper describes a prototype design of the GPC platform for hardware implementation at Register-Transfer Level
(RTL) based on modified RISC-V Rocket processors with scratchpad memories. It introduces a scalable Chisel-based
implementation of the modified Rocket cores with RTL generation and a functional test using Verilator simulation. This
work also includes the adaptation of the Chipyard software toolchain to extend the compiler to multi-core grids with
different local address spaces.}},
  author       = {{Luchterhandt, Lars and Nellius, Tom and Beck, Robert and Dömer, Rainer and Kneuper, Pascal and Müller, Wolfgang and Sadiye, Babak}},
  booktitle    = {{MBMV 2023 - 26. Workshop "Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen“, MBMV 2023, Freiburg}},
  location     = {{Freiburg}},
  publisher    = {{VDE Verlag}},
  title        = {{{Towards a Rocket Chip Based Implementation of the RISC-V GPC Architecture}}},
  year         = {{2023}},
}

@inproceedings{47064,
  author       = {{Iftekhar, Mohammed and Nagaraju, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium}},
  location     = {{MONTEREY, CALIFORNIA, USA}},
  title        = {{{A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology }}},
  year         = {{2023}},
}

@inproceedings{29302,
  abstract     = {{This paper introduces the project Scale4Edge. The project is focused on enabling an effective RISC-V ecosystem for optimization of edge applications. We describe the basic components of this ecosystem and introduce the envisioned
demonstrators, which will be used in their evaluation.}},
  author       = {{Ecker, Wolfgang and Adelt, Peer and Müller, Wolfgang and Heckmann, Reinhold and Krstic, Milos and Herdt, Vladimir and Drechsler, Rolf and Angst, Gerhard and Wimmer, Ralf and Mauderer, Andreas and Stahl, Rafael and Emrich, Karsten and Mueller-Gritschneder, Daniel and Becker, Bernd and Scholl, Philipp and Jentzsch, Eyck and Schlamelcher, Jan and Grüttner, Kim and Bernardo, Paul Palomero and Brinkmann, Oliver and Damian, Mihaela and Oppermann, Julian and Koch, Andreas and Bormann, Jörg and Partzsch, Johannes and Mayr, Christian and Kunz, Wolfgang}},
  booktitle    = {{In Proceedings of the Design Automation and Test Conference and Exhibition (DATE 2022)}},
  title        = {{{The Scale4Edge RISC-V Ecosystem}}},
  year         = {{2022}},
}

@inproceedings{32125,
  abstract     = {{Fault coverage analysis and fault simulation are well-established methods for the qualification of test vectors in hardware design. However, their role in virtual prototyping and the correlation to later steps in the design process need further investigation. We introduce a metric for RISC-V instruction and register coverage for binary software. The metric measures if RISC-V instruction types are executed and if GPRs, CSRs, and FPRs are accessed. The analysis is applied by the means of a virtual prototype which is based on an abstract instruction and register model with direct correspondence to their bit level representation. In this context, we analyzed three different openly available test suites: the RISC-V architectural testing framework, the RISC-V unit tests, and programs which are automatically generated by the RISC-V Torture test generator. We discuss their tradeoffs and show that by combining them to a unified test suite we can arrive at a 100% GPR and FPR register coverage and a 98.7% instruction type coverage.}},
  author       = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}},
  isbn         = {{978-3-8007-5500-4}},
  publisher    = {{VDE}},
  title        = {{{Register and Instruction Coverage Analysis for Different RISC-V ISA Modules}}},
  year         = {{2021}},
}

@inproceedings{32132,
  abstract     = {{Die Werkzeugdemonstration des QEMU Timing Analyzers (QTA) stellt eine Erweiterung des quelloffenen CPU Emulators QEMU zur Simulation von Softwareprogrammen und deren Worst-Case Zeitverhaltens vor, das durch eine statische Zeitanalyse vorher aus dem Softwareprogramm extrahiert wurde. Der Ablauf der Analyse gliedert sich in mehrere Schritte: Zunächst wird für das zu simulierende Binärprogramm eine WCET-Analyse mit aiT durchgeführt. Im Preprocessing des aiT-Reports wird daraufhin ein WCET-annotierter Kontrollflussgraph erzeugt. Dabei entsprechen die Knoten im Kontrollflussgraph den aiT-Blöcken und die Kanten dem jeweiligen Worst-Case-Zeitverbrauch, um das Programm im aktuellen Ausführungskontext vom Quell- bis zum Zielblock laufen zu lassen. Nach dem Preprocessing werden Binärprogramm und der zuvor erzeugte, zeitannotierte Kontrollflussgraph von QEMU geladen und gemeinsam simuliert.

Die Implementierung des QTA basiert auf der Standard TGI Plugin API (Tiny Code Generator Plugin API), die seit Ende 2019 mit QEMU V4.2 verfügbar ist. Dieses API erlaubt die Entwicklung von versionsunabhängigen QEMU-Erweiterungen. Die QEMU-QTA-Erweiterung wird zum Zeitpunkt der Werkzeugdemonstration inklusive des ait2qta-Preprozessors unter github.com im Quellcode frei verfügbar sein.

Die Demonstration geht von einer existierenden aiT-Analyse eines für TriCore© kompilierten binären Softwareprograms aus, erläutert das Kontrollflusszwischenformat und zeigt die zeitannotierte Simulation der Software.}},
  author       = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{MBMV 2021 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}},
  keywords     = {{QEMU, aiT, Zeitannotation, WCET}},
  publisher    = {{VDE}},
  title        = {{{QEMU zur Simulation von Worst-Case-Ausführungszeiten}}},
  year         = {{2021}},
}

@inproceedings{23992,
  author       = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2021)}},
  title        = {{{Register and Instruction Coverage Analysis for Different RISC-V ISA Modules}}},
  year         = {{2021}},
}

@inproceedings{24027,
  abstract     = {{Fault effect simulation is a well-established technique for the qualification of robust embedded software and hardware as required by different safety standards. Our article introduces a Virtual Prototype based approach for the fault analysis and fast simulation of a set of automatically generated and target compiled software programs. The approach scales to different RISC-V ISA standard subset configurations and is based on an instruction and hardware register coverage for automatic fault injections of permanent and transient bitflips. The analysis of each software binary evaluates its opcode type and register access coverage including the addressed memory space. Based on this information dedicated sets of fault injected hardware models, i.e., mutants, are generated. The simulation of all mutants conducted with the different binaries finally identifies the cases with a normal termination though executed on a faulty hardware model. They are identified as a subject for further investigations and improvements by the implementation of additional hardware or software safety countermeasures. Our final evaluation results with automatic C code generation, compilation, analysis, and simulation show that QEMU provides an adequate efficient platform, which also scales to more complex scenarios.}},
  author       = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{MBMV 2020 - Methods and Description Languages for Modelling and Verification of Circuits and Systems; GMM/ITG/GI-Workshop}},
  title        = {{{A Scalable Platform for QEMU Based Fault Effect Analysis for RISC-V Hardware Architectures}}},
  year         = {{2020}},
}

@inproceedings{24058,
  abstract     = {{Embedded systems require a high energy efficiency in combination with an optimized performance. As such, Bit Manipulation Instructions (BMIs) were introduced for x86 and ARMv8 to improve the runtime efficiency and power dissipation of the compiled software for various applications. Though the RISC-V platform is meanwhile widely accepted for embedded systems application, its instruction set architecture (ISA) currently still supports only two basic BMIs.We introduce ten advanced BMIs for the RISC-V ISA and implemented them on Berkeley's Rocket CPU [1], which we synthesized for the Artix-7 FPGA and the TSMC 65nm cell library. Our RISC-V BMI definitions are based on an analysis and combination of existing x86 and ARMv8 BMIs. Our Rocket CPU hardware extensions show that RISC-V BMI extensions have no negative impact on the critical path of the execution pipeline. Our software evaluations show that we can, for example, expect a significant impact for time and power consuming cryptographic applications.}},
  author       = {{Koppelmann, Bastian and Adelt, Peer and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{29th International Symposium on Power and Timing Modeling, Optimization and Simulation (PATMOS)}},
  title        = {{{RISC-V Extensions for Bit Manipulation Instructions}}},
  doi          = {{10.1109/PATMOS.2019.8862170}},
  year         = {{2019}},
}

@inproceedings{24060,
  abstract     = {{In diesem Artikel stellen wir eine Methode zur nicht-invasiven dynamischen Speicher- und IO-Analyse mit QEMU für sicherheitskritische eingebettete Software für die RISC-V Befehlssatzarchitektur vor. Die Implementierung basiert auf einer Erweiterung des Tiny Code Generator (TCG) des quelloffenen CPU-Emulators QEMU um die dynamische Identifikation von Zugriffen auf Datenspeicher sowie auf an die CPU angeschlossene IO-Geräte. Wir demonstrieren die Funktionalität der Methode anhand eines Versuchsaufbaus, bei dem eine Schließsystemkontrolle mittels serieller UART-Schnittstelle an einen RISC-V-Prozessor angebunden ist. Dieses Szenario zeigt, dass ein unberechtigter Zugriff auf die UART-Schnittstelle frühzeitig aufgedeckt und ein Angriff auf eine Zugangskontrolle somit endeckt werden kann. }},
  author       = {{Adelt, Peer and Koppelmann, Bastian and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{MBMV 2019-22.Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2019)}},
  isbn         = {{978-3-8007-4945-4}},
  title        = {{{Analyse sicherheitskritischer Software für RISC-V Prozessoren}}},
  year         = {{2019}},
}