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Wunderlich, in: 2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W), IEEE, 2023."},"type":"conference","language":[{"iso":"eng"}],"doi":"10.1109/dsn-w58399.2023.00056","date_updated":"2023-08-26T10:49:07Z","_id":"46739","publication_status":"published","status":"public","date_created":"2023-08-26T10:48:31Z","publisher":"IEEE","author":[{"id":"78614","last_name":"Sadeghi-Kohan","full_name":"Sadeghi-Kohan, Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","first_name":"Somayeh"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","id":"209"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"publication":"2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W)","department":[{"_id":"48"}],"title":"Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication","user_id":"78614"},{"language":[{"iso":"eng"}],"year":"2023","citation":{"ieee":"S. Sadeghi-Kohan, J. D. Reimer, S. Hellebrand, and H.-J. Wunderlich, “Optimizing the Streaming of Sensor Data with Approximate Communication,” presented at the IEEE Asian Test Symposium (ATS’23), 2023.","short":"S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, in: IEEE Asian Test Symposium (ATS’23), October 2023, Beijing, China, 2023.","mla":"Sadeghi-Kohan, Somayeh, et al. “Optimizing the Streaming of Sensor Data with Approximate Communication.” IEEE Asian Test Symposium (ATS’23), October 2023, 2023.","bibtex":"@inproceedings{Sadeghi-Kohan_Reimer_Hellebrand_Wunderlich_2023, place={Beijing, China}, title={Optimizing the Streaming of Sensor Data with Approximate Communication}, booktitle={IEEE Asian Test Symposium (ATS’23), October 2023}, author={Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }","apa":"Sadeghi-Kohan, S., Reimer, J. D., Hellebrand, S., & Wunderlich, H.-J. (2023). Optimizing the Streaming of Sensor Data with Approximate Communication. IEEE Asian Test Symposium (ATS’23), October 2023. IEEE Asian Test Symposium (ATS’23).","ama":"Sadeghi-Kohan S, Reimer JD, Hellebrand S, Wunderlich H-J. Optimizing the Streaming of Sensor Data with Approximate Communication. In: IEEE Asian Test Symposium (ATS’23), October 2023. ; 2023.","chicago":"Sadeghi-Kohan, Somayeh, Jan Dennis Reimer, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Optimizing the Streaming of Sensor Data with Approximate Communication.” In IEEE Asian Test Symposium (ATS’23), October 2023. Beijing, China, 2023."},"type":"conference","conference":{"name":"IEEE Asian Test Symposium (ATS'23)","start_date":"2023-10-14","end_date":"2023-10-17"},"_id":"46738","date_updated":"2024-01-08T08:49:08Z","publication":"IEEE Asian Test Symposium (ATS'23), October 2023","department":[{"_id":"48"}],"author":[{"last_name":"Sadeghi-Kohan","id":"78614","first_name":"Somayeh","orcid":"https://orcid.org/0000-0001-7246-0610","full_name":"Sadeghi-Kohan, Somayeh"},{"id":"36703","last_name":"Reimer","full_name":"Reimer, Jan Dennis","first_name":"Jan Dennis"},{"orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","first_name":"Sybille","id":"209","last_name":"Hellebrand"},{"first_name":"Hans-Joachim","full_name":"Wunderlich, Hans-Joachim","last_name":"Wunderlich"}],"date_created":"2023-08-26T08:47:52Z","status":"public","place":"Beijing, China","user_id":"36703","title":"Optimizing the Streaming of Sensor Data with Approximate Communication"},{"_id":"46264","main_file_link":[{"url":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10194315"}],"year":"2023","type":"journal_article","citation":{"ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Workload-Aware Periodic Interconnect BIST,” IEEE Design &Test, pp. 1–1, 2023, doi: 10.1109/mdat.2023.3298849.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, IEEE Design &Test (2023) 1–1.","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2023, title={Workload-Aware Periodic Interconnect BIST}, DOI={10.1109/mdat.2023.3298849}, journal={IEEE Design &Test}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023}, pages={1–1} }","mla":"Sadeghi-Kohan, Somayeh, et al. “Workload-Aware Periodic Interconnect BIST.” IEEE Design &Test, Institute of Electrical and Electronics Engineers (IEEE), 2023, pp. 1–1, doi:10.1109/mdat.2023.3298849.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Workload-Aware Periodic Interconnect BIST.” IEEE Design &Test, 2023, 1–1. https://doi.org/10.1109/mdat.2023.3298849.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Workload-Aware Periodic Interconnect BIST. IEEE Design &Test. Published online 2023:1-1. doi:10.1109/mdat.2023.3298849","apa":"Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2023). Workload-Aware Periodic Interconnect BIST. IEEE Design &Test, 1–1. https://doi.org/10.1109/mdat.2023.3298849"},"page":"1-1","article_type":"original","abstract":[{"text":"System-level interconnects provide the\r\nbackbone for increasingly complex systems on a chip. Their\r\nvulnerability to electromigration and crosstalk can lead to\r\nserious reliability and safety issues during the system lifetime.\r\nThis article presents an approach for periodic in-system testing\r\nwhich maintains a reliability profile to detect potential\r\nproblems before they actually cause a failure. Relying on a\r\ncommon infrastructure for EM-aware system workload\r\nmanagement and test, it minimizes the stress induced by the\r\ntest itself and contributes to the self-healing of system-induced\r\nelectromigration degradations. ","lang":"eng"}],"user_id":"209","author":[{"id":"78614","last_name":"Sadeghi-Kohan","orcid":"https://orcid.org/0000-0001-7246-0610","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh"},{"last_name":"Hellebrand","id":"209","first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","publication":"IEEE Design &Test","keyword":["Electrical and Electronic Engineering","Hardware and Architecture","Software"],"status":"public","date_created":"2023-08-02T11:07:43Z","date_updated":"2024-03-22T17:15:10Z","doi":"10.1109/mdat.2023.3298849","language":[{"iso":"eng"}],"title":"Workload-Aware Periodic Interconnect BIST","department":[{"_id":"48"}],"publication_status":"published","publication_identifier":{"issn":["2168-2356","2168-2364"]}},{"place":"Anaheim, CA, USA","title":"Robust Pattern Generation for Small Delay Faults under Process Variations","user_id":"209","publisher":"IEEE","author":[{"first_name":"Hanieh","full_name":"Jafarzadeh, Hanieh","last_name":"Jafarzadeh"},{"last_name":"Klemme","first_name":"Florian","full_name":"Klemme, Florian"},{"id":"36703","last_name":"Reimer","full_name":"Reimer, Jan Dennis","first_name":"Jan Dennis"},{"full_name":"Najafi Haghi, Zahra Paria","first_name":"Zahra Paria","last_name":"Najafi Haghi"},{"last_name":" Amrouch","first_name":"Hussam","full_name":" Amrouch, Hussam"},{"id":"209","last_name":"Hellebrand","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"last_name":" Wunderlich","full_name":" Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"department":[{"_id":"48"}],"publication":"IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023","publication_status":"published","status":"public","date_created":"2023-07-03T08:20:17Z","date_updated":"2024-03-22T17:14:02Z","_id":"45830","conference":{"location":"Anaheim, USA","start_date":"2023-10-08","name":"IEEE International Test Conference (ITC'23)","end_date":"2023-10-13"},"year":"2023","type":"conference","citation":{"bibtex":"@inproceedings{Jafarzadeh_Klemme_Reimer_Najafi Haghi_ Amrouch_Hellebrand_ Wunderlich_2023, place={Anaheim, CA, USA}, title={Robust Pattern Generation for Small Delay Faults under Process Variations}, booktitle={IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023}, publisher={IEEE}, author={Jafarzadeh, Hanieh and Klemme, Florian and Reimer, Jan Dennis and Najafi Haghi, Zahra Paria and Amrouch, Hussam and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2023} }","mla":"Jafarzadeh, Hanieh, et al. “Robust Pattern Generation for Small Delay Faults under Process Variations.” IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, 2023.","chicago":"Jafarzadeh, Hanieh, Florian Klemme, Jan Dennis Reimer, Zahra Paria Najafi Haghi, Hussam Amrouch, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Robust Pattern Generation for Small Delay Faults under Process Variations.” In IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. Anaheim, CA, USA: IEEE, 2023.","ama":"Jafarzadeh H, Klemme F, Reimer JD, et al. Robust Pattern Generation for Small Delay Faults under Process Variations. In: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE; 2023.","apa":"Jafarzadeh, H., Klemme, F., Reimer, J. D., Najafi Haghi, Z. P., Amrouch, H., Hellebrand, S., & Wunderlich, H.-J. (2023). Robust Pattern Generation for Small Delay Faults under Process Variations. IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023. IEEE International Test Conference (ITC’23), Anaheim, USA.","ieee":"H. Jafarzadeh et al., “Robust Pattern Generation for Small Delay Faults under Process Variations,” presented at the IEEE International Test Conference (ITC’23), Anaheim, USA, 2023.","short":"H. Jafarzadeh, F. Klemme, J.D. Reimer, Z.P. Najafi Haghi, H. Amrouch, S. Hellebrand, H.-J. Wunderlich, in: IEEE International Test Conference (ITC’23), Anaheim, USA, October 2023, IEEE, Anaheim, CA, USA, 2023."},"language":[{"iso":"eng"}]},{"status":"public","date_created":"2022-01-14T11:16:34Z","publication_status":"published","publication_identifier":{"issn":["0923-8174","1573-0727"]},"author":[{"id":"78614","last_name":"Sadeghi-Kohan","full_name":"Sadeghi-Kohan, Somayeh","first_name":"Somayeh"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","id":"209"},{"full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim","last_name":"Wunderlich"}],"publisher":"Springer Science and Business Media LLC","department":[{"_id":"48"}],"publication":"Journal of Electronic Testing","keyword":["Electrical and Electronic Engineering"],"user_id":"209","title":"Stress-Aware Periodic Test of Interconnects","article_type":"original","abstract":[{"text":"Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.","lang":"eng"}],"language":[{"iso":"eng"}],"year":"2022","type":"journal_article","citation":{"short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, Journal of Electronic Testing (2022).","ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, “Stress-Aware Periodic Test of Interconnects,” Journal of Electronic Testing, 2022, doi: 10.1007/s10836-021-05979-5.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. “Stress-Aware Periodic Test of Interconnects.” Journal of Electronic Testing, 2022. https://doi.org/10.1007/s10836-021-05979-5.","apa":"Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. https://doi.org/10.1007/s10836-021-05979-5","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. Stress-Aware Periodic Test of Interconnects. Journal of Electronic Testing. Published online 2022. doi:10.1007/s10836-021-05979-5","mla":"Sadeghi-Kohan, Somayeh, et al. “Stress-Aware Periodic Test of Interconnects.” Journal of Electronic Testing, Springer Science and Business Media LLC, 2022, doi:10.1007/s10836-021-05979-5.","bibtex":"@article{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, title={Stress-Aware Periodic Test of Interconnects}, DOI={10.1007/s10836-021-05979-5}, journal={Journal of Electronic Testing}, publisher={Springer Science and Business Media LLC}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }"},"doi":"10.1007/s10836-021-05979-5","date_updated":"2022-05-11T16:10:01Z","_id":"29351"},{"place":"Online","user_id":"209","title":"EM-Aware Interconnect BIST","publisher":"European Workshop on Silicon Lifecycle Management, March 18, 2022","author":[{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","id":"78614"},{"last_name":"Hellebrand","id":"209","first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille"},{"last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim","first_name":"Hans-Joachim"}],"department":[{"_id":"48"}],"keyword":["WORKSHOP"],"status":"public","date_created":"2022-02-19T14:21:24Z","publication_status":"published","date_updated":"2022-05-11T17:07:24Z","_id":"29890","language":[{"iso":"eng"}],"citation":{"ieee":"S. Sadeghi-Kohan, S. Hellebrand, and H.-J. Wunderlich, EM-Aware Interconnect BIST. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","short":"S. Sadeghi-Kohan, S. Hellebrand, H.-J. Wunderlich, EM-Aware Interconnect BIST, European Workshop on Silicon Lifecycle Management, March 18, 2022, Online, 2022.","bibtex":"@book{Sadeghi-Kohan_Hellebrand_Wunderlich_2022, place={Online}, title={EM-Aware Interconnect BIST}, publisher={European Workshop on Silicon Lifecycle Management, March 18, 2022}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille and Wunderlich, Hans-Joachim}, year={2022} }","mla":"Sadeghi-Kohan, Somayeh, et al. EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","chicago":"Sadeghi-Kohan, Somayeh, Sybille Hellebrand, and Hans-Joachim Wunderlich. EM-Aware Interconnect BIST. Online: European Workshop on Silicon Lifecycle Management, March 18, 2022, 2022.","ama":"Sadeghi-Kohan S, Hellebrand S, Wunderlich H-J. EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022; 2022.","apa":"Sadeghi-Kohan, S., Hellebrand, S., & Wunderlich, H.-J. (2022). EM-Aware Interconnect BIST. European Workshop on Silicon Lifecycle Management, March 18, 2022."},"year":"2022","type":"misc","page":"2"},{"type":"conference","citation":{"ieee":"A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.","short":"A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.","mla":"Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, 2020.","bibtex":"@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2020} }","chicago":"Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” In IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. Virtual Conference - Originally Frascati (Rome), Italy, 2020.","ama":"Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020. ; 2020.","apa":"Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020."},"year":"2020","language":[{"iso":"eng"}],"conference":{"end_date":"2020-10-21","start_date":"2020-10-19"},"_id":"19422","date_updated":"2022-02-19T14:16:58Z","publication_status":"published","date_created":"2020-09-15T14:03:02Z","status":"public","publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020","department":[{"_id":"48"}],"author":[{"id":"22707","last_name":"Sprenger","full_name":"Sprenger, Alexander","first_name":"Alexander"},{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","id":"78614"},{"last_name":"Reimer","id":"36703","first_name":"Jan Dennis","full_name":"Reimer, Jan Dennis"},{"last_name":"Hellebrand","id":"209","first_name":"Sybille","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939"}],"title":"Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study","user_id":"209","place":"Virtual Conference - Originally Frascati (Rome), Italy"},{"place":"Ludwigsburg","title":"Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects","user_id":"209","publisher":"32. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'20), 16. - 18. Februar 2020","author":[{"first_name":"Somayeh","full_name":"Sadeghi-Kohan, Somayeh","last_name":"Sadeghi-Kohan","id":"78614"},{"first_name":"Sybille","orcid":"0000-0002-3717-3939","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","id":"209"}],"department":[{"_id":"48"}],"keyword":["WORKSHOP"],"publication_status":"published","status":"public","date_created":"2019-12-29T16:13:58Z","date_updated":"2022-04-04T12:30:02Z","_id":"15419","type":"misc","citation":{"chicago":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. Ludwigsburg: 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","ama":"Sadeghi-Kohan S, Hellebrand S. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020; 2020.","apa":"Sadeghi-Kohan, S., & Hellebrand, S. (2020). Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020.","bibtex":"@book{Sadeghi-Kohan_Hellebrand_2020, place={Ludwigsburg}, title={Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects}, publisher={32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020}, author={Sadeghi-Kohan, Somayeh and Hellebrand, Sybille}, year={2020} }","mla":"Sadeghi-Kohan, Somayeh, and Sybille Hellebrand. Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects. 32. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’20), 16. - 18. Februar 2020, 2020.","short":"S. Sadeghi-Kohan, S. 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