Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations - Jafarzadeh, Hanieh; Klemme, Florian; Amrouch, Hussam; Hellebrand, Sybille; Wunderlich, Hans-Joachim (European Test Symposium, The Hague, Netherlands, May 20-24, 2024)

Vmin Testing under Variations: Defect vs. Fault Coverage - Jafarzadeh, Hanieh; Klemme, Florian; Amrouch, Hussam; Hellebrand, Sybille; Wunderlich, Hans-Joachim (IEEE Latin American Test Symposium (LATS), Maceió, Brazil, April 9-12, 2024)

Functional Safety and Reliability of Interconnects throughout the Silicon Life Cycle - Hellebrand, Sybille; Sadeghi-Kohan, Somayeh; Wunderlich, Hans-Joachim (International Symposium of EDA (ISEDA), Xi'an, China, May 10-13, 2024)

Robust Test of Small Delay Faults under PVT-Variations - Wunderlich, Hans-Joachim; Jafarzadeh, Hanieh; Hellebrand, Sybille (International Symposium of EDA (ISEDA), Xi’an, China, May 10-13, 2024)

Modeling Crosstalk-induced Interconnect Delay with Polynomial Regression - Stiballe, Alisa; Reimer, Jan Dennis; Sadeghi-Kohan, Somayeh; Hellebrand, Sybille

Crosstalk-Aware Simulation of Interconnects Using Artificial Neural Networks - Ustimova, Magdalina; Sadeghi-Kohan, Somayeh; Hellebrand, Sybille

Minimizing PVT-Variability by Exploiting the Zero Temperature Coefficient (ZTC) for Robust Delay Fault Testing - Jafarzadeh, Hanieh; Klemme, Florian; Reimer, Jan Dennis; Amrouch, Hussam; Hellebrand, Sybille; Wunderlich, Hans-Joachim (In: IEEE International Test Conference (ITC'24), San Diego, CA, USA, November 2024)

Optimizing the Streaming of Sensor Data with Approximate Communication - Sadeghi-Kohan, Somayeh; Reimer, Jan Dennis; Hellebrand, Sybille; Wunderlich, Hans-Joachim (IEEE Asian Test Symposium (ATS'23), October 2023)

Workload-Aware Periodic Interconnect BIST - Sadeghi-Kohan, Somayeh; Hellebrand, Sybille; Wunderlich, Hans-Joachim (IEEE Design &Test)
System-level interconnects provide the backbone for increasingly complex systems on a chip. Their vulnerability to electromigration and crosstalk can lead to serious reliability and safety issues during the system lifetime. This article presents an approach for periodic in-system testing which maintains a reliability profile to detect potential problems before they actually cause a failure. Relying on a common infrastructure for EM-aware system workload management and test, it minimizes the stress induced by the test itself and contributes to the self-healing of system-induced electromigration degradations.
Keywords: Electrical and Electronic Engineering; Hardware and Architecture; Software

Robust Pattern Generation for Small Delay Faults under Process Variations - Jafarzadeh, Hanieh; Klemme, Florian; Reimer, Jan Dennis; Najafi Haghi, Zahra Paria; Amrouch, Hussam; Hellebrand, Sybille; Wunderlich, Hans-Joachim (IEEE International Test Conference (ITC'23), Anaheim, USA, October 2023)

On Cryptography Effects on Interconnect Reliability - Ghazal, Abdulkarim; Sadeghi-Kohan, Somayeh; Reimer, Jan Dennis; Hellebrand, Sybille
Keywords: WORKSHOP

Approximate Computing: Balancing Performance, Power, Reliability, and Safety - Badran, Abdalrhman; Sadeghi-Kohan, Somayeh; Reimer, Jan Dennis; Hellebrand, Sybille (28th IEEE European Test Symposium (ETS'23), May 2023)

Low Power Streaming of Sensor Data Using Gray Code-Based Approximate Communication - Sadeghi-Kohan, Somayeh; Hellebrand, Sybille; Wunderlich, Hans-Joachim (2023 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W))

Stress-Aware Periodic Test of Interconnects - Sadeghi-Kohan, Somayeh; Hellebrand, Sybille; Wunderlich, Hans-Joachim (Journal of Electronic Testing)
Safety-critical systems have to follow extremely high dependability requirements as specified in the standards for automotive, air, and space applications. The required high fault coverage at runtime is usually obtained by a combination of concurrent error detection or correction and periodic tests within rather short time intervals. The concurrent scheme ensures the integrity of computed results while the periodic test has to identify potential aging problems and to prevent any fault accumulation which may invalidate the concurrent error detection mechanism. Such periodic built-in self-test (BIST) schemes are already commercialized for memories and for random logic. The paper at hand extends this approach to interconnect structures. A BIST scheme is presented which targets interconnect defects before they will actually affect the system functionality at nominal speed. A BIST schedule is developed which significantly reduces aging caused by electromigration during the lifetime application of the periodic test.
Keywords: Electrical and Electronic Engineering

EM-Aware Interconnect BIST - Sadeghi-Kohan, Somayeh; Hellebrand, Sybille; Wunderlich, Hans-Joachim
Keywords: WORKSHOP

Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study - Sprenger, Alexander; Sadeghi-Kohan, Somayeh; Reimer, Jan Dennis; Hellebrand, Sybille (IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020)

Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects - Sadeghi-Kohan, Somayeh; Hellebrand, Sybille
Keywords: WORKSHOP

Dynamic Multi-Frequency Test Method for Hidden Interconnect Defects - Sadeghi-Kohan, Somayeh; Hellebrand, Sybille (38th IEEE VLSI Test Symposium (VTS))

Logic Fault Diagnosis of Hidden Delay Defects - Holst, Stefan; Kampmann, Matthias; Sprenger, Alexander; Reimer, Jan Dennis; Hellebrand, Sybille; Wunderlich, Hans-Joachim; Weng, Xiaoqing (IEEE International Test Conference (ITC'20), November 2020)

A Hybrid Space Compactor for Varying X-Rates - Maaz, Mohammad Urf; Sprenger, Alexander; Hellebrand, Sybille
Keywords: WORKSHOP