@phdthesis{46482,
  abstract     = {{Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem.
With modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates.
To deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty.}},
  author       = {{Sprenger, Alexander}},
  keywords     = {{Testantwortkompaktierung, Prozessvariation, Silicon Lifecycle Management}},
  pages        = {{xi, 160}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}}},
  doi          = {{10.17619/UNIPB/1-1787}},
  year         = {{2023}},
}

@inproceedings{19422,
  author       = {{Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}},
  booktitle    = {{IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}},
  title        = {{{Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}}},
  year         = {{2020}},
}

@inproceedings{19421,
  author       = {{Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}},
  booktitle    = {{IEEE International Test Conference (ITC'20), November 2020}},
  title        = {{{Logic Fault Diagnosis of Hidden Delay Defects}}},
  year         = {{2020}},
}

@misc{8112,
  author       = {{Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}},
  keywords     = {{WORKSHOP}},
  publisher    = {{31. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'19)}},
  title        = {{{A Hybrid Space Compactor for Varying X-Rates}}},
  year         = {{2019}},
}

@article{8667,
  author       = {{Sprenger, Alexander and Hellebrand, Sybille}},
  issn         = {{0218-1266}},
  journal      = {{Journal of Circuits, Systems and Computers}},
  number       = {{1}},
  pages        = {{1--23}},
  publisher    = {{World Scientific Publishing Company}},
  title        = {{{Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test}}},
  doi          = {{10.1142/s0218126619400012}},
  volume       = {{28}},
  year         = {{2019}},
}

@inproceedings{12918,
  abstract     = {{The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. }},
  author       = {{Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}},
  booktitle    = {{50th IEEE International Test Conference (ITC)}},
  keywords     = {{Faster-than-at-speed test, BIST, DFT, Test response compaction, Stochastic compactor, X-handling}},
  location     = {{Washington, DC, USA}},
  pages        = {{1--8}},
  publisher    = {{IEEE}},
  title        = {{{A Hybrid Space Compactor for Adaptive X-Handling}}},
  year         = {{2019}},
}

@misc{4576,
  author       = {{Sprenger, Alexander and Hellebrand, Sybille}},
  keywords     = {{WORKSHOP}},
  publisher    = {{30. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen" (TuZ'18)}},
  title        = {{{Stochastische Kompaktierung für den Hochgeschwindigkeitstest}}},
  year         = {{2018}},
}

@inproceedings{4575,
  author       = {{Sprenger, Alexander and Hellebrand, Sybille}},
  booktitle    = {{2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)}},
  isbn         = {{9781538657546}},
  publisher    = {{IEEE}},
  title        = {{{Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}}},
  doi          = {{10.1109/ddecs.2018.00020}},
  year         = {{2018}},
}