[{"supervisor":[{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"},{"first_name":"Marco","last_name":"Platzner","full_name":"Platzner, Marco","id":"398"}],"author":[{"orcid":"0000-0002-0775-7677","last_name":"Sprenger","full_name":"Sprenger, Alexander","id":"22707","first_name":"Alexander"}],"date_updated":"2023-08-12T09:13:18Z","oa":"1","doi":"10.17619/UNIPB/1-1787","main_file_link":[{"open_access":"1","url":"https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493"}],"publication_status":"published","page":"xi, 160","citation":{"ama":"Sprenger A. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn; 2023. doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>","chicago":"Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität Paderborn, 2023. <a href=\"https://doi.org/10.17619/UNIPB/1-1787\">https://doi.org/10.17619/UNIPB/1-1787</a>.","ieee":"A. Sprenger, <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Paderborn: Universität Paderborn, 2023.","mla":"Sprenger, Alexander. <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn, 2023, doi:<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>.","short":"A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn, 2023.","bibtex":"@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen}, DOI={<a href=\"https://doi.org/10.17619/UNIPB/1-1787\">10.17619/UNIPB/1-1787</a>}, publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }","apa":"Sprenger, A. (2023). <i>Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen</i>. Universität Paderborn. <a href=\"https://doi.org/10.17619/UNIPB/1-1787\">https://doi.org/10.17619/UNIPB/1-1787</a>"},"place":"Paderborn","department":[{"_id":"48"}],"user_id":"22707","_id":"46482","extern":"1","type":"dissertation","status":"public","date_created":"2023-08-12T09:10:38Z","publisher":"Universität Paderborn","title":"Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen","year":"2023","language":[{"iso":"ger"}],"keyword":["Testantwortkompaktierung","Prozessvariation","Silicon Lifecycle Management"],"abstract":[{"text":"Ever increasing demands on the performance of microchips are leading to ever more complex semiconductor technologies with ever shrinking feature sizes. Complex applications with high demands on safety and reliability, such as autonomous driving, are simultaneously driving the requirements for test and diagnosis of VLSI circuits. Throughout the life cycle of a microchip, uncertainties occur that affect its timing behavior. For example, weak circuit structures, aging effects, or process variations can lead to a change in the timing behavior of the circuit. While these uncertainties do not necessarily lead to a change of the functional behavior, they can lead to a reliability problem.\r\nWith modular and hybrid compaction two test instruments are presented in this work that can be used for X-tolerant test response compaction in the built-in Faster-than-At-Speed Test (FAST) which is used to detect uncertainties in VLSI circuits. One challenge for test response compaction during FAST is the high and varying X-rate at the outputs of the circuit under test. By dividing the circuit outputs into test groups and separately compacting these test groups using stochastic compactors, the modular compaction is able to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic interconnects, a method for distinguishing crosstalk and process variation is presented. In current semiconductor technologies, the number of parasitic coupling capacitances between logic interconnects is growing. These coupling capacitances can lead to crosstalk, which causes increased current flow in the logic interconnects, which in turn can lead to increased electromigration. In the presented method, delay maps describing the timing behavior of the circuit outputs at different operating points are used to train artificial neural networks which classify the tested circuits into fault-free and faulty.","lang":"eng"},{"text":"Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei und fehlerhaft zu klassifizieren.","lang":"ger"}]},{"status":"public","type":"conference","publication":"IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020","language":[{"iso":"eng"}],"user_id":"209","department":[{"_id":"48"}],"_id":"19422","citation":{"bibtex":"@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer, Jan Dennis and Hellebrand, Sybille}, year={2020} }","short":"A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.","mla":"Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>, 2020.","apa":"Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., &#38; Hellebrand, S. (2020). Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>.","ieee":"A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.","chicago":"Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks - A Case Study.” In <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. Virtual Conference - Originally Frascati (Rome), Italy, 2020.","ama":"Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study. In: <i>IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020</i>. ; 2020."},"year":"2020","place":"Virtual Conference - Originally Frascati (Rome), Italy","publication_status":"published","conference":{"end_date":"2020-10-21","start_date":"2020-10-19"},"title":"Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study","author":[{"first_name":"Alexander","full_name":"Sprenger, Alexander","id":"22707","last_name":"Sprenger"},{"last_name":"Sadeghi-Kohan","full_name":"Sadeghi-Kohan, Somayeh","id":"78614","first_name":"Somayeh"},{"id":"36703","full_name":"Reimer, Jan Dennis","last_name":"Reimer","first_name":"Jan Dennis"},{"last_name":"Hellebrand","orcid":"0000-0002-3717-3939","id":"209","full_name":"Hellebrand, Sybille","first_name":"Sybille"}],"date_created":"2020-09-15T14:03:02Z","date_updated":"2022-02-19T14:16:58Z"},{"date_updated":"2022-05-11T17:08:20Z","author":[{"last_name":"Holst","full_name":"Holst, Stefan","first_name":"Stefan"},{"last_name":"Kampmann","full_name":"Kampmann, Matthias","id":"10935","first_name":"Matthias"},{"last_name":"Sprenger","id":"22707","full_name":"Sprenger, Alexander","first_name":"Alexander"},{"first_name":"Jan Dennis","full_name":"Reimer, Jan Dennis","id":"36703","last_name":"Reimer"},{"id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"},{"first_name":"Hans-Joachim","last_name":"Wunderlich","full_name":"Wunderlich, Hans-Joachim"},{"full_name":"Weng, Xiaoqing","last_name":"Weng","first_name":"Xiaoqing"}],"date_created":"2020-09-15T13:56:08Z","title":"Logic Fault Diagnosis of Hidden Delay Defects","publication_status":"published","year":"2020","place":"Virtual Conference - Originally Washington, DC, USA","citation":{"bibtex":"@inproceedings{Holst_Kampmann_Sprenger_Reimer_Hellebrand_Wunderlich_Weng_2020, place={Virtual Conference - Originally Washington, DC, USA}, title={Logic Fault Diagnosis of Hidden Delay Defects}, booktitle={IEEE International Test Conference (ITC’20), November 2020}, author={Holst, Stefan and Kampmann, Matthias and Sprenger, Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim and Weng, Xiaoqing}, year={2020} }","short":"S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich, X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual Conference - Originally Washington, DC, USA, 2020.","mla":"Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” <i>IEEE International Test Conference (ITC’20), November 2020</i>, 2020.","apa":"Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich, H.-J., &#38; Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. <i>IEEE International Test Conference (ITC’20), November 2020</i>.","ama":"Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay Defects. In: <i>IEEE International Test Conference (ITC’20), November 2020</i>. ; 2020.","chicago":"Holst, Stefan, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer, Sybille Hellebrand, Hans-Joachim Wunderlich, and Xiaoqing Weng. “Logic Fault Diagnosis of Hidden Delay Defects.” In <i>IEEE International Test Conference (ITC’20), November 2020</i>. Virtual Conference - Originally Washington, DC, USA, 2020.","ieee":"S. Holst <i>et al.</i>, “Logic Fault Diagnosis of Hidden Delay Defects,” 2020."},"_id":"19421","department":[{"_id":"48"}],"user_id":"209","language":[{"iso":"eng"}],"publication":"IEEE International Test Conference (ITC'20), November 2020","type":"conference","status":"public"},{"citation":{"apa":"Maaz, M. U., Sprenger, A., &#38; Hellebrand, S. (2019). <i>A Hybrid Space Compactor for Varying X-Rates</i>. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).","short":"M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), Prien am Chiemsee, 2019.","bibtex":"@book{Maaz_Sprenger_Hellebrand_2019, place={Prien am Chiemsee}, title={A Hybrid Space Compactor for Varying X-Rates}, publisher={31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19)}, author={Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019} }","mla":"Maaz, Mohammad Urf, et al. <i>A Hybrid Space Compactor for Varying X-Rates</i>. 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019.","ama":"Maaz MU, Sprenger A, Hellebrand S. <i>A Hybrid Space Compactor for Varying X-Rates</i>. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19); 2019.","ieee":"M. U. Maaz, A. Sprenger, and S. Hellebrand, <i>A Hybrid Space Compactor for Varying X-Rates</i>. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019.","chicago":"Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. <i>A Hybrid Space Compactor for Varying X-Rates</i>. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019."},"place":"Prien am Chiemsee","year":"2019","title":"A Hybrid Space Compactor for Varying X-Rates","author":[{"first_name":"Mohammad Urf","last_name":"Maaz","full_name":"Maaz, Mohammad Urf","id":"49274"},{"id":"22707","full_name":"Sprenger, Alexander","last_name":"Sprenger","first_name":"Alexander"},{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"date_created":"2019-02-26T15:11:02Z","date_updated":"2022-01-06T07:03:51Z","publisher":"31. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'19)","status":"public","type":"misc","language":[{"iso":"eng"}],"keyword":["WORKSHOP"],"user_id":"209","department":[{"_id":"48"}],"_id":"8112"},{"intvolume":"        28","page":"1-23","citation":{"apa":"Sprenger, A., &#38; Hellebrand, S. (2019). Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. <i>Journal of Circuits, Systems and Computers</i>, <i>28</i>(1), 1–23. <a href=\"https://doi.org/10.1142/s0218126619400012\">https://doi.org/10.1142/s0218126619400012</a>","bibtex":"@article{Sprenger_Hellebrand_2019, title={Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test}, volume={28}, DOI={<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>}, number={1}, journal={Journal of Circuits, Systems and Computers}, publisher={World Scientific Publishing Company}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–23} }","short":"A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28 (2019) 1–23.","mla":"Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test.” <i>Journal of Circuits, Systems and Computers</i>, vol. 28, no. 1, World Scientific Publishing Company, 2019, pp. 1–23, doi:<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>.","ama":"Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test. <i>Journal of Circuits, Systems and Computers</i>. 2019;28(1):1-23. doi:<a href=\"https://doi.org/10.1142/s0218126619400012\">10.1142/s0218126619400012</a>","chicago":"Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test.” <i>Journal of Circuits, Systems and Computers</i> 28, no. 1 (2019): 1–23. <a href=\"https://doi.org/10.1142/s0218126619400012\">https://doi.org/10.1142/s0218126619400012</a>.","ieee":"A. Sprenger and S. Hellebrand, “Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test,” <i>Journal of Circuits, Systems and Computers</i>, vol. 28, no. 1, pp. 1–23, 2019."},"publication_identifier":{"issn":["0218-1266","1793-6454"]},"publication_status":"published","doi":"10.1142/s0218126619400012","date_updated":"2022-01-06T07:03:58Z","volume":28,"author":[{"first_name":"Alexander","id":"22707","full_name":"Sprenger, Alexander","last_name":"Sprenger"},{"id":"209","full_name":"Hellebrand, Sybille","orcid":"0000-0002-3717-3939","last_name":"Hellebrand","first_name":"Sybille"}],"status":"public","type":"journal_article","_id":"8667","project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"department":[{"_id":"48"}],"user_id":"59789","year":"2019","issue":"1","title":"Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test","publisher":"World Scientific Publishing Company","date_created":"2019-03-27T08:57:42Z","publication":"Journal of Circuits, Systems and Computers","language":[{"iso":"eng"}]},{"department":[{"_id":"48"}],"user_id":"209","_id":"12918","language":[{"iso":"eng"}],"keyword":["Faster-than-at-speed test","BIST","DFT","Test response compaction","Stochastic compactor","X-handling"],"publication":"50th IEEE International Test Conference (ITC)","type":"conference","status":"public","abstract":[{"lang":"eng","text":"The test for small delay faults is of major importance for predicting potential early life failures or wearout problems. Typically, a faster-than-at-speed test (FAST) with sev¬eral different frequencies is used to detect also hidden small delays, which can only be propagated over short paths. But then the outputs at the end of long paths may no longer reach their stable values at the nominal observation time and must be considered as unknown (X-values). Thus, test response compaction for FAST must be extremely flexible to cope with high X-rates, which also vary with the test frequencies. Stochastic compaction introduced by Mitra et al. is controlled by weighted pseudo-random signals allowing for easy adaptation to varying conditions. As demonstrated in previous work, the pseudo-random control can be optimized for high fault efficiency or X-reduction, but a given target in fault efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is introduced in this paper. It is based on the observation that many faults are lost in the compaction of relatively few critical test patterns. For these critical patterns a deterministic compaction phase is added to the test, where the existing compactor structure is re-used, but controlled by specifically determined control vectors. "}],"author":[{"last_name":"Maaz","id":"49274","full_name":"Maaz, Mohammad Urf","first_name":"Mohammad Urf"},{"last_name":"Sprenger","full_name":"Sprenger, Alexander","id":"22707","first_name":"Alexander"},{"full_name":"Hellebrand, Sybille","id":"209","last_name":"Hellebrand","orcid":"0000-0002-3717-3939","first_name":"Sybille"}],"date_created":"2019-08-14T06:59:04Z","date_updated":"2022-05-11T17:09:35Z","publisher":"IEEE","conference":{"location":"Washington, DC, USA","end_date":"2019-11-14","start_date":"2019-11-12","name":"50th IEEE International Test Conference (ITC)"},"title":"A Hybrid Space Compactor for Adaptive X-Handling","quality_controlled":"1","publication_status":"published","page":"1-8","citation":{"apa":"Maaz, M. U., Sprenger, A., &#38; Hellebrand, S. (2019). A Hybrid Space Compactor for Adaptive X-Handling. <i>50th IEEE International Test Conference (ITC)</i>, 1–8.","bibtex":"@inproceedings{Maaz_Sprenger_Hellebrand_2019, place={Washington, DC, USA}, title={A Hybrid Space Compactor for Adaptive X-Handling}, booktitle={50th IEEE International Test Conference (ITC)}, publisher={IEEE}, author={Maaz, Mohammad Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–8} }","short":"M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.","mla":"Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.” <i>50th IEEE International Test Conference (ITC)</i>, IEEE, 2019, pp. 1–8.","chicago":"Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. “A Hybrid Space Compactor for Adaptive X-Handling.” In <i>50th IEEE International Test Conference (ITC)</i>, 1–8. Washington, DC, USA: IEEE, 2019.","ieee":"M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for Adaptive X-Handling,” in <i>50th IEEE International Test Conference (ITC)</i>, Washington, DC, USA, 2019, pp. 1–8.","ama":"Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling. In: <i>50th IEEE International Test Conference (ITC)</i>. IEEE; 2019:1-8."},"place":"Washington, DC, USA","year":"2019"},{"citation":{"apa":"Sprenger, A., &#38; Hellebrand, S. (2018). <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).","bibtex":"@book{Sprenger_Hellebrand_2018, place={Freiburg, Germany}, title={Stochastische Kompaktierung für den Hochgeschwindigkeitstest}, publisher={30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18)}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2018} }","short":"A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest, 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), Freiburg, Germany, 2018.","mla":"Sprenger, Alexander, and Sybille Hellebrand. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.","ama":"Sprenger A, Hellebrand S. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18); 2018.","ieee":"A. Sprenger and S. Hellebrand, <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.","chicago":"Sprenger, Alexander, and Sybille Hellebrand. <i>Stochastische Kompaktierung für den Hochgeschwindigkeitstest</i>. Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018."},"year":"2018","place":"Freiburg, Germany","date_created":"2018-10-02T12:29:44Z","author":[{"last_name":"Sprenger","full_name":"Sprenger, Alexander","id":"22707","first_name":"Alexander"},{"first_name":"Sybille","full_name":"Hellebrand, Sybille","id":"209","orcid":"0000-0002-3717-3939","last_name":"Hellebrand"}],"publisher":"30. Workshop \"Testmethoden und Zuverlässigkeit von Schaltungen und Systemen\" (TuZ'18)","date_updated":"2022-01-06T07:01:13Z","title":"Stochastische Kompaktierung für den Hochgeschwindigkeitstest","type":"misc","status":"public","user_id":"22707","department":[{"_id":"48"}],"_id":"4576","language":[{"iso":"ger"}],"keyword":["WORKSHOP"]},{"type":"conference","publication":"2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS)","status":"public","user_id":"209","department":[{"_id":"48"}],"project":[{"name":"Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"_id":"4575","language":[{"iso":"eng"}],"publication_status":"published","publication_identifier":{"isbn":["9781538657546"]},"citation":{"chicago":"Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” In <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. Budapest, Hungary: IEEE, 2018. <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">https://doi.org/10.1109/ddecs.2018.00020</a>.","ieee":"A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test,” 2018, doi: <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>.","ama":"Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. In: <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>","apa":"Sprenger, A., &#38; Hellebrand, S. (2018). Tuning Stochastic Space Compaction to Faster-than-at-Speed Test. <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>. <a href=\"https://doi.org/10.1109/ddecs.2018.00020\">https://doi.org/10.1109/ddecs.2018.00020</a>","mla":"Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction to Faster-than-at-Speed Test.” <i>2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)</i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>.","bibtex":"@inproceedings{Sprenger_Hellebrand_2018, place={Budapest, Hungary}, title={Tuning Stochastic Space Compaction to Faster-than-at-Speed Test}, DOI={<a href=\"https://doi.org/10.1109/ddecs.2018.00020\">10.1109/ddecs.2018.00020</a>}, booktitle={2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS)}, publisher={IEEE}, author={Sprenger, Alexander and Hellebrand, Sybille}, year={2018} }","short":"A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic Circuits &#38; Systems (DDECS), IEEE, Budapest, Hungary, 2018."},"year":"2018","place":"Budapest, Hungary","author":[{"full_name":"Sprenger, Alexander","id":"22707","last_name":"Sprenger","first_name":"Alexander"},{"first_name":"Sybille","id":"209","full_name":"Hellebrand, Sybille","last_name":"Hellebrand","orcid":"0000-0002-3717-3939"}],"date_created":"2018-10-02T12:18:46Z","publisher":"IEEE","date_updated":"2022-05-11T17:10:37Z","doi":"10.1109/ddecs.2018.00020","title":"Tuning Stochastic Space Compaction to Faster-than-at-Speed Test"}]