---
_id: '46482'
abstract:
- lang: eng
text: "Ever increasing demands on the performance of microchips are leading to ever
more complex semiconductor technologies with ever shrinking feature sizes. Complex
applications with high demands on safety and reliability, such as autonomous driving,
are simultaneously driving the requirements for test and diagnosis of VLSI circuits.
Throughout the life cycle of a microchip, uncertainties occur that affect its
timing behavior. For example, weak circuit structures, aging effects, or process
variations can lead to a change in the timing behavior of the circuit. While these
uncertainties do not necessarily lead to a change of the functional behavior,
they can lead to a reliability problem.\r\nWith modular and hybrid compaction
two test instruments are presented in this work that can be used for X-tolerant
test response compaction in the built-in Faster-than-At-Speed Test (FAST) which
is used to detect uncertainties in VLSI circuits. One challenge for test response
compaction during FAST is the high and varying X-rate at the outputs of the circuit
under test. By dividing the circuit outputs into test groups and separately compacting
these test groups using stochastic compactors, the modular compaction is able
to handle these high and varying X-rates.\r\nTo deal with uncertainties on logic
interconnects, a method for distinguishing crosstalk and process variation is
presented. In current semiconductor technologies, the number of parasitic coupling
capacitances between logic interconnects is growing. These coupling capacitances
can lead to crosstalk, which causes increased current flow in the logic interconnects,
which in turn can lead to increased electromigration. In the presented method,
delay maps describing the timing behavior of the circuit outputs at different
operating points are used to train artificial neural networks which classify the
tested circuits into fault-free and faulty."
- lang: ger
text: "Immer größere Anforderungen an die Leistungsfähigkeit von Mikrochips führen
zu Halbleitertechnologien mit immer kleiner werdenden Strukturgrößen. Anwendungen
mit hohen Ansprüchen an Sicherheit und Zuverlässigkeit, wie z.B. das autonome
Fahren, treiben gleichzeitig die Anforderungen an den Test hochintegrierter Schaltungen
an. Während des gesamten Lebenszyklus eines Mikrochips kommt es zu Unsicherheiten
im Zeitverhalten. So können z.B. schwache Schaltungsstrukturen, Alterungseffekte
oder Prozessvariationen zu einer Veränderung des Zeitverhaltens führen. Während
diese Unsicherheiten nicht zu einer Veränderung des funktionalen Verhaltens führen
müssen, können sie jedoch zu einem Zuverlässigkeitsproblem führen.\r\nMit der
modularen und der hybriden Kompaktierung werden in dieser Arbeit zwei Testinstrumente
vorgestellt, die für die X-tolerante Testantwortkompaktierung im eingebauten Hochgeschwindigkeitstest
verwendet werden können. Eine Herausforderung für die Testantwortkompaktierung
während des Hochgeschwindigkeitstests ist die hohe und variierende X-Rate an den
Ausgängen der zu testenden Schaltung. Durch die Einteilung der Schaltungsausgänge
in Prüfgruppen und die separierte Kompaktierung der Prüfgruppen mithilfe von stochastischen
Kompaktierern, können die vorgestellten Verfahren diese hohen und variierenden
X-Raten verarbeiten.\r\nFür den Umgang mit Unsicherheiten auf Verbindungsleitungen
der Logik-Schaltung wird ein Verfahren zur Unterscheidung von Übersprechen und
Prozessvariation vorgestellt. In aktuellen Halbleitertechnologien kommt es vermehrt
zu parasitären Koppelkapazitäten zwischen den Verbindungsleitungen. In dem vorgestellten
Verfahren werden künstliche neuronale Netze trainiert, um die Schaltungen in fehlerfrei
und fehlerhaft zu klassifizieren."
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
orcid: 0000-0002-0775-7677
citation:
ama: Sprenger A. Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten
in Logikblöcken hochintegrierter Schaltungen. Universität Paderborn; 2023.
doi:10.17619/UNIPB/1-1787
apa: Sprenger, A. (2023). Testinstrumente und Testdatenanalyse zur Verarbeitung
von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität
Paderborn. https://doi.org/10.17619/UNIPB/1-1787
bibtex: '@book{Sprenger_2023, place={Paderborn}, title={Testinstrumente und Testdatenanalyse
zur Verarbeitung von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen},
DOI={10.17619/UNIPB/1-1787},
publisher={Universität Paderborn}, author={Sprenger, Alexander}, year={2023} }'
chicago: 'Sprenger, Alexander. Testinstrumente und Testdatenanalyse zur Verarbeitung
von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Paderborn:
Universität Paderborn, 2023. https://doi.org/10.17619/UNIPB/1-1787.'
ieee: 'A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von
Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Paderborn: Universität
Paderborn, 2023.'
mla: Sprenger, Alexander. Testinstrumente und Testdatenanalyse zur Verarbeitung
von Unsicherheiten in Logikblöcken hochintegrierter Schaltungen. Universität
Paderborn, 2023, doi:10.17619/UNIPB/1-1787.
short: A. Sprenger, Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten
in Logikblöcken hochintegrierter Schaltungen, Universität Paderborn, Paderborn,
2023.
date_created: 2023-08-12T09:10:38Z
date_updated: 2023-08-12T09:13:18Z
department:
- _id: '48'
doi: 10.17619/UNIPB/1-1787
extern: '1'
keyword:
- Testantwortkompaktierung
- Prozessvariation
- Silicon Lifecycle Management
language:
- iso: ger
main_file_link:
- open_access: '1'
url: https://nbn-resolving.org/urn:nbn:de:hbz:466:2-45493
oa: '1'
page: xi, 160
place: Paderborn
publication_status: published
publisher: Universität Paderborn
status: public
supervisor:
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
title: Testinstrumente und Testdatenanalyse zur Verarbeitung von Unsicherheiten in
Logikblöcken hochintegrierter Schaltungen
type: dissertation
user_id: '22707'
year: '2023'
...
---
_id: '19422'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Somayeh
full_name: Sadeghi-Kohan, Somayeh
id: '78614'
last_name: Sadeghi-Kohan
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Sadeghi-Kohan S, Reimer JD, Hellebrand S. Variation-Aware Test
for Logic Interconnects using Neural Networks - A Case Study. In: IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020. ; 2020.'
apa: Sprenger, A., Sadeghi-Kohan, S., Reimer, J. D., & Hellebrand, S. (2020).
Variation-Aware Test for Logic Interconnects using Neural Networks - A Case Study.
IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFT’20), October 2020.
bibtex: '@inproceedings{Sprenger_Sadeghi-Kohan_Reimer_Hellebrand_2020, place={Virtual
Conference - Originally Frascati (Rome), Italy}, title={Variation-Aware Test for
Logic Interconnects using Neural Networks - A Case Study}, booktitle={IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020}, author={Sprenger, Alexander and Sadeghi-Kohan, Somayeh and Reimer,
Jan Dennis and Hellebrand, Sybille}, year={2020} }'
chicago: Sprenger, Alexander, Somayeh Sadeghi-Kohan, Jan Dennis Reimer, and Sybille
Hellebrand. “Variation-Aware Test for Logic Interconnects Using Neural Networks
- A Case Study.” In IEEE International Symposium on Defect and Fault Tolerance
in VLSI and Nanotechnology Systems (DFT’20), October 2020. Virtual Conference
- Originally Frascati (Rome), Italy, 2020.
ieee: A. Sprenger, S. Sadeghi-Kohan, J. D. Reimer, and S. Hellebrand, “Variation-Aware
Test for Logic Interconnects using Neural Networks - A Case Study,” 2020.
mla: Sprenger, Alexander, et al. “Variation-Aware Test for Logic Interconnects Using
Neural Networks - A Case Study.” IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20), October 2020,
2020.
short: 'A. Sprenger, S. Sadeghi-Kohan, J.D. Reimer, S. Hellebrand, in: IEEE International
Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT’20),
October 2020, Virtual Conference - Originally Frascati (Rome), Italy, 2020.'
conference:
end_date: 2020-10-21
start_date: 2020-10-19
date_created: 2020-09-15T14:03:02Z
date_updated: 2022-02-19T14:16:58Z
department:
- _id: '48'
language:
- iso: eng
place: Virtual Conference - Originally Frascati (Rome), Italy
publication: IEEE International Symposium on Defect and Fault Tolerance in VLSI and
Nanotechnology Systems (DFT’20), October 2020
publication_status: published
status: public
title: Variation-Aware Test for Logic Interconnects using Neural Networks - A Case
Study
type: conference
user_id: '209'
year: '2020'
...
---
_id: '19421'
author:
- first_name: Stefan
full_name: Holst, Stefan
last_name: Holst
- first_name: Matthias
full_name: Kampmann, Matthias
id: '10935'
last_name: Kampmann
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Jan Dennis
full_name: Reimer, Jan Dennis
id: '36703'
last_name: Reimer
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
- first_name: Hans-Joachim
full_name: Wunderlich, Hans-Joachim
last_name: Wunderlich
- first_name: Xiaoqing
full_name: Weng, Xiaoqing
last_name: Weng
citation:
ama: 'Holst S, Kampmann M, Sprenger A, et al. Logic Fault Diagnosis of Hidden Delay
Defects. In: IEEE International Test Conference (ITC’20), November 2020.
; 2020.'
apa: Holst, S., Kampmann, M., Sprenger, A., Reimer, J. D., Hellebrand, S., Wunderlich,
H.-J., & Weng, X. (2020). Logic Fault Diagnosis of Hidden Delay Defects. IEEE
International Test Conference (ITC’20), November 2020.
bibtex: '@inproceedings{Holst_Kampmann_Sprenger_Reimer_Hellebrand_Wunderlich_Weng_2020,
place={Virtual Conference - Originally Washington, DC, USA}, title={Logic Fault
Diagnosis of Hidden Delay Defects}, booktitle={IEEE International Test Conference
(ITC’20), November 2020}, author={Holst, Stefan and Kampmann, Matthias and Sprenger,
Alexander and Reimer, Jan Dennis and Hellebrand, Sybille and Wunderlich, Hans-Joachim
and Weng, Xiaoqing}, year={2020} }'
chicago: Holst, Stefan, Matthias Kampmann, Alexander Sprenger, Jan Dennis Reimer,
Sybille Hellebrand, Hans-Joachim Wunderlich, and Xiaoqing Weng. “Logic Fault Diagnosis
of Hidden Delay Defects.” In IEEE International Test Conference (ITC’20), November
2020. Virtual Conference - Originally Washington, DC, USA, 2020.
ieee: S. Holst et al., “Logic Fault Diagnosis of Hidden Delay Defects,” 2020.
mla: Holst, Stefan, et al. “Logic Fault Diagnosis of Hidden Delay Defects.” IEEE
International Test Conference (ITC’20), November 2020, 2020.
short: 'S. Holst, M. Kampmann, A. Sprenger, J.D. Reimer, S. Hellebrand, H.-J. Wunderlich,
X. Weng, in: IEEE International Test Conference (ITC’20), November 2020, Virtual
Conference - Originally Washington, DC, USA, 2020.'
date_created: 2020-09-15T13:56:08Z
date_updated: 2022-05-11T17:08:20Z
department:
- _id: '48'
language:
- iso: eng
place: Virtual Conference - Originally Washington, DC, USA
publication: IEEE International Test Conference (ITC'20), November 2020
publication_status: published
status: public
title: Logic Fault Diagnosis of Hidden Delay Defects
type: conference
user_id: '209'
year: '2020'
...
---
_id: '8112'
author:
- first_name: Mohammad Urf
full_name: Maaz, Mohammad Urf
id: '49274'
last_name: Maaz
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Varying
X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’19); 2019.'
apa: 'Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space
Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19).'
bibtex: '@book{Maaz_Sprenger_Hellebrand_2019, place={Prien am Chiemsee}, title={A
Hybrid Space Compactor for Varying X-Rates}, publisher={31. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19)}, author={Maaz, Mohammad
Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019} }'
chicago: 'Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. A Hybrid
Space Compactor for Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19), 2019.'
ieee: 'M. U. Maaz, A. Sprenger, and S. Hellebrand, A Hybrid Space Compactor for
Varying X-Rates. Prien am Chiemsee: 31. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’19), 2019.'
mla: Maaz, Mohammad Urf, et al. A Hybrid Space Compactor for Varying X-Rates.
31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’19),
2019.
short: M.U. Maaz, A. Sprenger, S. Hellebrand, A Hybrid Space Compactor for Varying
X-Rates, 31. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen”
(TuZ’19), Prien am Chiemsee, 2019.
date_created: 2019-02-26T15:11:02Z
date_updated: 2022-01-06T07:03:51Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: eng
place: Prien am Chiemsee
publisher: 31. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'19)
status: public
title: A Hybrid Space Compactor for Varying X-Rates
type: misc
user_id: '209'
year: '2019'
...
---
_id: '8667'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: Sprenger A, Hellebrand S. Divide and Compact - Stochastic Space Compaction
for Faster-than-At-Speed Test. Journal of Circuits, Systems and Computers.
2019;28(1):1-23. doi:10.1142/s0218126619400012
apa: Sprenger, A., & Hellebrand, S. (2019). Divide and Compact - Stochastic
Space Compaction for Faster-than-At-Speed Test. Journal of Circuits, Systems
and Computers, 28(1), 1–23. https://doi.org/10.1142/s0218126619400012
bibtex: '@article{Sprenger_Hellebrand_2019, title={Divide and Compact - Stochastic
Space Compaction for Faster-than-At-Speed Test}, volume={28}, DOI={10.1142/s0218126619400012},
number={1}, journal={Journal of Circuits, Systems and Computers}, publisher={World
Scientific Publishing Company}, author={Sprenger, Alexander and Hellebrand, Sybille},
year={2019}, pages={1–23} }'
chicago: 'Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic
Space Compaction for Faster-than-At-Speed Test.” Journal of Circuits, Systems
and Computers 28, no. 1 (2019): 1–23. https://doi.org/10.1142/s0218126619400012.'
ieee: A. Sprenger and S. Hellebrand, “Divide and Compact - Stochastic Space Compaction
for Faster-than-At-Speed Test,” Journal of Circuits, Systems and Computers,
vol. 28, no. 1, pp. 1–23, 2019.
mla: Sprenger, Alexander, and Sybille Hellebrand. “Divide and Compact - Stochastic
Space Compaction for Faster-than-At-Speed Test.” Journal of Circuits, Systems
and Computers, vol. 28, no. 1, World Scientific Publishing Company, 2019,
pp. 1–23, doi:10.1142/s0218126619400012.
short: A. Sprenger, S. Hellebrand, Journal of Circuits, Systems and Computers 28
(2019) 1–23.
date_created: 2019-03-27T08:57:42Z
date_updated: 2022-01-06T07:03:58Z
department:
- _id: '48'
doi: 10.1142/s0218126619400012
intvolume: ' 28'
issue: '1'
language:
- iso: eng
page: 1-23
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Journal of Circuits, Systems and Computers
publication_identifier:
issn:
- 0218-1266
- 1793-6454
publication_status: published
publisher: World Scientific Publishing Company
status: public
title: Divide and Compact - Stochastic Space Compaction for Faster-than-At-Speed Test
type: journal_article
user_id: '59789'
volume: 28
year: '2019'
...
---
_id: '12918'
abstract:
- lang: eng
text: 'The test for small delay faults is of major importance for predicting potential
early life failures or wearout problems. Typically, a faster-than-at-speed test
(FAST) with sev¬eral different frequencies is used to detect also hidden small
delays, which can only be propagated over short paths. But then the outputs at
the end of long paths may no longer reach their stable values at the nominal observation
time and must be considered as unknown (X-values). Thus, test response compaction
for FAST must be extremely flexible to cope with high X-rates, which also vary
with the test frequencies. Stochastic compaction introduced by Mitra et al. is
controlled by weighted pseudo-random signals allowing for easy adaptation to varying
conditions. As demonstrated in previous work, the pseudo-random control can be
optimized for high fault efficiency or X-reduction, but a given target in fault
efficiency cannot be guaranteed. To close this gap, a hybrid space compactor is
introduced in this paper. It is based on the observation that many faults are
lost in the compaction of relatively few critical test patterns. For these critical
patterns a deterministic compaction phase is added to the test, where the existing
compactor structure is re-used, but controlled by specifically determined control
vectors. '
author:
- first_name: Mohammad Urf
full_name: Maaz, Mohammad Urf
id: '49274'
last_name: Maaz
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Maaz MU, Sprenger A, Hellebrand S. A Hybrid Space Compactor for Adaptive X-Handling.
In: 50th IEEE International Test Conference (ITC). IEEE; 2019:1-8.'
apa: Maaz, M. U., Sprenger, A., & Hellebrand, S. (2019). A Hybrid Space Compactor
for Adaptive X-Handling. 50th IEEE International Test Conference (ITC),
1–8.
bibtex: '@inproceedings{Maaz_Sprenger_Hellebrand_2019, place={Washington, DC, USA},
title={A Hybrid Space Compactor for Adaptive X-Handling}, booktitle={50th IEEE
International Test Conference (ITC)}, publisher={IEEE}, author={Maaz, Mohammad
Urf and Sprenger, Alexander and Hellebrand, Sybille}, year={2019}, pages={1–8}
}'
chicago: 'Maaz, Mohammad Urf, Alexander Sprenger, and Sybille Hellebrand. “A Hybrid
Space Compactor for Adaptive X-Handling.” In 50th IEEE International Test Conference
(ITC), 1–8. Washington, DC, USA: IEEE, 2019.'
ieee: M. U. Maaz, A. Sprenger, and S. Hellebrand, “A Hybrid Space Compactor for
Adaptive X-Handling,” in 50th IEEE International Test Conference (ITC),
Washington, DC, USA, 2019, pp. 1–8.
mla: Maaz, Mohammad Urf, et al. “A Hybrid Space Compactor for Adaptive X-Handling.”
50th IEEE International Test Conference (ITC), IEEE, 2019, pp. 1–8.
short: 'M.U. Maaz, A. Sprenger, S. Hellebrand, in: 50th IEEE International Test
Conference (ITC), IEEE, Washington, DC, USA, 2019, pp. 1–8.'
conference:
end_date: 2019-11-14
location: Washington, DC, USA
name: 50th IEEE International Test Conference (ITC)
start_date: 2019-11-12
date_created: 2019-08-14T06:59:04Z
date_updated: 2022-05-11T17:09:35Z
department:
- _id: '48'
keyword:
- Faster-than-at-speed test
- BIST
- DFT
- Test response compaction
- Stochastic compactor
- X-handling
language:
- iso: eng
page: 1-8
place: Washington, DC, USA
publication: 50th IEEE International Test Conference (ITC)
publication_status: published
publisher: IEEE
quality_controlled: '1'
status: public
title: A Hybrid Space Compactor for Adaptive X-Handling
type: conference
user_id: '209'
year: '2019'
...
---
_id: '4576'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Hellebrand S. Stochastische Kompaktierung für den Hochgeschwindigkeitstest.
Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen” (TuZ’18); 2018.'
apa: 'Sprenger, A., & Hellebrand, S. (2018). Stochastische Kompaktierung
für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18).'
bibtex: '@book{Sprenger_Hellebrand_2018, place={Freiburg, Germany}, title={Stochastische
Kompaktierung für den Hochgeschwindigkeitstest}, publisher={30. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18)}, author={Sprenger,
Alexander and Hellebrand, Sybille}, year={2018} }'
chicago: 'Sprenger, Alexander, and Sybille Hellebrand. Stochastische Kompaktierung
für den Hochgeschwindigkeitstest. Freiburg, Germany: 30. Workshop “Testmethoden
und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18), 2018.'
ieee: 'A. Sprenger and S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest.
Freiburg, Germany: 30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen
und Systemen” (TuZ’18), 2018.'
mla: Sprenger, Alexander, and Sybille Hellebrand. Stochastische Kompaktierung
für den Hochgeschwindigkeitstest. 30. Workshop “Testmethoden und Zuverlässigkeit
von Schaltungen und Systemen” (TuZ’18), 2018.
short: A. Sprenger, S. Hellebrand, Stochastische Kompaktierung für den Hochgeschwindigkeitstest,
30. Workshop “Testmethoden und Zuverlässigkeit von Schaltungen und Systemen” (TuZ’18),
Freiburg, Germany, 2018.
date_created: 2018-10-02T12:29:44Z
date_updated: 2022-01-06T07:01:13Z
department:
- _id: '48'
keyword:
- WORKSHOP
language:
- iso: ger
place: Freiburg, Germany
publisher: 30. Workshop "Testmethoden und Zuverlässigkeit von Schaltungen und Systemen"
(TuZ'18)
status: public
title: Stochastische Kompaktierung für den Hochgeschwindigkeitstest
type: misc
user_id: '22707'
year: '2018'
...
---
_id: '4575'
author:
- first_name: Alexander
full_name: Sprenger, Alexander
id: '22707'
last_name: Sprenger
- first_name: Sybille
full_name: Hellebrand, Sybille
id: '209'
last_name: Hellebrand
orcid: 0000-0002-3717-3939
citation:
ama: 'Sprenger A, Hellebrand S. Tuning Stochastic Space Compaction to Faster-than-at-Speed
Test. In: 2018 IEEE 21st International Symposium on Design and Diagnostics
of Electronic Circuits & Systems (DDECS). IEEE; 2018. doi:10.1109/ddecs.2018.00020'
apa: Sprenger, A., & Hellebrand, S. (2018). Tuning Stochastic Space Compaction
to Faster-than-at-Speed Test. 2018 IEEE 21st International Symposium on Design
and Diagnostics of Electronic Circuits & Systems (DDECS). https://doi.org/10.1109/ddecs.2018.00020
bibtex: '@inproceedings{Sprenger_Hellebrand_2018, place={Budapest, Hungary}, title={Tuning
Stochastic Space Compaction to Faster-than-at-Speed Test}, DOI={10.1109/ddecs.2018.00020},
booktitle={2018 IEEE 21st International Symposium on Design and Diagnostics of
Electronic Circuits & Systems (DDECS)}, publisher={IEEE}, author={Sprenger,
Alexander and Hellebrand, Sybille}, year={2018} }'
chicago: 'Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space
Compaction to Faster-than-at-Speed Test.” In 2018 IEEE 21st International Symposium
on Design and Diagnostics of Electronic Circuits & Systems (DDECS). Budapest,
Hungary: IEEE, 2018. https://doi.org/10.1109/ddecs.2018.00020.'
ieee: 'A. Sprenger and S. Hellebrand, “Tuning Stochastic Space Compaction to Faster-than-at-Speed
Test,” 2018, doi: 10.1109/ddecs.2018.00020.'
mla: Sprenger, Alexander, and Sybille Hellebrand. “Tuning Stochastic Space Compaction
to Faster-than-at-Speed Test.” 2018 IEEE 21st International Symposium on Design
and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, 2018,
doi:10.1109/ddecs.2018.00020.
short: 'A. Sprenger, S. Hellebrand, in: 2018 IEEE 21st International Symposium on
Design and Diagnostics of Electronic Circuits & Systems (DDECS), IEEE, Budapest,
Hungary, 2018.'
date_created: 2018-10-02T12:18:46Z
date_updated: 2022-05-11T17:10:37Z
department:
- _id: '48'
doi: 10.1109/ddecs.2018.00020
language:
- iso: eng
place: Budapest, Hungary
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: 2018 IEEE 21st International Symposium on Design and Diagnostics of Electronic
Circuits & Systems (DDECS)
publication_identifier:
isbn:
- '9781538657546'
publication_status: published
publisher: IEEE
status: public
title: Tuning Stochastic Space Compaction to Faster-than-at-Speed Test
type: conference
user_id: '209'
year: '2018'
...