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(TACO)</i>, vol. 16, no. 2, ACM, 2019, pp. 14:1–14:26, doi:<a href=\"https://doi.org/10.1145/3319423\">10.1145/3319423</a>.","bibtex":"@article{Riebler_Vaz_Kenter_Plessl_2019, title={Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL}, volume={16}, DOI={<a href=\"https://doi.org/10.1145/3319423\">10.1145/3319423</a>}, number={2}, journal={ACM Trans. Archit. Code Optim. (TACO)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2019}, pages={14:1–14:26} }","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Tobias Kenter, and Christian Plessl. “Transparent Acceleration for Heterogeneous Platforms with Compilation to OpenCL.” <i>ACM Trans. Archit. Code Optim. (TACO)</i> 16, no. 2 (2019): 14:1–14:26. <a href=\"https://doi.org/10.1145/3319423\">https://doi.org/10.1145/3319423</a>.","ieee":"H. Riebler, G. F. Vaz, T. Kenter, and C. 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ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, 2018.","bibtex":"@inproceedings{Riebler_Vaz_Kenter_Plessl_2018, title={Automated Code Acceleration Targeting Heterogeneous OpenCL Devices}, DOI={<a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>}, booktitle={Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)}, publisher={ACM}, author={Riebler, Heinrich and Vaz, Gavin Francis and Kenter, Tobias and Plessl, Christian}, year={2018} }","mla":"Riebler, Heinrich, et al. “Automated Code Acceleration Targeting Heterogeneous OpenCL Devices.” <i>Proc. ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP)</i>, ACM, 2018, doi:<a href=\"https://doi.org/10.1145/3178487.3178534\">10.1145/3178487.3178534</a>.","apa":"Riebler, H., Vaz, G. F., Kenter, T., &#38; Plessl, C. (2018). Automated Code Acceleration Targeting Heterogeneous OpenCL Devices. <i>Proc. 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HiPEAC Workshop on Reonfigurable Computing (WRC)","type":"conference","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","date_updated":"2023-09-26T13:25:59Z","author":[{"last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961","first_name":"Heinrich"},{"first_name":"Gavin Francis","last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332"},{"first_name":"Christian","last_name":"Plessl","orcid":"0000-0001-5728-9982","id":"16153","full_name":"Plessl, Christian"},{"full_name":"Trainiti, Ettore M. G.","last_name":"Trainiti","first_name":"Ettore M. G."},{"first_name":"Gianluca C.","last_name":"Durelli","full_name":"Durelli, Gianluca C."},{"last_name":"Bolchini","full_name":"Bolchini, Cristiana","first_name":"Cristiana"}],"date_created":"2017-07-26T15:16:31Z","year":"2016","citation":{"ieee":"H. Riebler, G. F. Vaz, C. Plessl, E. M. G. Trainiti, G. C. Durelli, and C. Bolchini, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” 2016.","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G. Trainiti, Gianluca C. Durelli, and Cristiana Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","ama":"Riebler H, Vaz GF, Plessl C, Trainiti EMG, Durelli GC, Bolchini C. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>. ; 2016.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>.","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, C. Bolchini, in: Proc. HiPEAC Workshop on Reonfigurable Computing (WRC), 2016.","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)</i>, 2016.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, booktitle={Proc. HiPEAC Workshop on Reonfigurable Computing (WRC)}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G. and Durelli, Gianluca C. and Bolchini, Cristiana}, year={2016} }"},"quality_controlled":"1","has_accepted_license":"1"},{"publication":"Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)","type":"conference","abstract":[{"text":"Hardware accelerators are becoming popular in academia and industry. To move one step further from the state-of-the-art multicore plus accelerator approaches, we present in this paper our innovative SAVEHSA architecture. It comprises of a heterogeneous hardware platform with three different high-end accelerators attached over PCIe (GPGPU, FPGA and Intel MIC). Such systems can process parallel workloads very efficiently whilst being more energy efficient than regular CPU systems. To leverage the heterogeneity, the workload has to be distributed among the computing units in a way that each unit is well-suited for the assigned task and executable code must be available. To tackle this problem we present two software components; the first can perform resource allocation at runtime while respecting system and application goals (in terms of throughput, energy, latency, etc.) and the second is able to analyze an application and generate executable code for an accelerator at runtime. We demonstrate the first proof-of-concept implementation of our framework on the heterogeneous platform, discuss different runtime policies and measure the introduced overheads.","lang":"eng"}],"status":"public","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-21T13:01:09Z","creator":"florida","date_created":"2018-03-21T13:01:09Z","file_size":184334,"file_id":"1560","access_level":"closed","file_name":"138-07740545.pdf"}],"_id":"138","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","ddc":["040"],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-21T13:01:09Z","has_accepted_license":"1","quality_controlled":"1","year":"2016","page":"1-5","citation":{"ama":"Riebler H, Vaz GF, Plessl C, et al. Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. In: <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>. IEEE; 2016:1-5. doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>","chicago":"Riebler, Heinrich, Gavin Francis Vaz, Christian Plessl, Ettore M. G.  Trainiti, Gianluca C. Durelli, Emanuele Del Sozzo, Marco D.  Santambrogio, and Christina Bolchini. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” In <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. IEEE, 2016. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>.","ieee":"H. Riebler <i>et al.</i>, “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems,” in <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 2016, pp. 1–5, doi: <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","apa":"Riebler, H., Vaz, G. F., Plessl, C., Trainiti, E. M. G., Durelli, G. C., Del Sozzo, E., Santambrogio, M. D., &#38; Bolchini, C. (2016). Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems. <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, 1–5. <a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">https://doi.org/10.1109/RTSI.2016.7740545</a>","mla":"Riebler, Heinrich, et al. “Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems.” <i>Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)</i>, IEEE, 2016, pp. 1–5, doi:<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>.","bibtex":"@inproceedings{Riebler_Vaz_Plessl_Trainiti_Durelli_Del Sozzo_Santambrogio_Bolchini_2016, title={Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems}, DOI={<a href=\"https://doi.org/10.1109/RTSI.2016.7740545\">10.1109/RTSI.2016.7740545</a>}, booktitle={Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI)}, publisher={IEEE}, author={Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian and Trainiti, Ettore M. G.  and Durelli, Gianluca C. and Del Sozzo, Emanuele and Santambrogio, Marco D.  and Bolchini, Christina}, year={2016}, pages={1–5} }","short":"H. Riebler, G.F. Vaz, C. Plessl, E.M.G. Trainiti, G.C. Durelli, E. Del Sozzo, M.D. Santambrogio, C. Bolchini, in: Proceedings of International Forum on Research and Technologies for Society and Industry (RTSI), IEEE, 2016, pp. 1–5."},"publisher":"IEEE","date_updated":"2023-09-26T13:28:11Z","author":[{"first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Gavin Francis","last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis"},{"full_name":"Plessl, Christian","id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian"},{"full_name":"Trainiti, Ettore M. G. ","last_name":"Trainiti","first_name":"Ettore M. G. "},{"first_name":"Gianluca C.","full_name":"Durelli, Gianluca C.","last_name":"Durelli"},{"first_name":"Emanuele","full_name":"Del Sozzo, Emanuele","last_name":"Del Sozzo"},{"first_name":"Marco D. ","full_name":"Santambrogio, Marco D. ","last_name":"Santambrogio"},{"first_name":"Christina","last_name":"Bolchini","full_name":"Bolchini, Christina"}],"date_created":"2017-10-17T12:41:18Z","title":"Using Just-in-Time Code Generation for Transparent Resource Management in Heterogeneous Systems","doi":"10.1109/RTSI.2016.7740545"},{"ddc":["040"],"language":[{"iso":"eng"}],"abstract":[{"text":"A broad spectrum of applications can be accelerated by offloading computation intensive parts to reconfigurable hardware. However, to achieve speedups, the number of loop it- erations (trip count) needs to be sufficiently large to amortize offloading overheads. Trip counts are frequently not known at compile time, but only at runtime just before entering a loop. Therefore, we propose to generate code for both the CPU and the coprocessor, and defer the offloading decision to the application runtime. We demonstrate how a toolflow, based on the LLVM compiler framework, can automatically embed dynamic offloading de- cisions into the application code. We perform in-depth static and dynamic analysis of pop- ular benchmarks, which confirm the general potential of such an approach. We also pro- pose to optimize the offloading process by decoupling the runtime decision from the loop execution (decision slack). The feasibility of our approach is demonstrated by a toolflow that automatically identifies suitable data-parallel loops and generates code for the FPGA coprocessor of a Convey HC-1. We evaluate the integrated toolflow with representative loops executed for different input data sizes.","lang":"eng"}],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":3037854,"access_level":"closed","file_name":"165-1-s2.0-S0045790616301021-main.pdf","file_id":"1544","date_updated":"2018-03-21T12:45:47Z","date_created":"2018-03-21T12:45:47Z","creator":"florida"}],"publication":"Computers and Electrical Engineering","title":"Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code","publisher":"Elsevier","date_created":"2017-10-17T12:41:24Z","year":"2016","quality_controlled":"1","file_date_updated":"2018-03-21T12:45:47Z","_id":"165","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"grant_number":"160364472","_id":"14","name":"SFB 901 - Subprojekt C2"},{"_id":"4","name":"SFB 901 - Project Area C"},{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","status":"public","type":"journal_article","doi":"10.1016/j.compeleceng.2016.04.021","date_updated":"2023-09-26T13:26:38Z","volume":55,"author":[{"full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz","first_name":"Gavin Francis"},{"id":"8961","full_name":"Riebler, Heinrich","last_name":"Riebler","first_name":"Heinrich"},{"first_name":"Tobias","id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter"},{"full_name":"Plessl, Christian","id":"16153","orcid":"0000-0001-5728-9982","last_name":"Plessl","first_name":"Christian"}],"intvolume":"        55","page":"91-111","citation":{"chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i> 55 (2016): 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code,” <i>Computers and Electrical Engineering</i>, vol. 55, pp. 91–111, 2016, doi: <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>. 2016;55:91-111. doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2016). Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code. <i>Computers and Electrical Engineering</i>, <i>55</i>, 91–111. <a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">https://doi.org/10.1016/j.compeleceng.2016.04.021</a>","mla":"Vaz, Gavin Francis, et al. “Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code.” <i>Computers and Electrical Engineering</i>, vol. 55, Elsevier, 2016, pp. 91–111, doi:<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>.","bibtex":"@article{Vaz_Riebler_Kenter_Plessl_2016, title={Potential and Methods for Embedding Dynamic Offloading Decisions into Application Code}, volume={55}, DOI={<a href=\"https://doi.org/10.1016/j.compeleceng.2016.04.021\">10.1016/j.compeleceng.2016.04.021</a>}, journal={Computers and Electrical Engineering}, publisher={Elsevier}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2016}, pages={91–111} }","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, Computers and Electrical Engineering 55 (2016) 91–111."},"has_accepted_license":"1","publication_identifier":{"issn":["0045-7906"]}},{"quality_controlled":"1","has_accepted_license":"1","citation":{"ieee":"T. Kenter, G. F. Vaz, H. Riebler, and C. Plessl, “Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract),” 2016.","chicago":"Kenter, Tobias, Gavin Francis Vaz, Heinrich Riebler, and Christian Plessl. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” In <i>Workshop on Reconfigurable Computing (WRC)</i>, 2016.","ama":"Kenter T, Vaz GF, Riebler H, Plessl C. Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). In: <i>Workshop on Reconfigurable Computing (WRC)</i>. ; 2016.","short":"T. Kenter, G.F. Vaz, H. Riebler, C. Plessl, in: Workshop on Reconfigurable Computing (WRC), 2016.","mla":"Kenter, Tobias, et al. “Opportunities for Deferring Application Partitioning and Accelerator Synthesis to Runtime (Extended Abstract).” <i>Workshop on Reconfigurable Computing (WRC)</i>, 2016.","bibtex":"@inproceedings{Kenter_Vaz_Riebler_Plessl_2016, title={Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)}, booktitle={Workshop on Reconfigurable Computing (WRC)}, author={Kenter, Tobias and Vaz, Gavin Francis and Riebler, Heinrich and Plessl, Christian}, year={2016} }","apa":"Kenter, T., Vaz, G. F., Riebler, H., &#38; Plessl, C. (2016). Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract). <i>Workshop on Reconfigurable Computing (WRC)</i>."},"year":"2016","date_created":"2017-10-17T12:41:25Z","author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz"},{"last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich","first_name":"Heinrich"},{"first_name":"Christian","id":"16153","full_name":"Plessl, Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl"}],"date_updated":"2023-09-26T13:27:21Z","title":"Opportunities for deferring application partitioning and accelerator synthesis to runtime (extended abstract)","publication":"Workshop on Reconfigurable Computing (WRC)","type":"conference","status":"public","file":[{"content_type":"application/pdf","relation":"main_file","success":1,"date_created":"2018-03-21T12:39:46Z","creator":"florida","date_updated":"2018-03-21T12:39:46Z","access_level":"closed","file_name":"171-plessl16_fpl_wrc.pdf","file_id":"1538","file_size":54421}],"department":[{"_id":"27"},{"_id":"518"}],"user_id":"15278","_id":"171","project":[{"grant_number":"160364472","name":"SFB 901","_id":"1"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"language":[{"iso":"eng"}],"file_date_updated":"2018-03-21T12:39:46Z","ddc":["040"]},{"page":"1078-1083","citation":{"ieee":"M. Damschen, H. Riebler, G. F. Vaz, and C. Plessl, “Transparent offloading of computational hotspots from binary code to Xeon Phi,” in <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 2015, pp. 1078–1083, doi: <a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>.","chicago":"Damschen, Marvin, Heinrich Riebler, Gavin Francis Vaz, and Christian Plessl. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” In <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 1078–83. EDA Consortium / IEEE, 2015. <a href=\"https://doi.org/10.7873/DATE.2015.1124\">https://doi.org/10.7873/DATE.2015.1124</a>.","ama":"Damschen M, Riebler H, Vaz GF, Plessl C. Transparent offloading of computational hotspots from binary code to Xeon Phi. In: <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>. EDA Consortium / IEEE; 2015:1078-1083. doi:<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>","mla":"Damschen, Marvin, et al. “Transparent Offloading of Computational Hotspots from Binary Code to Xeon Phi.” <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, EDA Consortium / IEEE, 2015, pp. 1078–83, doi:<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>.","bibtex":"@inproceedings{Damschen_Riebler_Vaz_Plessl_2015, title={Transparent offloading of computational hotspots from binary code to Xeon Phi}, DOI={<a href=\"https://doi.org/10.7873/DATE.2015.1124\">10.7873/DATE.2015.1124</a>}, booktitle={Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)}, publisher={EDA Consortium / IEEE}, author={Damschen, Marvin and Riebler, Heinrich and Vaz, Gavin Francis and Plessl, Christian}, year={2015}, pages={1078–1083} }","short":"M. Damschen, H. Riebler, G.F. Vaz, C. Plessl, in: Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE), EDA Consortium / IEEE, 2015, pp. 1078–1083.","apa":"Damschen, M., Riebler, H., Vaz, G. F., &#38; Plessl, C. (2015). Transparent offloading of computational hotspots from binary code to Xeon Phi. <i>Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)</i>, 1078–1083. <a href=\"https://doi.org/10.7873/DATE.2015.1124\">https://doi.org/10.7873/DATE.2015.1124</a>"},"has_accepted_license":"1","doi":"10.7873/DATE.2015.1124","author":[{"last_name":"Damschen","full_name":"Damschen, Marvin","first_name":"Marvin"},{"first_name":"Heinrich","full_name":"Riebler, Heinrich","id":"8961","last_name":"Riebler"},{"first_name":"Gavin Francis","last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"}],"date_updated":"2023-09-26T13:31:44Z","status":"public","type":"conference","file_date_updated":"2018-03-21T10:29:49Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","_id":"238","project":[{"name":"SFB 901","_id":"1","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34","grant_number":"610996"}],"year":"2015","quality_controlled":"1","title":"Transparent offloading of computational hotspots from binary code to Xeon Phi","date_created":"2017-10-17T12:41:38Z","publisher":"EDA Consortium / IEEE","file":[{"date_updated":"2018-03-21T10:29:49Z","creator":"florida","date_created":"2018-03-21T10:29:49Z","file_size":380552,"file_name":"238-plessl15_date.pdf","file_id":"1500","access_level":"closed","content_type":"application/pdf","success":1,"relation":"main_file"}],"abstract":[{"text":"In this paper, we study how binary applications can be transparently accelerated with novel heterogeneous computing resources without requiring any manual porting or developer-provided hints. Our work is based on Binary Acceleration At Runtime (BAAR), our previously introduced binary acceleration mechanism that uses the LLVM Compiler Infrastructure. BAAR is designed as a client-server architecture. The client runs the program to be accelerated in an environment, which allows program analysis and profiling and identifies and extracts suitable program parts to be offloaded. The server compiles and optimizes these offloaded program parts for the accelerator and offers access to these functions to the client with a remote procedure call (RPC) interface. Our previous work proved the feasibility of our approach, but also showed that communication time and overheads limit the granularity of functions that can be meaningfully offloaded. In this work, we motivate the importance of a lightweight, high-performance communication between server and client and present a communication mechanism based on the Message Passing Interface (MPI). We evaluate our approach by using an Intel Xeon Phi 5110P as the acceleration target and show that the communication overhead can be reduced from 40% to 10%, thus enabling even small hotspots to benefit from offloading to an accelerator.","lang":"eng"}],"publication":"Proceedings of the 2015 Conference on Design, Automation and Test in Europe (DATE)","language":[{"iso":"eng"}],"ddc":["040"]},{"intvolume":"      8405","page":"144-155","citation":{"apa":"Kenter, T., Vaz, G. F., &#38; Plessl, C. (2014). Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, <i>8405</i>, 144–155. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>","short":"T. Kenter, G.F. Vaz, C. Plessl, in: Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC), Springer International Publishing, Cham, 2014, pp. 144–155.","bibtex":"@inproceedings{Kenter_Vaz_Plessl_2014, place={Cham}, series={Lecture Notes in Computer Science (LNCS)}, title={Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer}, volume={8405}, DOI={<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>}, booktitle={Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)}, publisher={Springer International Publishing}, author={Kenter, Tobias and Vaz, Gavin Francis and Plessl, Christian}, year={2014}, pages={144–155}, collection={Lecture Notes in Computer Science (LNCS)} }","mla":"Kenter, Tobias, et al. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, vol. 8405, Springer International Publishing, 2014, pp. 144–55, doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","chicago":"Kenter, Tobias, Gavin Francis Vaz, and Christian Plessl. “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer.” In <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 8405:144–55. Lecture Notes in Computer Science (LNCS). Cham: Springer International Publishing, 2014. <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">https://doi.org/10.1007/978-3-319-05960-0_13</a>.","ieee":"T. Kenter, G. F. Vaz, and C. Plessl, “Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer,” in <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>, 2014, vol. 8405, pp. 144–155, doi: <a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>.","ama":"Kenter T, Vaz GF, Plessl C. Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer. In: <i>Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)</i>. Vol 8405. Lecture Notes in Computer Science (LNCS). Springer International Publishing; 2014:144-155. doi:<a href=\"https://doi.org/10.1007/978-3-319-05960-0_13\">10.1007/978-3-319-05960-0_13</a>"},"place":"Cham","has_accepted_license":"1","doi":"10.1007/978-3-319-05960-0_13","volume":8405,"author":[{"last_name":"Kenter","id":"3145","full_name":"Kenter, Tobias","first_name":"Tobias"},{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"date_updated":"2023-09-26T13:34:08Z","status":"public","type":"conference","file_date_updated":"2018-03-20T07:02:02Z","department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"series_title":"Lecture Notes in Computer Science (LNCS)","user_id":"15278","_id":"388","project":[{"grant_number":"160364472","_id":"1","name":"SFB 901"},{"name":"SFB 901 - Subprojekt C2","_id":"14","grant_number":"160364472"},{"name":"SFB 901 - Project Area C","_id":"4"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"year":"2014","quality_controlled":"1","title":"Partitioning and Vectorizing Binary Applications for a Reconfigurable Vector Computer","date_created":"2017-10-17T12:42:07Z","publisher":"Springer International Publishing","file":[{"content_type":"application/pdf","success":1,"relation":"main_file","date_updated":"2018-03-20T07:02:02Z","creator":"florida","date_created":"2018-03-20T07:02:02Z","file_size":330193,"access_level":"closed","file_name":"388-plessl14_arc.pdf","file_id":"1387"}],"abstract":[{"text":"In order to leverage the use of reconfigurable architectures in general-purpose computing, quick and automated methods to find suitable accelerator designs are required. We tackle this challenge in both regards. In order to avoid long synthesis times, we target a vector copro- cessor, implemented on the FPGAs of a Convey HC-1. Previous studies showed that existing tools were not able to accelerate a real-world application with low effort. We present a toolflow to automatically identify suitable loops for vectorization, generate a corresponding hardware/software bipartition, and generate coprocessor code. Where applicable, we leverage outer-loop vectorization. We evaluate our tools with a set of characteristic loops, systematically analyzing different dependency and data layout properties.","lang":"eng"}],"publication":"Proceedings of the International Symposium on Reconfigurable Computing: Architectures, Tools, and Applications (ARC)","language":[{"iso":"eng"}],"ddc":["040"]},{"title":"Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach","doi":"10.1109/ISPA.2014.27","publisher":"IEEE","date_updated":"2023-09-26T13:35:40Z","author":[{"full_name":"C. Durelli, Gianluca","last_name":"C. Durelli","first_name":"Gianluca"},{"first_name":"Marcello","last_name":"Pogliani","full_name":"Pogliani, Marcello"},{"last_name":"Miele","full_name":"Miele, Antonio","first_name":"Antonio"},{"last_name":"Plessl","orcid":"0000-0001-5728-9982","full_name":"Plessl, Christian","id":"16153","first_name":"Christian"},{"first_name":"Heinrich","last_name":"Riebler","full_name":"Riebler, Heinrich","id":"8961"},{"id":"30332","full_name":"Vaz, Gavin Francis","last_name":"Vaz","first_name":"Gavin Francis"},{"full_name":"D. Santambrogio, Marco","last_name":"D. Santambrogio","first_name":"Marco"},{"first_name":"Cristiana","last_name":"Bolchini","full_name":"Bolchini, Cristiana"}],"date_created":"2018-03-26T13:40:14Z","year":"2014","page":"142-149","citation":{"bibtex":"@inproceedings{C. Durelli_Pogliani_Miele_Plessl_Riebler_Vaz_D. Santambrogio_Bolchini_2014, title={Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach}, DOI={<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>}, booktitle={Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)}, publisher={IEEE}, author={C. Durelli, Gianluca and Pogliani, Marcello and Miele, Antonio and Plessl, Christian and Riebler, Heinrich and Vaz, Gavin Francis and D. Santambrogio, Marco and Bolchini, Cristiana}, year={2014}, pages={142–149} }","mla":"C. Durelli, Gianluca, et al. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, IEEE, 2014, pp. 142–49, doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","short":"G. C. Durelli, M. Pogliani, A. Miele, C. Plessl, H. Riebler, G.F. Vaz, M. D. Santambrogio, C. Bolchini, in: Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA), IEEE, 2014, pp. 142–149.","apa":"C. Durelli, G., Pogliani, M., Miele, A., Plessl, C., Riebler, H., Vaz, G. F., D. Santambrogio, M., &#38; Bolchini, C. (2014). Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–149. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>","ieee":"G. C. Durelli <i>et al.</i>, “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach,” in <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 2014, pp. 142–149, doi: <a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>.","chicago":"C. Durelli, Gianluca, Marcello Pogliani, Antonio Miele, Christian Plessl, Heinrich Riebler, Gavin Francis Vaz, Marco D. Santambrogio, and Cristiana Bolchini. “Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach.” In <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>, 142–49. IEEE, 2014. <a href=\"https://doi.org/10.1109/ISPA.2014.27\">https://doi.org/10.1109/ISPA.2014.27</a>.","ama":"C. Durelli G, Pogliani M, Miele A, et al. Runtime Resource Management in Heterogeneous System Architectures: The SAVE Approach. In: <i>Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)</i>. IEEE; 2014:142-149. doi:<a href=\"https://doi.org/10.1109/ISPA.2014.27\">10.1109/ISPA.2014.27</a>"},"quality_controlled":"1","language":[{"iso":"eng"}],"_id":"1778","project":[{"grant_number":"610996","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","_id":"34"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","status":"public","publication":"Proc. Int. Symp. on Parallel and Distributed Processing with Applications (ISPA)","type":"conference"},{"page":"1-8","citation":{"ama":"Vaz GF, Riebler H, Kenter T, Plessl C. Deferring Accelerator Offloading Decisions to Application Runtime. In: <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>. IEEE; 2014:1-8. doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>","chicago":"Vaz, Gavin Francis, Heinrich Riebler, Tobias Kenter, and Christian Plessl. “Deferring Accelerator Offloading Decisions to Application Runtime.” In <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. IEEE, 2014. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>.","ieee":"G. F. Vaz, H. Riebler, T. Kenter, and C. Plessl, “Deferring Accelerator Offloading Decisions to Application Runtime,” in <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 2014, pp. 1–8, doi: <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","bibtex":"@inproceedings{Vaz_Riebler_Kenter_Plessl_2014, title={Deferring Accelerator Offloading Decisions to Application Runtime}, DOI={<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, publisher={IEEE}, author={Vaz, Gavin Francis and Riebler, Heinrich and Kenter, Tobias and Plessl, Christian}, year={2014}, pages={1–8} }","short":"G.F. Vaz, H. Riebler, T. Kenter, C. Plessl, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), IEEE, 2014, pp. 1–8.","mla":"Vaz, Gavin Francis, et al. “Deferring Accelerator Offloading Decisions to Application Runtime.” <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, IEEE, 2014, pp. 1–8, doi:<a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">10.1109/ReConFig.2014.7032509</a>.","apa":"Vaz, G. F., Riebler, H., Kenter, T., &#38; Plessl, C. (2014). Deferring Accelerator Offloading Decisions to Application Runtime. <i>Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)</i>, 1–8. <a href=\"https://doi.org/10.1109/ReConFig.2014.7032509\">https://doi.org/10.1109/ReConFig.2014.7032509</a>"},"has_accepted_license":"1","doi":"10.1109/ReConFig.2014.7032509","date_updated":"2023-09-26T13:37:02Z","author":[{"first_name":"Gavin Francis","full_name":"Vaz, Gavin Francis","id":"30332","last_name":"Vaz"},{"first_name":"Heinrich","last_name":"Riebler","id":"8961","full_name":"Riebler, Heinrich"},{"id":"3145","full_name":"Kenter, Tobias","last_name":"Kenter","first_name":"Tobias"},{"first_name":"Christian","orcid":"0000-0001-5728-9982","last_name":"Plessl","id":"16153","full_name":"Plessl, Christian"}],"status":"public","type":"conference","file_date_updated":"2018-03-16T11:29:52Z","_id":"439","project":[{"_id":"1","name":"SFB 901","grant_number":"160364472"},{"_id":"14","name":"SFB 901 - Subprojekt C2","grant_number":"160364472"},{"_id":"4","name":"SFB 901 - Project Area C"},{"_id":"34","name":"Self-Adaptive Virtualisation-Aware High-Performance/Low-Energy Heterogeneous System Architectures","grant_number":"610996"}],"department":[{"_id":"27"},{"_id":"518"},{"_id":"78"}],"user_id":"15278","year":"2014","quality_controlled":"1","title":"Deferring Accelerator Offloading Decisions to Application Runtime","publisher":"IEEE","date_created":"2017-10-17T12:42:17Z","abstract":[{"text":"Reconfigurable architectures provide an opportunityto accelerate a wide range of applications, frequentlyby exploiting data-parallelism, where the same operations arehomogeneously executed on a (large) set of data. However, whenthe sequential code is executed on a host CPU and only dataparallelloops are executed on an FPGA coprocessor, a sufficientlylarge number of loop iterations (trip counts) is required, such thatthe control- and data-transfer overheads to the coprocessor canbe amortized. However, the trip count of large data-parallel loopsis frequently not known at compile time, but only at runtime justbefore entering a loop. Therefore, we propose to generate codeboth for the CPU and the coprocessor, and to defer the decisionwhere to execute the appropriate code to the runtime of theapplication when the trip count of the loop can be determinedjust at runtime. We demonstrate how an LLVM compiler basedtoolflow can automatically insert appropriate decision blocks intothe application code. Analyzing popular benchmark suites, weshow that this kind of runtime decisions is often applicable. Thepractical feasibility of our approach is demonstrated by a toolflowthat automatically identifies loops suitable for vectorization andgenerates code for the FPGA coprocessor of a Convey HC-1. Thetoolflow adds decisions based on a comparison of the runtimecomputedtrip counts to thresholds for specific loops and alsoincludes support to move just the required data to the coprocessor.We evaluate the integrated toolflow with characteristic loopsexecuted on different input data sizes.","lang":"eng"}],"file":[{"success":1,"relation":"main_file","content_type":"application/pdf","file_size":557362,"access_level":"closed","file_id":"1353","file_name":"439-plessl14a_reconfig.pdf","date_updated":"2018-03-16T11:29:52Z","creator":"florida","date_created":"2018-03-16T11:29:52Z"}],"publication":"Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)","ddc":["040"],"language":[{"iso":"eng"}]},{"status":"public","type":"conference","publication":"Proc. 4th IEEE Workshop on Self-Organizing Real-Time Systems (SORT) 2013","language":[{"iso":"eng"}],"user_id":"21240","department":[{"_id":"672"}],"_id":"25292","citation":{"apa":"Rammig, F.-J., Stahl, K., &#38; Vaz, G. F. (2013). A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems. <i>Proc. 4th IEEE Workshop on Self-Organizing Real-Time Systems (SORT) 2013</i>.","short":"F.-J. Rammig, K. Stahl, G.F. Vaz, in: Proc. 4th IEEE Workshop on Self-Organizing Real-Time Systems (SORT) 2013, IEEE, 2013.","mla":"Rammig, Franz-Josef, et al. “A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems.” <i>Proc. 4th IEEE Workshop on Self-Organizing Real-Time Systems (SORT) 2013</i>, IEEE, 2013.","bibtex":"@inproceedings{Rammig_Stahl_Vaz_2013, title={A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems}, booktitle={Proc. 4th IEEE Workshop on Self-Organizing Real-Time Systems (SORT) 2013}, publisher={IEEE}, author={Rammig, Franz-Josef and Stahl, Katharina and Vaz, Gavin Francis}, year={2013} }","ieee":"F.-J. Rammig, K. Stahl, and G. F. Vaz, “A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems,” 2013.","chicago":"Rammig, Franz-Josef, Katharina Stahl, and Gavin Francis Vaz. “A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems.” In <i>Proc. 4th IEEE Workshop on Self-Organizing Real-Time Systems (SORT) 2013</i>. IEEE, 2013.","ama":"Rammig F-J, Stahl K, Vaz GF. A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems. In: <i>Proc. 4th IEEE Workshop on Self-Organizing Real-Time Systems (SORT) 2013</i>. IEEE; 2013."},"year":"2013","title":"A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems","date_created":"2021-10-04T12:29:09Z","author":[{"last_name":"Rammig","full_name":"Rammig, Franz-Josef","first_name":"Franz-Josef"},{"first_name":"Katharina","last_name":"Stahl","full_name":"Stahl, Katharina"},{"last_name":"Vaz","id":"30332","full_name":"Vaz, Gavin Francis","first_name":"Gavin Francis"}],"publisher":"IEEE","date_updated":"2022-01-06T06:56:59Z"},{"user_id":"24135","department":[{"_id":"70"}],"_id":"1785","type":"conference","publication":"IEEE Int. Symp. on Object/component/service-oriented Real-time distributed Computing (ISORC)","status":"public","author":[{"first_name":"Franz","last_name":"Rammig","full_name":"Rammig, Franz"},{"last_name":"Stahl","full_name":"Stahl, Katharina","first_name":"Katharina"},{"first_name":"Gavin Francis","last_name":"Vaz","full_name":"Vaz, Gavin Francis","id":"30332"}],"date_created":"2018-03-26T14:46:48Z","publisher":"IEEE","date_updated":"2022-01-06T06:53:20Z","doi":"10.1109/ISORC.2013.6913240","title":"A framework for enhancing dependability in self-x systems by Artificial Immune Systems","citation":{"ieee":"F. Rammig, K. Stahl, and G. F. Vaz, “A framework for enhancing dependability in self-x systems by Artificial Immune Systems,” in <i>IEEE Int. Symp. on Object/component/service-oriented Real-time distributed Computing (ISORC)</i>, 2013, pp. 1–10.","chicago":"Rammig, Franz, Katharina Stahl, and Gavin Francis Vaz. “A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems.” In <i>IEEE Int. Symp. on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)</i>, 1–10. IEEE, 2013. <a href=\"https://doi.org/10.1109/ISORC.2013.6913240\">https://doi.org/10.1109/ISORC.2013.6913240</a>.","ama":"Rammig F, Stahl K, Vaz GF. A framework for enhancing dependability in self-x systems by Artificial Immune Systems. In: <i>IEEE Int. Symp. on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)</i>. IEEE; 2013:1-10. doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913240\">10.1109/ISORC.2013.6913240</a>","bibtex":"@inproceedings{Rammig_Stahl_Vaz_2013, title={A framework for enhancing dependability in self-x systems by Artificial Immune Systems}, DOI={<a href=\"https://doi.org/10.1109/ISORC.2013.6913240\">10.1109/ISORC.2013.6913240</a>}, booktitle={IEEE Int. Symp. on Object/component/service-oriented Real-time distributed Computing (ISORC)}, publisher={IEEE}, author={Rammig, Franz and Stahl, Katharina and Vaz, Gavin Francis}, year={2013}, pages={1–10} }","mla":"Rammig, Franz, et al. “A Framework for Enhancing Dependability in Self-x Systems by Artificial Immune Systems.” <i>IEEE Int. Symp. on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC)</i>, IEEE, 2013, pp. 1–10, doi:<a href=\"https://doi.org/10.1109/ISORC.2013.6913240\">10.1109/ISORC.2013.6913240</a>.","short":"F. Rammig, K. Stahl, G.F. Vaz, in: IEEE Int. Symp. on Object/Component/Service-Oriented Real-Time Distributed Computing (ISORC), IEEE, 2013, pp. 1–10.","apa":"Rammig, F., Stahl, K., &#38; Vaz, G. F. (2013). A framework for enhancing dependability in self-x systems by Artificial Immune Systems. In <i>IEEE Int. Symp. on Object/component/service-oriented Real-time distributed Computing (ISORC)</i> (pp. 1–10). IEEE. <a href=\"https://doi.org/10.1109/ISORC.2013.6913240\">https://doi.org/10.1109/ISORC.2013.6913240</a>"},"page":"1-10","year":"2013"}]