[{"year":"2021","issue":"9","title":"Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS","publisher":"Institute of Electrical and Electronics Engineers (IEEE)","date_created":"2022-01-10T13:51:36Z","abstract":[{"text":"This paper investigates an ultra-broadband sampling technique based on charge sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration times. The charge sampling technique is mathematically analyzed in detail and compared to conventional switched-capacitor sampling. The mathematical analysis allows to predict the sampler bandwidth as well as the degradation of sampling precision due to analog circuit impairments such as integrator gain error, integration capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore, design, simulation, and measurement results of an ultra-broadband charge sampler IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits (ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results suggest that charge sampling using an IHC is a viable concept for ultra-broadband sampling.","lang":"eng"}],"publication":"IEEE Transactions on Circuits and Systems I: Regular Papers","keyword":["Electrical and Electronic Engineering"],"language":[{"iso":"eng"}],"intvolume":"        68","page":"3668-3681","citation":{"apa":"Wu, L., &#38; Scheytt, J. C. (2021). Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS. <i>IEEE Transactions on Circuits and Systems I: Regular Papers</i>, <i>68</i>(9), 3668–3681. <a href=\"https://doi.org/10.1109/tcsi.2021.3094428\">https://doi.org/10.1109/tcsi.2021.3094428</a>","short":"L. Wu, J.C. Scheytt, IEEE Transactions on Circuits and Systems I: Regular Papers 68 (2021) 3668–3681.","bibtex":"@article{Wu_Scheytt_2021, title={Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS}, volume={68}, DOI={<a href=\"https://doi.org/10.1109/tcsi.2021.3094428\">10.1109/tcsi.2021.3094428</a>}, number={9}, journal={IEEE Transactions on Circuits and Systems I: Regular Papers}, publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Wu, Liang and Scheytt, J. Christoph}, year={2021}, pages={3668–3681} }","mla":"Wu, Liang, and J. Christoph Scheytt. “Analysis and Design of a Charge Sampler With 70-GHz 1-DB Bandwidth in 130-Nm SiGe BiCMOS.” <i>IEEE Transactions on Circuits and Systems I: Regular Papers</i>, vol. 68, no. 9, Institute of Electrical and Electronics Engineers (IEEE), 2021, pp. 3668–81, doi:<a href=\"https://doi.org/10.1109/tcsi.2021.3094428\">10.1109/tcsi.2021.3094428</a>.","ama":"Wu L, Scheytt JC. Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS. <i>IEEE Transactions on Circuits and Systems I: Regular Papers</i>. 2021;68(9):3668-3681. doi:<a href=\"https://doi.org/10.1109/tcsi.2021.3094428\">10.1109/tcsi.2021.3094428</a>","ieee":"L. Wu and J. C. Scheytt, “Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS,” <i>IEEE Transactions on Circuits and Systems I: Regular Papers</i>, vol. 68, no. 9, pp. 3668–3681, 2021, doi: <a href=\"https://doi.org/10.1109/tcsi.2021.3094428\">10.1109/tcsi.2021.3094428</a>.","chicago":"Wu, Liang, and J. Christoph Scheytt. “Analysis and Design of a Charge Sampler With 70-GHz 1-DB Bandwidth in 130-Nm SiGe BiCMOS.” <i>IEEE Transactions on Circuits and Systems I: Regular Papers</i> 68, no. 9 (2021): 3668–81. <a href=\"https://doi.org/10.1109/tcsi.2021.3094428\">https://doi.org/10.1109/tcsi.2021.3094428</a>."},"publication_identifier":{"issn":["1549-8328","1558-0806"]},"publication_status":"published","related_material":{"link":[{"relation":"confirmation","url":"https://ieeexplore.ieee.org/document/9482511/authors#authors"}]},"doi":"10.1109/tcsi.2021.3094428","date_updated":"2022-01-10T13:53:08Z","volume":68,"author":[{"first_name":"Liang","last_name":"Wu","full_name":"Wu, Liang","id":"30401"},{"first_name":"J. Christoph","last_name":"Scheytt","id":"37144","full_name":"Scheytt, J. Christoph"}],"status":"public","type":"journal_article","_id":"29210","department":[{"_id":"58"}],"user_id":"15931"},{"language":[{"iso":"eng"}],"_id":"52664","user_id":"5786","series_title":"HNI-Verlagsschriftreihe","department":[{"_id":"26"}],"status":"public","type":"dissertation","title":"Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler mit zeitversetzter Abtastung","date_updated":"2024-04-02T09:47:49Z","author":[{"first_name":"Liang","full_name":"Wu, Liang","id":"30401","last_name":"Wu"}],"date_created":"2024-03-20T09:53:23Z","volume":402,"year":"2021","citation":{"apa":"Wu, L. (2021). <i>Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler mit zeitversetzter Abtastung</i> (Vol. 402).","mla":"Wu, Liang. <i>Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler Mit Zeitversetzter Abtastung</i>. 2021.","short":"L. Wu, Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler Mit Zeitversetzter Abtastung, 2021.","bibtex":"@book{Wu_2021, series={HNI-Verlagsschriftreihe}, title={Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler mit zeitversetzter Abtastung}, volume={402}, author={Wu, Liang}, year={2021}, collection={HNI-Verlagsschriftreihe} }","ama":"Wu L. <i>Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler Mit Zeitversetzter Abtastung</i>. Vol 402.; 2021.","ieee":"L. Wu, <i>Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler mit zeitversetzter Abtastung</i>, vol. 402. 2021.","chicago":"Wu, Liang. <i>Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler Mit Zeitversetzter Abtastung</i>. Vol. 402. HNI-Verlagsschriftreihe, 2021."},"intvolume":"       402","publication_identifier":{"isbn":["978-3-947647-21-7"]}},{"user_id":"44271","department":[{"_id":"58"}],"_id":"24021","language":[{"iso":"eng"}],"type":"conference","publication":"2020 IEEE International Symposium on Circuits and Systems (ISCAS)","status":"public","abstract":[{"text":"This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits both large- and small-signal bandwidth exeeding 60 GHz. It achieves an effective number of bits (ENOB) of 7 bit at 34 GHz input frequency and an ENOB of >5 bit over the whole input frequency bandwidth at sampling rate of 10 GS/s. Much higher sampling rates are possible but lead to somewhat worse performance. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 78 mA from a -4.8 V supply voltage, dissipating 375 mW.","lang":"eng"}],"date_created":"2021-09-09T11:50:12Z","author":[{"first_name":"Liang","id":"30401","full_name":"Wu, Liang","last_name":"Wu"},{"first_name":"Maxim","full_name":"Weizel, Maxim","id":"44271","last_name":"Weizel","orcid":"https://orcid.org/0000-0003-2699-9839"},{"first_name":"Christoph","id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt","orcid":"0000-0002-5950-6618 "}],"publisher":"IEEE","date_updated":"2025-02-13T12:08:28Z","doi":"10.1109/ISCAS45731.2020.9180947","conference":{"start_date":"2020.10.12","end_date":"2020.10.14"},"title":"Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology","publication_identifier":{"issn":["2158-1525 "],"isbn":["978-1-7281-3320-1"]},"citation":{"apa":"Wu, L., Weizel, M., &#38; Scheytt, C. (2020). Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. <i>2020 IEEE International Symposium on Circuits and Systems (ISCAS)</i>. <a href=\"https://doi.org/10.1109/ISCAS45731.2020.9180947\">https://doi.org/10.1109/ISCAS45731.2020.9180947</a>","bibtex":"@inproceedings{Wu_Weizel_Scheytt_2020, place={Sevilla, Spain}, title={Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/ISCAS45731.2020.9180947\">10.1109/ISCAS45731.2020.9180947</a>}, booktitle={2020 IEEE International Symposium on Circuits and Systems (ISCAS)}, publisher={IEEE}, author={Wu, Liang and Weizel, Maxim and Scheytt, Christoph}, year={2020} }","mla":"Wu, Liang, et al. “Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 Nm SiGe BiCMOS Technology.” <i>2020 IEEE International Symposium on Circuits and Systems (ISCAS)</i>, IEEE, 2020, doi:<a href=\"https://doi.org/10.1109/ISCAS45731.2020.9180947\">10.1109/ISCAS45731.2020.9180947</a>.","short":"L. Wu, M. Weizel, C. Scheytt, in: 2020 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE, Sevilla, Spain, 2020.","ieee":"L. Wu, M. Weizel, and C. Scheytt, “Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology,” 2020, doi: <a href=\"https://doi.org/10.1109/ISCAS45731.2020.9180947\">10.1109/ISCAS45731.2020.9180947</a>.","chicago":"Wu, Liang, Maxim Weizel, and Christoph Scheytt. “Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 Nm SiGe BiCMOS Technology.” In <i>2020 IEEE International Symposium on Circuits and Systems (ISCAS)</i>. Sevilla, Spain: IEEE, 2020. <a href=\"https://doi.org/10.1109/ISCAS45731.2020.9180947\">https://doi.org/10.1109/ISCAS45731.2020.9180947</a>.","ama":"Wu L, Weizel M, Scheytt C. Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. In: <i>2020 IEEE International Symposium on Circuits and Systems (ISCAS)</i>. IEEE; 2020. doi:<a href=\"https://doi.org/10.1109/ISCAS45731.2020.9180947\">10.1109/ISCAS45731.2020.9180947</a>"},"place":"Sevilla, Spain","year":"2020"},{"year":"2019","place":"Genova, Italy","citation":{"ieee":"L. Wu, M. Weizel, and C. Scheytt, “A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology,” 2019, doi: <a href=\"https://doi.org/10.1109/ICECS46596.2019.8965046\">10.1109/ICECS46596.2019.8965046</a>.","chicago":"Wu, Liang, Maxim Weizel, and Christoph Scheytt. “A 70 GHz Small-Signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 Nm SiGe BiCMOS Technology.” In <i>26th IEEE International Conference on Electronics Circuits and Systems (ICECS)</i>. Genova, Italy, 2019. <a href=\"https://doi.org/10.1109/ICECS46596.2019.8965046\">https://doi.org/10.1109/ICECS46596.2019.8965046</a>.","ama":"Wu L, Weizel M, Scheytt C. A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. In: <i>26th IEEE International Conference on Electronics Circuits and Systems (ICECS)</i>. ; 2019. doi:<a href=\"https://doi.org/10.1109/ICECS46596.2019.8965046\">10.1109/ICECS46596.2019.8965046</a>","bibtex":"@inproceedings{Wu_Weizel_Scheytt_2019, place={Genova, Italy}, title={A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/ICECS46596.2019.8965046\">10.1109/ICECS46596.2019.8965046</a>}, booktitle={26th IEEE International Conference on Electronics Circuits and Systems (ICECS)}, author={Wu, Liang and Weizel, Maxim and Scheytt, Christoph}, year={2019} }","mla":"Wu, Liang, et al. “A 70 GHz Small-Signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 Nm SiGe BiCMOS Technology.” <i>26th IEEE International Conference on Electronics Circuits and Systems (ICECS)</i>, 2019, doi:<a href=\"https://doi.org/10.1109/ICECS46596.2019.8965046\">10.1109/ICECS46596.2019.8965046</a>.","short":"L. Wu, M. Weizel, C. Scheytt, in: 26th IEEE International Conference on Electronics Circuits and Systems (ICECS), Genova, Italy, 2019.","apa":"Wu, L., Weizel, M., &#38; Scheytt, C. (2019). A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. <i>26th IEEE International Conference on Electronics Circuits and Systems (ICECS)</i>. <a href=\"https://doi.org/10.1109/ICECS46596.2019.8965046\">https://doi.org/10.1109/ICECS46596.2019.8965046</a>"},"date_updated":"2025-02-13T12:09:29Z","author":[{"last_name":"Wu","id":"30401","full_name":"Wu, Liang","first_name":"Liang"},{"first_name":"Maxim","last_name":"Weizel","orcid":"https://orcid.org/0000-0003-2699-9839","full_name":"Weizel, Maxim","id":"44271"},{"first_name":"Christoph","full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt","orcid":"0000-0002-5950-6618 "}],"date_created":"2021-09-09T12:26:06Z","title":"A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology","doi":"10.1109/ICECS46596.2019.8965046","conference":{"start_date":"2019.11.27","end_date":"2019.11.29"},"type":"conference","publication":"26th IEEE International Conference on Electronics Circuits and Systems (ICECS)","abstract":[{"lang":"eng","text":"This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower (SEF) topology. The THA exhibits a record 3dB small-signal bandwidth of 70 GHz. With the high sampling rate of 40 GS/s, it achieves an effective number of bits (ENOB) of 7.5 bit at 1 GHz input frequency and an ENOB of >5 bit up to 15 GHz input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP (SG13G2). It draws 110 mA from a -4 V supply voltage, dissipating 440 mW."}],"status":"public","_id":"24052","user_id":"44271","department":[{"_id":"58"}],"language":[{"iso":"eng"}]},{"date_updated":"2025-02-13T12:09:17Z","date_created":"2021-09-09T12:26:04Z","author":[{"first_name":"Liang","id":"30401","full_name":"Wu, Liang","last_name":"Wu"},{"orcid":"https://orcid.org/0000-0003-2699-9839","last_name":"Weizel","full_name":"Weizel, Maxim","id":"44271","first_name":"Maxim"},{"orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144","first_name":"Christoph"}],"title":"70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology","conference":{"end_date":"2019.12.13","location":"Singapore ","start_date":"2019.12.10"},"doi":"10.1109/APMC46564.2019.9038239","year":"2019","citation":{"chicago":"Wu, Liang, Maxim Weizel, and Christoph Scheytt. “70 GHz Large-Signal Bandwidth Sampler Using Current-Mode Integrate-and-Hold Circuit in 130 Nm SiGe BiCMOS Technology.” In <i>Asia-Pacific Microwave Conference (APMC)</i>, 2019. <a href=\"https://doi.org/10.1109/APMC46564.2019.9038239\">https://doi.org/10.1109/APMC46564.2019.9038239</a>.","ieee":"L. Wu, M. Weizel, and C. Scheytt, “70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology,” Singapore , 2019, doi: <a href=\"https://doi.org/10.1109/APMC46564.2019.9038239\">10.1109/APMC46564.2019.9038239</a>.","ama":"Wu L, Weizel M, Scheytt C. 70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology. In: <i>Asia-Pacific Microwave Conference (APMC)</i>. ; 2019. doi:<a href=\"https://doi.org/10.1109/APMC46564.2019.9038239\">10.1109/APMC46564.2019.9038239</a>","short":"L. Wu, M. Weizel, C. Scheytt, in: Asia-Pacific Microwave Conference (APMC), 2019.","bibtex":"@inproceedings{Wu_Weizel_Scheytt_2019, title={70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology}, DOI={<a href=\"https://doi.org/10.1109/APMC46564.2019.9038239\">10.1109/APMC46564.2019.9038239</a>}, booktitle={Asia-Pacific Microwave Conference (APMC)}, author={Wu, Liang and Weizel, Maxim and Scheytt, Christoph}, year={2019} }","mla":"Wu, Liang, et al. “70 GHz Large-Signal Bandwidth Sampler Using Current-Mode Integrate-and-Hold Circuit in 130 Nm SiGe BiCMOS Technology.” <i>Asia-Pacific Microwave Conference (APMC)</i>, 2019, doi:<a href=\"https://doi.org/10.1109/APMC46564.2019.9038239\">10.1109/APMC46564.2019.9038239</a>.","apa":"Wu, L., Weizel, M., &#38; Scheytt, C. (2019). 70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology. <i>Asia-Pacific Microwave Conference (APMC)</i>. <a href=\"https://doi.org/10.1109/APMC46564.2019.9038239\">https://doi.org/10.1109/APMC46564.2019.9038239</a>"},"_id":"24049","department":[{"_id":"58"}],"user_id":"44271","language":[{"iso":"eng"}],"publication":"Asia-Pacific Microwave Conference (APMC)","type":"conference","abstract":[{"text":"This paper presents a broadband sampler IC using a current-mode integrated-and-hold-circuit (IHC) as sampling circuit. The sampler IC exhibits 1dB large-signal bandwidth of 70 GHz and excellent signal integrity on hold-mode. With a sampling rate of 5 GS/s, it achieves effective number of bits (ENOB) of 6 bit at 9.9 GHz input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP.","lang":"eng"}],"status":"public"},{"title":"Analog fault simulation automation at schematic level with random sampling techniques","conference":{"start_date":"2018.04.09","end_date":"2018.04.12"},"doi":"10.1109/DTIS.2018.8368549","publisher":"IEEE","date_updated":"2022-01-06T06:56:09Z","author":[{"first_name":"Liang","last_name":"Wu","id":"30401","full_name":"Wu, Liang"},{"full_name":"Hussain, Mohammad Khizer","last_name":"Hussain","first_name":"Mohammad Khizer"},{"first_name":"Saed","last_name":"Abughannam","full_name":"Abughannam, Saed","id":"37628"},{"full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller","first_name":"Wolfgang"},{"id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt","first_name":"Christoph"},{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"}],"date_created":"2021-09-13T07:38:03Z","year":"2018","place":"Italy/Taormina","citation":{"apa":"Wu, L., Hussain, M. K., Abughannam, S., Müller, W., Scheytt, C., &#38; Ecker, W. (2018). Analog fault simulation automation at schematic level with random sampling techniques. <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">https://doi.org/10.1109/DTIS.2018.8368549</a>","mla":"Wu, Liang, et al. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>, IEEE, 2018, doi:<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>.","bibtex":"@inproceedings{Wu_Hussain_Abughannam_Müller_Scheytt_Ecker_2018, place={Italy/Taormina}, title={Analog fault simulation automation at schematic level with random sampling techniques}, DOI={<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>}, booktitle={2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) }, publisher={IEEE}, author={Wu, Liang and Hussain, Mohammad Khizer and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang}, year={2018} }","short":"L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.","ama":"Wu L, Hussain MK, Abughannam S, Müller W, Scheytt C, Ecker W. Analog fault simulation automation at schematic level with random sampling techniques. In: <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. IEEE; 2018. doi:<a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>","ieee":"L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “Analog fault simulation automation at schematic level with random sampling techniques,” 2018, doi: <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">10.1109/DTIS.2018.8368549</a>.","chicago":"Wu, Liang, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang Ecker. “Analog Fault Simulation Automation at Schematic Level with Random Sampling Techniques.” In <i>2018 13th International Conference on Design &#38; Technology of Integrated Systems In Nanoscale Era (DTIS)) </i>. Italy/Taormina: IEEE, 2018. <a href=\"https://doi.org/10.1109/DTIS.2018.8368549\">https://doi.org/10.1109/DTIS.2018.8368549</a>."},"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/8368549","relation":"confirmation"}]},"language":[{"iso":"eng"}],"_id":"24196","user_id":"15931","department":[{"_id":"58"}],"abstract":[{"lang":"eng","text":"This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation."}],"status":"public","type":"conference","publication":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)) "},{"publication_date":"27.05.2020","_id":"24198","user_id":"15931","department":[{"_id":"58"}],"type":"patent","status":"public","date_updated":"2022-01-06T06:56:09Z","ipc":"H03K 3/42","author":[{"first_name":"Christoph","id":"37144","full_name":"Scheytt, Christoph","last_name":"Scheytt"},{"id":"30401","full_name":"Wu, Liang","last_name":"Wu","first_name":"Liang"}],"date_created":"2021-09-13T07:38:06Z","ipn":"EP000003656056A1","title":"Integrier‐ und Halte‐Schaltung ","application_number":"18756368","related_material":{"link":[{"relation":"confirmation","url":"https://depatisnet.dpma.de/DepatisNet/depatisnet?action=bibdat&docid=EP000003656056A1"}]},"year":"2018","application_date":"16.07.2018","citation":{"ama":"Scheytt C, Wu L. Integrier‐ und Halte‐Schaltung . Published online 2018.","ieee":"C. Scheytt and L. Wu, “Integrier‐ und Halte‐Schaltung .” 2018.","chicago":"Scheytt, Christoph, and Liang Wu. “Integrier‐ Und Halte‐Schaltung ,” 2018.","apa":"Scheytt, C., &#38; Wu, L. (2018). <i>Integrier‐ und Halte‐Schaltung </i>.","bibtex":"@article{Scheytt_Wu_2018, title={Integrier‐ und Halte‐Schaltung }, author={Scheytt, Christoph and Wu, Liang}, year={2018} }","mla":"Scheytt, Christoph, and Liang Wu. <i>Integrier‐ Und Halte‐Schaltung </i>. 2018.","short":"C. Scheytt, L. Wu, (2018)."}},{"page":"68","citation":{"ieee":"L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study,” in <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 2017, p. 68.","chicago":"Wu, Liang, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang Ecker. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study.” In <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 68. Lausanne, Switzerland, 2017.","ama":"Wu L, Abughannam S, Müller W, Scheytt C, Ecker W. SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study. In: <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)</i>. ; 2017:68.","short":"L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017, p. 68.","mla":"Wu, Liang, et al. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study.” <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 2017, p. 68.","bibtex":"@inproceedings{Wu_Abughannam_Müller_Scheytt_Ecker_2017, place={Lausanne, Switzerland}, title={SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study}, booktitle={2nd Workshop on Resiliency in Embedded Electronic Systems (REES)}, author={Wu, Liang and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang}, year={2017}, pages={68} }","apa":"Wu, L., Abughannam, S., Müller, W., Scheytt, C., &#38; Ecker, W. (2017). SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study. <i>2nd Workshop on Resiliency in Embedded Electronic Systems (REES)</i>, 68."},"place":"Lausanne, Switzerland","year":"2017","related_material":{"link":[{"url":"https://past.date-conference.com/date17/conference/workshop-w05","relation":"confirmation"}]},"title":"SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case Study","author":[{"first_name":"Liang","last_name":"Wu","id":"30401","full_name":"Wu, Liang"},{"last_name":"Abughannam","id":"37628","full_name":"Abughannam, Saed","first_name":"Saed"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"last_name":"Scheytt","id":"37144","full_name":"Scheytt, Christoph","first_name":"Christoph"},{"full_name":"Ecker, Wolfgang","last_name":"Ecker","first_name":"Wolfgang"}],"date_created":"2021-09-13T08:20:39Z","date_updated":"2022-01-06T06:56:13Z","status":"public","abstract":[{"lang":"eng","text":"This paper presents the design flow of using \r\nsampling technique for fault injection on sche-\r\nmatic level. The parameters used in the docu-\r\nment to calculate the likelihood could be modi-\r\nfied by using more realistic data from the fab. \r\nWith the help of the fault simulator, the whole \r\ndesign flow of the fault effect simulation can be \r\nrealized automatically."}],"publication":"2nd Workshop on Resiliency in Embedded Electronic Systems (REES)","type":"conference","language":[{"iso":"eng"}],"department":[{"_id":"58"}],"user_id":"15931","_id":"24223"},{"publication":"Analog 2016 - VDE","type":"conference","status":"public","abstract":[{"text":"The design of safety critical systems requires an efficient methodology for an effective fault effect simulation for analog and digital circuits where analog fault injection and fault effect simulation is currently a field of active research and commercial tools are not available yet. This article begins by discussing fault injection strategies for analog circuits applied on a case study with two topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs on the basis of the example of a Wireless Sensor Network (WSN) node, how far different mixed level implementations with Verilog-A and SPICE can affect the simulation time and points out which component consumes the major part of the simulation time.","lang":"eng"}],"department":[{"_id":"58"}],"user_id":"15931","_id":"24263","language":[{"iso":"eng"}],"related_material":{"link":[{"url":"https://ieeexplore.ieee.org/document/7584296/","relation":"confirmation"}]},"publication_identifier":{"isbn":["978-3-8007-4265-3"]},"citation":{"apa":"Abughannam, S., Wu, L., Müller, W., Scheytt, C., Ecker, W., &#38; Novello, C. (2016). Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study. <i>Analog 2016 - VDE</i>.","bibtex":"@inproceedings{Abughannam_Wu_Müller_Scheytt_Ecker_Novello_2016, title={Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study}, booktitle={Analog 2016 - VDE}, author={Abughannam, Saed and Wu, Liang and Müller, Wolfgang and Scheytt, Christoph and Ecker, Wolfgang and Novello, Christiano}, year={2016} }","short":"S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, C. Novello, in: Analog 2016 - VDE, 2016.","mla":"Abughannam, Saed, et al. “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study.” <i>Analog 2016 - VDE</i>, 2016.","ama":"Abughannam S, Wu L, Müller W, Scheytt C, Ecker W, Novello C. Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study. In: <i>Analog 2016 - VDE</i>. ; 2016.","ieee":"S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016.","chicago":"Abughannam, Saed, Liang Wu, Wolfgang Müller, Christoph Scheytt, Wolfgang Ecker, and Christiano Novello. “Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study.” In <i>Analog 2016 - VDE</i>, 2016."},"year":"2016","author":[{"last_name":"Abughannam","id":"37628","full_name":"Abughannam, Saed","first_name":"Saed"},{"first_name":"Liang","id":"30401","full_name":"Wu, Liang","last_name":"Wu"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243","last_name":"Müller"},{"last_name":"Scheytt","full_name":"Scheytt, Christoph","id":"37144","first_name":"Christoph"},{"first_name":"Wolfgang","last_name":"Ecker","full_name":"Ecker, Wolfgang"},{"last_name":"Novello","full_name":"Novello, Christiano","first_name":"Christiano"}],"date_created":"2021-09-13T09:44:29Z","date_updated":"2022-02-17T13:58:08Z","conference":{"end_date":"2016.09.14","start_date":"2016.09.12"},"title":"Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study"},{"date_created":"2021-09-14T07:06:31Z","author":[{"first_name":"Wolfgang","last_name":"Müller","id":"16243","full_name":"Müller, Wolfgang"},{"first_name":"Liang","last_name":"Wu","full_name":"Wu, Liang","id":"30401"},{"first_name":"Christoph","full_name":"Scheytt, Christoph","id":"37144","last_name":"Scheytt"},{"last_name":"Becker","full_name":"Becker, Markus","first_name":"Markus"},{"first_name":"Sven","full_name":"Schoenberg, Sven","last_name":"Schoenberg"}],"date_updated":"2022-02-17T10:08:53Z","title":"On the Correlation of HW Faults and SW Errors","citation":{"ama":"Müller W, Wu L, Scheytt C, Becker M, Schoenberg S. On the Correlation of HW Faults and SW Errors. In: Mueller-Gritschneder D, Müller W, Mitra S, eds. <i>Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)</i>. ; 2015.","chicago":"Müller, Wolfgang, Liang Wu, Christoph Scheytt, Markus Becker, and Sven Schoenberg. “On the Correlation of HW Faults and SW Errors.” In <i>Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)</i>, edited by Daniel Mueller-Gritschneder, Wolfgang Müller, and Subhasish Mitra. Amsterdam, Netherland, 2015.","ieee":"W. Müller, L. Wu, C. Scheytt, M. Becker, and S. Schoenberg, “On the Correlation of HW Faults and SW Errors,” in <i>Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)</i>, 2015.","apa":"Müller, W., Wu, L., Scheytt, C., Becker, M., &#38; Schoenberg, S. (2015). On the Correlation of HW Faults and SW Errors. In D. Mueller-Gritschneder, W. Müller, &#38; S. Mitra (Eds.), <i>Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)</i>.","bibtex":"@inproceedings{Müller_Wu_Scheytt_Becker_Schoenberg_2015, place={Amsterdam, Netherland}, title={On the Correlation of HW Faults and SW Errors}, booktitle={Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)}, author={Müller, Wolfgang and Wu, Liang and Scheytt, Christoph and Becker, Markus and Schoenberg, Sven}, editor={Mueller-Gritschneder, Daniel and Müller, Wolfgang and Mitra, Subhasish}, year={2015} }","short":"W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: D. Mueller-Gritschneder, W. Müller, S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014), Amsterdam, Netherland, 2015.","mla":"Müller, Wolfgang, et al. “On the Correlation of HW Faults and SW Errors.” <i>Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)</i>, edited by Daniel Mueller-Gritschneder et al., 2015."},"place":"Amsterdam, Netherland","year":"2015","department":[{"_id":"58"}],"user_id":"15931","_id":"24289","language":[{"iso":"eng"}],"publication":"Proceedings of the 1st International Workshop on Resiliency in Embedded Electronic Systems (REES 2014)","type":"conference","status":"public","editor":[{"first_name":"Daniel","full_name":"Mueller-Gritschneder, Daniel","last_name":"Mueller-Gritschneder"},{"first_name":"Wolfgang","full_name":"Müller, Wolfgang","last_name":"Müller"},{"first_name":"Subhasish","last_name":"Mitra","full_name":"Mitra, Subhasish"}]}]