---
_id: '29210'
abstract:
- lang: eng
text: This paper investigates an ultra-broadband sampling technique based on charge
sampling using an Integrate-and-Hold Circuit (IHC) and ultra-short integration
times. The charge sampling technique is mathematically analyzed in detail and
compared to conventional switched-capacitor sampling. The mathematical analysis
allows to predict the sampler bandwidth as well as the degradation of sampling
precision due to analog circuit impairments such as integrator gain error, integration
capacitor leakage, hold-mode droop, thermal noise, and clock jitter. Furthermore,
design, simulation, and measurement results of an ultra-broadband charge sampler
IC in SiGe BiCMOS technology are presented. The charge sampler IC achieves a 1dB
bandwidth of 70 GHz. A resolution of better than 5.9 effective number of bits
(ENOB) is measured from 0 to 70 GHz at a sampling rate of 5 GS/s. The results
suggest that charge sampling using an IHC is a viable concept for ultra-broadband
sampling.
author:
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Wu L, Scheytt JC. Analysis and Design of a Charge Sampler With 70-GHz 1-dB
Bandwidth in 130-nm SiGe BiCMOS. IEEE Transactions on Circuits and Systems
I: Regular Papers. 2021;68(9):3668-3681. doi:10.1109/tcsi.2021.3094428'
apa: 'Wu, L., & Scheytt, J. C. (2021). Analysis and Design of a Charge Sampler
With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS. IEEE Transactions on Circuits
and Systems I: Regular Papers, 68(9), 3668–3681. https://doi.org/10.1109/tcsi.2021.3094428'
bibtex: '@article{Wu_Scheytt_2021, title={Analysis and Design of a Charge Sampler
With 70-GHz 1-dB Bandwidth in 130-nm SiGe BiCMOS}, volume={68}, DOI={10.1109/tcsi.2021.3094428},
number={9}, journal={IEEE Transactions on Circuits and Systems I: Regular Papers},
publisher={Institute of Electrical and Electronics Engineers (IEEE)}, author={Wu,
Liang and Scheytt, J. Christoph}, year={2021}, pages={3668–3681} }'
chicago: 'Wu, Liang, and J. Christoph Scheytt. “Analysis and Design of a Charge
Sampler With 70-GHz 1-DB Bandwidth in 130-Nm SiGe BiCMOS.” IEEE Transactions
on Circuits and Systems I: Regular Papers 68, no. 9 (2021): 3668–81. https://doi.org/10.1109/tcsi.2021.3094428.'
ieee: 'L. Wu and J. C. Scheytt, “Analysis and Design of a Charge Sampler With 70-GHz
1-dB Bandwidth in 130-nm SiGe BiCMOS,” IEEE Transactions on Circuits and Systems
I: Regular Papers, vol. 68, no. 9, pp. 3668–3681, 2021, doi: 10.1109/tcsi.2021.3094428.'
mla: 'Wu, Liang, and J. Christoph Scheytt. “Analysis and Design of a Charge Sampler
With 70-GHz 1-DB Bandwidth in 130-Nm SiGe BiCMOS.” IEEE Transactions on Circuits
and Systems I: Regular Papers, vol. 68, no. 9, Institute of Electrical and
Electronics Engineers (IEEE), 2021, pp. 3668–81, doi:10.1109/tcsi.2021.3094428.'
short: 'L. Wu, J.C. Scheytt, IEEE Transactions on Circuits and Systems I: Regular
Papers 68 (2021) 3668–3681.'
date_created: 2022-01-10T13:51:36Z
date_updated: 2022-01-10T13:53:08Z
department:
- _id: '58'
doi: 10.1109/tcsi.2021.3094428
intvolume: ' 68'
issue: '9'
keyword:
- Electrical and Electronic Engineering
language:
- iso: eng
page: 3668-3681
publication: 'IEEE Transactions on Circuits and Systems I: Regular Papers'
publication_identifier:
issn:
- 1549-8328
- 1558-0806
publication_status: published
publisher: Institute of Electrical and Electronics Engineers (IEEE)
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/9482511/authors#authors
status: public
title: Analysis and Design of a Charge Sampler With 70-GHz 1-dB Bandwidth in 130-nm
SiGe BiCMOS
type: journal_article
user_id: '15931'
volume: 68
year: '2021'
...
---
_id: '52664'
author:
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
citation:
ama: Wu L. Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler
Mit Zeitversetzter Abtastung. Vol 402.; 2021.
apa: Wu, L. (2021). Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für
Analog-Digital-Wandler mit zeitversetzter Abtastung (Vol. 402).
bibtex: '@book{Wu_2021, series={HNI-Verlagsschriftreihe}, title={Ultrabreitbandige
Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler mit zeitversetzter
Abtastung}, volume={402}, author={Wu, Liang}, year={2021}, collection={HNI-Verlagsschriftreihe}
}'
chicago: Wu, Liang. Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für
Analog-Digital-Wandler Mit Zeitversetzter Abtastung. Vol. 402. HNI-Verlagsschriftreihe,
2021.
ieee: L. Wu, Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler
mit zeitversetzter Abtastung, vol. 402. 2021.
mla: Wu, Liang. Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler
Mit Zeitversetzter Abtastung. 2021.
short: L. Wu, Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie Für Analog-Digital-Wandler
Mit Zeitversetzter Abtastung, 2021.
date_created: 2024-03-20T09:53:23Z
date_updated: 2024-04-02T09:47:49Z
department:
- _id: '26'
intvolume: ' 402'
language:
- iso: eng
publication_identifier:
isbn:
- 978-3-947647-21-7
series_title: HNI-Verlagsschriftreihe
status: public
title: Ultrabreitbandige Sampler in SiGe-BiCMOS-Technologie für Analog-Digital-Wandler
mit zeitversetzter Abtastung
type: dissertation
user_id: '5786'
volume: 402
year: '2021'
...
---
_id: '24021'
abstract:
- lang: eng
text: This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower
(SEF) topology. The THA exhibits both large- and small-signal bandwidth exeeding
60 GHz. It achieves an effective number of bits (ENOB) of 7 bit at 34 GHz input
frequency and an ENOB of >5 bit over the whole input frequency bandwidth at sampling
rate of 10 GS/s. Much higher sampling rates are possible but lead to somewhat
worse performance. The chip was fabricated in a 130 nm SiGe BiCMOS technology
from IHP (SG13G2). It draws 78 mA from a -4.8 V supply voltage, dissipating 375
mW.
author:
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
- first_name: Maxim
full_name: Weizel, Maxim
id: '44271'
last_name: Weizel
orcid: https://orcid.org/0000-0003-2699-9839
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Wu L, Weizel M, Scheytt C. Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold
Amplifier in 130 nm SiGe BiCMOS Technology. In: 2020 IEEE International Symposium
on Circuits and Systems (ISCAS). IEEE; 2020. doi:10.1109/ISCAS45731.2020.9180947'
apa: Wu, L., Weizel, M., & Scheytt, C. (2020). Above 60 GHz Bandwidth 10 GS/s
Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. 2020
IEEE International Symposium on Circuits and Systems (ISCAS). https://doi.org/10.1109/ISCAS45731.2020.9180947
bibtex: '@inproceedings{Wu_Weizel_Scheytt_2020, place={Sevilla, Spain}, title={Above
60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 nm SiGe
BiCMOS Technology}, DOI={10.1109/ISCAS45731.2020.9180947},
booktitle={2020 IEEE International Symposium on Circuits and Systems (ISCAS)},
publisher={IEEE}, author={Wu, Liang and Weizel, Maxim and Scheytt, Christoph},
year={2020} }'
chicago: 'Wu, Liang, Maxim Weizel, and Christoph Scheytt. “Above 60 GHz Bandwidth
10 GS/s Sampling Rate Track-and-Hold Amplifier in 130 Nm SiGe BiCMOS Technology.”
In 2020 IEEE International Symposium on Circuits and Systems (ISCAS). Sevilla,
Spain: IEEE, 2020. https://doi.org/10.1109/ISCAS45731.2020.9180947.'
ieee: 'L. Wu, M. Weizel, and C. Scheytt, “Above 60 GHz Bandwidth 10 GS/s Sampling
Rate Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology,” 2020, doi: 10.1109/ISCAS45731.2020.9180947.'
mla: Wu, Liang, et al. “Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold
Amplifier in 130 Nm SiGe BiCMOS Technology.” 2020 IEEE International Symposium
on Circuits and Systems (ISCAS), IEEE, 2020, doi:10.1109/ISCAS45731.2020.9180947.
short: 'L. Wu, M. Weizel, C. Scheytt, in: 2020 IEEE International Symposium on Circuits
and Systems (ISCAS), IEEE, Sevilla, Spain, 2020.'
conference:
end_date: 2020.10.14
start_date: 2020.10.12
date_created: 2021-09-09T11:50:12Z
date_updated: 2025-02-13T12:08:28Z
department:
- _id: '58'
doi: 10.1109/ISCAS45731.2020.9180947
language:
- iso: eng
place: Sevilla, Spain
publication: 2020 IEEE International Symposium on Circuits and Systems (ISCAS)
publication_identifier:
isbn:
- 978-1-7281-3320-1
issn:
- '2158-1525 '
publisher: IEEE
status: public
title: Above 60 GHz Bandwidth 10 GS/s Sampling Rate Track-and-Hold Amplifier in 130
nm SiGe BiCMOS Technology
type: conference
user_id: '44271'
year: '2020'
...
---
_id: '24052'
abstract:
- lang: eng
text: This paper presents a broadband track-and-hold amplifier (THA) based on switched-emitter-follower
(SEF) topology. The THA exhibits a record 3dB small-signal bandwidth of 70 GHz.
With the high sampling rate of 40 GS/s, it achieves an effective number of bits
(ENOB) of 7.5 bit at 1 GHz input frequency and an ENOB of >5 bit up to 15 GHz
input frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from
IHP (SG13G2). It draws 110 mA from a -4 V supply voltage, dissipating 440 mW.
author:
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
- first_name: Maxim
full_name: Weizel, Maxim
id: '44271'
last_name: Weizel
orcid: https://orcid.org/0000-0003-2699-9839
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Wu L, Weizel M, Scheytt C. A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold
Amplifier in 130 nm SiGe BiCMOS Technology. In: 26th IEEE International Conference
on Electronics Circuits and Systems (ICECS). ; 2019. doi:10.1109/ICECS46596.2019.8965046'
apa: Wu, L., Weizel, M., & Scheytt, C. (2019). A 70 GHz Small-signal Bandwidth
40 GS/s Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology. 26th IEEE
International Conference on Electronics Circuits and Systems (ICECS). https://doi.org/10.1109/ICECS46596.2019.8965046
bibtex: '@inproceedings{Wu_Weizel_Scheytt_2019, place={Genova, Italy}, title={A
70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm SiGe
BiCMOS Technology}, DOI={10.1109/ICECS46596.2019.8965046},
booktitle={26th IEEE International Conference on Electronics Circuits and Systems
(ICECS)}, author={Wu, Liang and Weizel, Maxim and Scheytt, Christoph}, year={2019}
}'
chicago: Wu, Liang, Maxim Weizel, and Christoph Scheytt. “A 70 GHz Small-Signal
Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 Nm SiGe BiCMOS Technology.”
In 26th IEEE International Conference on Electronics Circuits and Systems (ICECS).
Genova, Italy, 2019. https://doi.org/10.1109/ICECS46596.2019.8965046.
ieee: 'L. Wu, M. Weizel, and C. Scheytt, “A 70 GHz Small-signal Bandwidth 40 GS/s
Track-and-Hold Amplifier in 130 nm SiGe BiCMOS Technology,” 2019, doi: 10.1109/ICECS46596.2019.8965046.'
mla: Wu, Liang, et al. “A 70 GHz Small-Signal Bandwidth 40 GS/s Track-and-Hold Amplifier
in 130 Nm SiGe BiCMOS Technology.” 26th IEEE International Conference on Electronics
Circuits and Systems (ICECS), 2019, doi:10.1109/ICECS46596.2019.8965046.
short: 'L. Wu, M. Weizel, C. Scheytt, in: 26th IEEE International Conference on
Electronics Circuits and Systems (ICECS), Genova, Italy, 2019.'
conference:
end_date: 2019.11.29
start_date: 2019.11.27
date_created: 2021-09-09T12:26:06Z
date_updated: 2025-02-13T12:09:29Z
department:
- _id: '58'
doi: 10.1109/ICECS46596.2019.8965046
language:
- iso: eng
place: Genova, Italy
publication: 26th IEEE International Conference on Electronics Circuits and Systems
(ICECS)
status: public
title: A 70 GHz Small-signal Bandwidth 40 GS/s Track-and-Hold Amplifier in 130 nm
SiGe BiCMOS Technology
type: conference
user_id: '44271'
year: '2019'
...
---
_id: '24049'
abstract:
- lang: eng
text: This paper presents a broadband sampler IC using a current-mode integrated-and-hold-circuit
(IHC) as sampling circuit. The sampler IC exhibits 1dB large-signal bandwidth
of 70 GHz and excellent signal integrity on hold-mode. With a sampling rate of
5 GS/s, it achieves effective number of bits (ENOB) of 6 bit at 9.9 GHz input
frequency. The chip was fabricated in a 130 nm SiGe BiCMOS technology from IHP.
author:
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
- first_name: Maxim
full_name: Weizel, Maxim
id: '44271'
last_name: Weizel
orcid: https://orcid.org/0000-0003-2699-9839
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Wu L, Weizel M, Scheytt C. 70 GHz Large-signal Bandwidth Sampler Using Current-mode
Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology. In: Asia-Pacific
Microwave Conference (APMC). ; 2019. doi:10.1109/APMC46564.2019.9038239'
apa: Wu, L., Weizel, M., & Scheytt, C. (2019). 70 GHz Large-signal Bandwidth
Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology.
Asia-Pacific Microwave Conference (APMC). https://doi.org/10.1109/APMC46564.2019.9038239
bibtex: '@inproceedings{Wu_Weizel_Scheytt_2019, title={70 GHz Large-signal Bandwidth
Sampler Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology},
DOI={10.1109/APMC46564.2019.9038239},
booktitle={Asia-Pacific Microwave Conference (APMC)}, author={Wu, Liang and Weizel,
Maxim and Scheytt, Christoph}, year={2019} }'
chicago: Wu, Liang, Maxim Weizel, and Christoph Scheytt. “70 GHz Large-Signal Bandwidth
Sampler Using Current-Mode Integrate-and-Hold Circuit in 130 Nm SiGe BiCMOS Technology.”
In Asia-Pacific Microwave Conference (APMC), 2019. https://doi.org/10.1109/APMC46564.2019.9038239.
ieee: 'L. Wu, M. Weizel, and C. Scheytt, “70 GHz Large-signal Bandwidth Sampler
Using Current-mode Integrate-and-Hold Circuit in 130 nm SiGe BiCMOS Technology,”
Singapore , 2019, doi: 10.1109/APMC46564.2019.9038239.'
mla: Wu, Liang, et al. “70 GHz Large-Signal Bandwidth Sampler Using Current-Mode
Integrate-and-Hold Circuit in 130 Nm SiGe BiCMOS Technology.” Asia-Pacific
Microwave Conference (APMC), 2019, doi:10.1109/APMC46564.2019.9038239.
short: 'L. Wu, M. Weizel, C. Scheytt, in: Asia-Pacific Microwave Conference (APMC),
2019.'
conference:
end_date: 2019.12.13
location: 'Singapore '
start_date: 2019.12.10
date_created: 2021-09-09T12:26:04Z
date_updated: 2025-02-13T12:09:17Z
department:
- _id: '58'
doi: 10.1109/APMC46564.2019.9038239
language:
- iso: eng
publication: Asia-Pacific Microwave Conference (APMC)
status: public
title: 70 GHz Large-signal Bandwidth Sampler Using Current-mode Integrate-and-Hold
Circuit in 130 nm SiGe BiCMOS Technology
type: conference
user_id: '44271'
year: '2019'
...
---
_id: '24196'
abstract:
- lang: eng
text: This paper presents an approach for analog fault effect simulation automation
based on random fault selection with a high fault coverage of the circuit under
test by means of fault injection and simulation based on advanced sampling techniques.
The random fault selection utilizes the likelihood of the fault occurrence of
different electrical components in the circuit with a confidence level. Defect
models of different devices are analyzed for the calculation of the fault probability.
A case study with our implemented tool demonstrates that likelihood calculation
and fault simulation provides means for efficient fault effect simulation automation.
author:
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
- first_name: Mohammad Khizer
full_name: Hussain, Mohammad Khizer
last_name: Hussain
- first_name: Saed
full_name: Abughannam, Saed
id: '37628'
last_name: Abughannam
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
citation:
ama: 'Wu L, Hussain MK, Abughannam S, Müller W, Scheytt C, Ecker W. Analog fault
simulation automation at schematic level with random sampling techniques. In:
2018 13th International Conference on Design & Technology of Integrated
Systems In Nanoscale Era (DTIS)) . IEEE; 2018. doi:10.1109/DTIS.2018.8368549'
apa: Wu, L., Hussain, M. K., Abughannam, S., Müller, W., Scheytt, C., & Ecker,
W. (2018). Analog fault simulation automation at schematic level with random sampling
techniques. 2018 13th International Conference on Design & Technology of
Integrated Systems In Nanoscale Era (DTIS)) . https://doi.org/10.1109/DTIS.2018.8368549
bibtex: '@inproceedings{Wu_Hussain_Abughannam_Müller_Scheytt_Ecker_2018, place={Italy/Taormina},
title={Analog fault simulation automation at schematic level with random sampling
techniques}, DOI={10.1109/DTIS.2018.8368549},
booktitle={2018 13th International Conference on Design & Technology of Integrated
Systems In Nanoscale Era (DTIS)) }, publisher={IEEE}, author={Wu, Liang and Hussain,
Mohammad Khizer and Abughannam, Saed and Müller, Wolfgang and Scheytt, Christoph
and Ecker, Wolfgang}, year={2018} }'
chicago: 'Wu, Liang, Mohammad Khizer Hussain, Saed Abughannam, Wolfgang Müller,
Christoph Scheytt, and Wolfgang Ecker. “Analog Fault Simulation Automation at
Schematic Level with Random Sampling Techniques.” In 2018 13th International
Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS))
. Italy/Taormina: IEEE, 2018. https://doi.org/10.1109/DTIS.2018.8368549.'
ieee: 'L. Wu, M. K. Hussain, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker,
“Analog fault simulation automation at schematic level with random sampling techniques,”
2018, doi: 10.1109/DTIS.2018.8368549.'
mla: Wu, Liang, et al. “Analog Fault Simulation Automation at Schematic Level with
Random Sampling Techniques.” 2018 13th International Conference on Design &
Technology of Integrated Systems In Nanoscale Era (DTIS)) , IEEE, 2018, doi:10.1109/DTIS.2018.8368549.
short: 'L. Wu, M.K. Hussain, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in:
2018 13th International Conference on Design & Technology of Integrated Systems
In Nanoscale Era (DTIS)) , IEEE, Italy/Taormina, 2018.'
conference:
end_date: 2018.04.12
start_date: 2018.04.09
date_created: 2021-09-13T07:38:03Z
date_updated: 2022-01-06T06:56:09Z
department:
- _id: '58'
doi: 10.1109/DTIS.2018.8368549
language:
- iso: eng
place: Italy/Taormina
publication: '2018 13th International Conference on Design & Technology of Integrated
Systems In Nanoscale Era (DTIS)) '
publisher: IEEE
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/8368549
status: public
title: Analog fault simulation automation at schematic level with random sampling
techniques
type: conference
user_id: '15931'
year: '2018'
...
---
_id: '24198'
application_date: 16.07.2018
application_number: '18756368'
author:
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
citation:
ama: Scheytt C, Wu L. Integrier‐ und Halte‐Schaltung . Published online 2018.
apa: Scheytt, C., & Wu, L. (2018). Integrier‐ und Halte‐Schaltung .
bibtex: '@article{Scheytt_Wu_2018, title={Integrier‐ und Halte‐Schaltung }, author={Scheytt,
Christoph and Wu, Liang}, year={2018} }'
chicago: Scheytt, Christoph, and Liang Wu. “Integrier‐ Und Halte‐Schaltung ,” 2018.
ieee: C. Scheytt and L. Wu, “Integrier‐ und Halte‐Schaltung .” 2018.
mla: Scheytt, Christoph, and Liang Wu. Integrier‐ Und Halte‐Schaltung . 2018.
short: C. Scheytt, L. Wu, (2018).
date_created: 2021-09-13T07:38:06Z
date_updated: 2022-01-06T06:56:09Z
department:
- _id: '58'
ipc: H03K 3/42
ipn: EP000003656056A1
publication_date: 27.05.2020
related_material:
link:
- relation: confirmation
url: https://depatisnet.dpma.de/DepatisNet/depatisnet?action=bibdat&docid=EP000003656056A1
status: public
title: 'Integrier‐ und Halte‐Schaltung '
type: patent
user_id: '15931'
year: '2018'
...
---
_id: '24223'
abstract:
- lang: eng
text: "This paper presents the design flow of using \r\nsampling technique for fault
injection on sche-\r\nmatic level. The parameters used in the docu-\r\nment to
calculate the likelihood could be modi-\r\nfied by using more realistic data from
the fab. \r\nWith the help of the fault simulator, the whole \r\ndesign flow of
the fault effect simulation can be \r\nrealized automatically."
author:
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
- first_name: Saed
full_name: Abughannam, Saed
id: '37628'
last_name: Abughannam
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
citation:
ama: 'Wu L, Abughannam S, Müller W, Scheytt C, Ecker W. SPICE-Level Fault Injection
with Likelihood Weighted Random Sampling - A Case Study. In: 2nd Workshop on
Resiliency in Embedded Electronic Systems (REES). ; 2017:68.'
apa: Wu, L., Abughannam, S., Müller, W., Scheytt, C., & Ecker, W. (2017). SPICE-Level
Fault Injection with Likelihood Weighted Random Sampling - A Case Study. 2nd
Workshop on Resiliency in Embedded Electronic Systems (REES), 68.
bibtex: '@inproceedings{Wu_Abughannam_Müller_Scheytt_Ecker_2017, place={Lausanne,
Switzerland}, title={SPICE-Level Fault Injection with Likelihood Weighted Random
Sampling - A Case Study}, booktitle={2nd Workshop on Resiliency in Embedded Electronic
Systems (REES)}, author={Wu, Liang and Abughannam, Saed and Müller, Wolfgang and
Scheytt, Christoph and Ecker, Wolfgang}, year={2017}, pages={68} }'
chicago: Wu, Liang, Saed Abughannam, Wolfgang Müller, Christoph Scheytt, and Wolfgang
Ecker. “SPICE-Level Fault Injection with Likelihood Weighted Random Sampling -
A Case Study.” In 2nd Workshop on Resiliency in Embedded Electronic Systems
(REES), 68. Lausanne, Switzerland, 2017.
ieee: L. Wu, S. Abughannam, W. Müller, C. Scheytt, and W. Ecker, “SPICE-Level Fault
Injection with Likelihood Weighted Random Sampling - A Case Study,” in 2nd
Workshop on Resiliency in Embedded Electronic Systems (REES), 2017, p. 68.
mla: Wu, Liang, et al. “SPICE-Level Fault Injection with Likelihood Weighted Random
Sampling - A Case Study.” 2nd Workshop on Resiliency in Embedded Electronic
Systems (REES), 2017, p. 68.
short: 'L. Wu, S. Abughannam, W. Müller, C. Scheytt, W. Ecker, in: 2nd Workshop
on Resiliency in Embedded Electronic Systems (REES), Lausanne, Switzerland, 2017,
p. 68.'
date_created: 2021-09-13T08:20:39Z
date_updated: 2022-01-06T06:56:13Z
department:
- _id: '58'
language:
- iso: eng
page: '68'
place: Lausanne, Switzerland
publication: 2nd Workshop on Resiliency in Embedded Electronic Systems (REES)
related_material:
link:
- relation: confirmation
url: https://past.date-conference.com/date17/conference/workshop-w05
status: public
title: SPICE-Level Fault Injection with Likelihood Weighted Random Sampling - A Case
Study
type: conference
user_id: '15931'
year: '2017'
...
---
_id: '24263'
abstract:
- lang: eng
text: The design of safety critical systems requires an efficient methodology for
an effective fault effect simulation for analog and digital circuits where analog
fault injection and fault effect simulation is currently a field of active research
and commercial tools are not available yet. This article begins by discussing
fault injection strategies for analog circuits applied on a case study with two
topologies of a Voltage Controlled Oscillator (VCO). In the second part it performs
on the basis of the example of a Wireless Sensor Network (WSN) node, how far different
mixed level implementations with Verilog-A and SPICE can affect the simulation
time and points out which component consumes the major part of the simulation
time.
author:
- first_name: Saed
full_name: Abughannam, Saed
id: '37628'
last_name: Abughannam
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
- first_name: Christiano
full_name: Novello, Christiano
last_name: Novello
citation:
ama: 'Abughannam S, Wu L, Müller W, Scheytt C, Ecker W, Novello C. Fault Injection
and Mixed-Level Simulation for Analog Circuits - A Case Study. In: Analog 2016
- VDE. ; 2016.'
apa: Abughannam, S., Wu, L., Müller, W., Scheytt, C., Ecker, W., & Novello,
C. (2016). Fault Injection and Mixed-Level Simulation for Analog Circuits - A
Case Study. Analog 2016 - VDE.
bibtex: '@inproceedings{Abughannam_Wu_Müller_Scheytt_Ecker_Novello_2016, title={Fault
Injection and Mixed-Level Simulation for Analog Circuits - A Case Study}, booktitle={Analog
2016 - VDE}, author={Abughannam, Saed and Wu, Liang and Müller, Wolfgang and Scheytt,
Christoph and Ecker, Wolfgang and Novello, Christiano}, year={2016} }'
chicago: Abughannam, Saed, Liang Wu, Wolfgang Müller, Christoph Scheytt, Wolfgang
Ecker, and Christiano Novello. “Fault Injection and Mixed-Level Simulation for
Analog Circuits - A Case Study.” In Analog 2016 - VDE, 2016.
ieee: S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, and C. Novello, “Fault
Injection and Mixed-Level Simulation for Analog Circuits - A Case Study,” 2016.
mla: Abughannam, Saed, et al. “Fault Injection and Mixed-Level Simulation for Analog
Circuits - A Case Study.” Analog 2016 - VDE, 2016.
short: 'S. Abughannam, L. Wu, W. Müller, C. Scheytt, W. Ecker, C. Novello, in: Analog
2016 - VDE, 2016.'
conference:
end_date: 2016.09.14
start_date: 2016.09.12
date_created: 2021-09-13T09:44:29Z
date_updated: 2022-02-17T13:58:08Z
department:
- _id: '58'
language:
- iso: eng
publication: Analog 2016 - VDE
publication_identifier:
isbn:
- 978-3-8007-4265-3
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/7584296/
status: public
title: Fault Injection and Mixed-Level Simulation for Analog Circuits - A Case Study
type: conference
user_id: '15931'
year: '2016'
...
---
_id: '24289'
author:
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Liang
full_name: Wu, Liang
id: '30401'
last_name: Wu
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
- first_name: Markus
full_name: Becker, Markus
last_name: Becker
- first_name: Sven
full_name: Schoenberg, Sven
last_name: Schoenberg
citation:
ama: 'Müller W, Wu L, Scheytt C, Becker M, Schoenberg S. On the Correlation of HW
Faults and SW Errors. In: Mueller-Gritschneder D, Müller W, Mitra S, eds. Proceedings
of the 1st International Workshop on Resiliency in Embedded Electronic Systems
(REES 2014). ; 2015.'
apa: Müller, W., Wu, L., Scheytt, C., Becker, M., & Schoenberg, S. (2015). On
the Correlation of HW Faults and SW Errors. In D. Mueller-Gritschneder, W. Müller,
& S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency
in Embedded Electronic Systems (REES 2014).
bibtex: '@inproceedings{Müller_Wu_Scheytt_Becker_Schoenberg_2015, place={Amsterdam,
Netherland}, title={On the Correlation of HW Faults and SW Errors}, booktitle={Proceedings
of the 1st International Workshop on Resiliency in Embedded Electronic Systems
(REES 2014)}, author={Müller, Wolfgang and Wu, Liang and Scheytt, Christoph and
Becker, Markus and Schoenberg, Sven}, editor={Mueller-Gritschneder, Daniel and
Müller, Wolfgang and Mitra, Subhasish}, year={2015} }'
chicago: Müller, Wolfgang, Liang Wu, Christoph Scheytt, Markus Becker, and Sven
Schoenberg. “On the Correlation of HW Faults and SW Errors.” In Proceedings
of the 1st International Workshop on Resiliency in Embedded Electronic Systems
(REES 2014), edited by Daniel Mueller-Gritschneder, Wolfgang Müller, and Subhasish
Mitra. Amsterdam, Netherland, 2015.
ieee: W. Müller, L. Wu, C. Scheytt, M. Becker, and S. Schoenberg, “On the Correlation
of HW Faults and SW Errors,” in Proceedings of the 1st International Workshop
on Resiliency in Embedded Electronic Systems (REES 2014), 2015.
mla: Müller, Wolfgang, et al. “On the Correlation of HW Faults and SW Errors.” Proceedings
of the 1st International Workshop on Resiliency in Embedded Electronic Systems
(REES 2014), edited by Daniel Mueller-Gritschneder et al., 2015.
short: 'W. Müller, L. Wu, C. Scheytt, M. Becker, S. Schoenberg, in: D. Mueller-Gritschneder,
W. Müller, S. Mitra (Eds.), Proceedings of the 1st International Workshop on Resiliency
in Embedded Electronic Systems (REES 2014), Amsterdam, Netherland, 2015.'
date_created: 2021-09-14T07:06:31Z
date_updated: 2022-02-17T10:08:53Z
department:
- _id: '58'
editor:
- first_name: Daniel
full_name: Mueller-Gritschneder, Daniel
last_name: Mueller-Gritschneder
- first_name: Wolfgang
full_name: Müller, Wolfgang
last_name: Müller
- first_name: Subhasish
full_name: Mitra, Subhasish
last_name: Mitra
language:
- iso: eng
place: Amsterdam, Netherland
publication: Proceedings of the 1st International Workshop on Resiliency in Embedded
Electronic Systems (REES 2014)
status: public
title: On the Correlation of HW Faults and SW Errors
type: conference
user_id: '15931'
year: '2015'
...