--- _id: '52686' author: - first_name: Qazi Arbab full_name: Ahmed, Qazi Arbab id: '72764' last_name: Ahmed orcid: 0000-0002-1837-2254 - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Ahmed QA, Wiersema T, Platzner M. Post-configuration Activation of Hardware Trojans in FPGAs. Journal of Hardware and Systems Security. Published online 2024. doi:10.1007/s41635-024-00147-5 apa: Ahmed, Q. A., Wiersema, T., & Platzner, M. (2024). Post-configuration Activation of Hardware Trojans in FPGAs. Journal of Hardware and Systems Security. https://doi.org/10.1007/s41635-024-00147-5 bibtex: '@article{Ahmed_Wiersema_Platzner_2024, title={Post-configuration Activation of Hardware Trojans in FPGAs}, DOI={10.1007/s41635-024-00147-5}, journal={Journal of Hardware and Systems Security}, publisher={Springer Science and Business Media LLC}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2024} }' chicago: Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Post-Configuration Activation of Hardware Trojans in FPGAs.” Journal of Hardware and Systems Security, 2024. https://doi.org/10.1007/s41635-024-00147-5. ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Post-configuration Activation of Hardware Trojans in FPGAs,” Journal of Hardware and Systems Security, 2024, doi: 10.1007/s41635-024-00147-5.' mla: Ahmed, Qazi Arbab, et al. “Post-Configuration Activation of Hardware Trojans in FPGAs.” Journal of Hardware and Systems Security, Springer Science and Business Media LLC, 2024, doi:10.1007/s41635-024-00147-5. short: Q.A. Ahmed, T. Wiersema, M. Platzner, Journal of Hardware and Systems Security (2024). date_created: 2024-03-20T12:24:50Z date_updated: 2024-03-20T12:31:36Z department: - _id: '78' doi: 10.1007/s41635-024-00147-5 keyword: - General Engineering - Energy Engineering and Power Technology language: - iso: eng publication: Journal of Hardware and Systems Security publication_identifier: issn: - 2509-3428 - 2509-3436 publication_status: published publisher: Springer Science and Business Media LLC status: public title: Post-configuration Activation of Hardware Trojans in FPGAs type: journal_article user_id: '72764' year: '2024' ... --- _id: '29945' author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Lucas David full_name: Reuter, Lucas David last_name: Reuter - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Wiersema T, Reuter LD, Platzner M. Search Space Characterization for Approximate Logic Synthesis . In: 2022 59th ACM/IEEE Design Automation Conference (DAC).' apa: Witschen, L. M., Wiersema, T., Reuter, L. D., & Platzner, M. (n.d.). Search Space Characterization for Approximate Logic Synthesis . 2022 59th ACM/IEEE Design Automation Conference (DAC). 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA. bibtex: '@inproceedings{Witschen_Wiersema_Reuter_Platzner, title={Search Space Characterization for Approximate Logic Synthesis }, booktitle={2022 59th ACM/IEEE Design Automation Conference (DAC)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Reuter, Lucas David and Platzner, Marco} }' chicago: Witschen, Linus Matthias, Tobias Wiersema, Lucas David Reuter, and Marco Platzner. “Search Space Characterization for Approximate Logic Synthesis .” In 2022 59th ACM/IEEE Design Automation Conference (DAC), n.d. ieee: L. M. Witschen, T. Wiersema, L. D. Reuter, and M. Platzner, “Search Space Characterization for Approximate Logic Synthesis ,” presented at the 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA. mla: Witschen, Linus Matthias, et al. “Search Space Characterization for Approximate Logic Synthesis .” 2022 59th ACM/IEEE Design Automation Conference (DAC). short: 'L.M. Witschen, T. Wiersema, L.D. Reuter, M. Platzner, in: 2022 59th ACM/IEEE Design Automation Conference (DAC), n.d.' conference: end_date: 2022-07-14 location: San Francisco, USA name: 2022 59th ACM/IEEE Design Automation Conference (DAC) start_date: 2022-07-10 date_created: 2022-02-22T07:51:38Z date_updated: 2022-02-22T07:51:42Z department: - _id: '78' language: - iso: eng project: - _id: '1' name: 'SFB 901: SFB 901' - _id: '3' name: 'SFB 901 - B: SFB 901 - Project Area B' - _id: '12' name: 'SFB 901 - B4: SFB 901 - Subproject B4' publication: 2022 59th ACM/IEEE Design Automation Conference (DAC) publication_status: accepted status: public title: 'Search Space Characterization for Approximate Logic Synthesis ' type: conference user_id: '49051' year: '2022' ... --- _id: '29865' author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Matthias full_name: Artmann, Matthias last_name: Artmann - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Wiersema T, Artmann M, Platzner M. MUSCAT: MUS-based Circuit Approximation Technique. In: Design, Automation and Test in Europe (DATE).' apa: 'Witschen, L. M., Wiersema, T., Artmann, M., & Platzner, M. (n.d.). MUSCAT: MUS-based Circuit Approximation Technique. Design, Automation and Test in Europe (DATE). Design, Automation and Test in Europe (DATE), Online.' bibtex: '@inproceedings{Witschen_Wiersema_Artmann_Platzner, title={MUSCAT: MUS-based Circuit Approximation Technique}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Artmann, Matthias and Platzner, Marco} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Matthias Artmann, and Marco Platzner. “MUSCAT: MUS-Based Circuit Approximation Technique.” In Design, Automation and Test in Europe (DATE), n.d.' ieee: 'L. M. Witschen, T. Wiersema, M. Artmann, and M. Platzner, “MUSCAT: MUS-based Circuit Approximation Technique,” presented at the Design, Automation and Test in Europe (DATE), Online.' mla: 'Witschen, Linus Matthias, et al. “MUSCAT: MUS-Based Circuit Approximation Technique.” Design, Automation and Test in Europe (DATE).' short: 'L.M. Witschen, T. Wiersema, M. Artmann, M. Platzner, in: Design, Automation and Test in Europe (DATE), n.d.' conference: location: Online name: Design, Automation and Test in Europe (DATE) date_created: 2022-02-16T16:22:23Z date_updated: 2022-02-22T07:52:01Z department: - _id: '78' language: - iso: eng project: - _id: '1' name: 'SFB 901: SFB 901' - _id: '3' name: 'SFB 901 - B: SFB 901 - Project Area B' - _id: '12' name: 'SFB 901 - B4: SFB 901 - Subproject B4' - _id: '52' name: 'PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing' publication: Design, Automation and Test in Europe (DATE) publication_status: accepted status: public title: 'MUSCAT: MUS-based Circuit Approximation Technique' type: conference user_id: '49051' year: '2022' ... --- _id: '26746' abstract: - lang: eng text: "Previous research in proof-carrying hardware has established the feasibility and utility of the approach, and provided a concrete solution for employing it for the certification of functional equivalence checking against a specification, but fell short in connecting it to state-of-the-art formal verification insights, methods and tools. Due to the immense complexity of modern circuits, and verification challenges such as the state explosion problem for sequential circuits, this restriction of readily-available verification solutions severely limited the applicability of the approach in wider contexts.\r\n\r\nThis thesis closes the gap between the PCH approach and current advances in formal hardware verification, provides methods and tools to express and certify a wide range of circuit properties, both functional and non-functional, and presents for the first time prototypes in which circuits that are implemented on actual reconfigurable hardware are verified with PCH methods. Using these results, designers can now apply PCH to establish trust in more complex circuits, by using more diverse properties which they can express using modern, efficient property specification techniques." - lang: ger text: "Die bisherige Forschung zu Proof-Carrying Hardware (PCH) hat dessen Machbarkeit und Nützlichkeit gezeigt und einen Ansatz zur Zertifizierung der funktionalen Äquivalenz zu einer Spezifikation geliefert, jedoch ohne PCH mit aktuellen Erkenntnissen, Methoden oder Werkzeugen formaler Hardwareverifikation zu verknüpfen. Aufgrund der Komplexität moderner Schaltungen und Verifikationsherausforderungen wie der Zustandsexplosion bei sequentiellen Schaltungen, limitiert diese Einschränkung sofort verfügbarer Verifikationslösungen die Anwendbarkeit des Ansatzes in einem größeren Kontext signifikant.\r\n\r\nDiese Dissertation schließt die Lücke zwischen PCH und modernen Entwicklungen in der Schaltungsverifikation und stellt Methoden und Werkzeuge zur Verfügung, welche die Zertifizierung einer großen Bandbreite von Schaltungseigenschaften ermöglicht; sowohl funktionale, als auch nicht-funktionale. Überdies werden erstmals Prototypen vorgestellt in welchen Schaltungen mittels PCH verifiziert werden, die auf tatsächlicher rekonfigurierbarer Hardware realisiert sind. Dank dieser Ergebnisse können Entwickler PCH zur Herstellung von Vertrauen in weit komplexere Schaltungen verwenden, unter Zuhilfenahme einer größeren Vielfalt von Eigenschaften, welche durch moderne, effiziente Spezifikationstechniken ausgedrückt werden können." author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema citation: ama: Wiersema T. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University; 2021. apa: Wiersema, T. (2021). Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University. bibtex: '@book{Wiersema_2021, place={Paderborn}, title={Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware}, publisher={Paderborn University}, author={Wiersema, Tobias}, year={2021} }' chicago: 'Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.' ieee: 'T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn: Paderborn University, 2021.' mla: Wiersema, Tobias. Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware. Paderborn University, 2021. short: T. Wiersema, Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware, Paderborn University, Paderborn, 2021. date_created: 2021-10-25T06:35:41Z date_updated: 2022-01-06T06:57:26Z ddc: - '006' department: - _id: '78' keyword: - Proof-Carrying Hardware - Formal Verification - Sequential Circuits - Non-Functional Properties - Functional Properties language: - iso: eng main_file_link: - open_access: '1' url: https://nbn-resolving.de/urn:nbn:de:hbz:466:2-39800 oa: '1' page: '293' place: Paderborn project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 publication_status: published publisher: Paderborn University status: public supervisor: - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner title: Guaranteeing Properties of Reconfigurable Hardware Circuits with Proof-Carrying Hardware type: dissertation user_id: '3118' year: '2021' ... --- _id: '21953' author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Masood full_name: Raeisi Nafchi, Masood last_name: Raeisi Nafchi - first_name: Arne full_name: Bockhorn, Arne last_name: Bockhorn - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Wiersema T, Raeisi Nafchi M, Bockhorn A, Platzner M. Timing Optimization for Virtual FPGA Configurations. In: Hannig F, Derrien S, Diniz P, Chillet D, eds. Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21). Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science. doi:10.1007/978-3-030-79025-7_4' apa: Witschen, L. M., Wiersema, T., Raeisi Nafchi, M., Bockhorn, A., & Platzner, M. (n.d.). Timing Optimization for Virtual FPGA Configurations. In F. Hannig, S. Derrien, P. Diniz, & D. Chillet (Eds.), Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21). Springer Lecture Notes in Computer Science. https://doi.org/10.1007/978-3-030-79025-7_4 bibtex: '@inproceedings{Witschen_Wiersema_Raeisi Nafchi_Bockhorn_Platzner, series={Reconfigurable Computing: Architectures, Tools, and Applications}, title={Timing Optimization for Virtual FPGA Configurations}, DOI={10.1007/978-3-030-79025-7_4}, booktitle={Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21)}, publisher={Springer Lecture Notes in Computer Science}, author={Witschen, Linus Matthias and Wiersema, Tobias and Raeisi Nafchi, Masood and Bockhorn, Arne and Platzner, Marco}, editor={Hannig, Frank and Derrien, Steven and Diniz, Pedro and Chillet, Daniel}, collection={Reconfigurable Computing: Architectures, Tools, and Applications} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Masood Raeisi Nafchi, Arne Bockhorn, and Marco Platzner. “Timing Optimization for Virtual FPGA Configurations.” In Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), edited by Frank Hannig, Steven Derrien, Pedro Diniz, and Daniel Chillet. Reconfigurable Computing: Architectures, Tools, and Applications. Springer Lecture Notes in Computer Science, n.d. https://doi.org/10.1007/978-3-030-79025-7_4.' ieee: 'L. M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, and M. Platzner, “Timing Optimization for Virtual FPGA Configurations,” in Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Virtual conference, doi: 10.1007/978-3-030-79025-7_4.' mla: Witschen, Linus Matthias, et al. “Timing Optimization for Virtual FPGA Configurations.” Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), edited by Frank Hannig et al., Springer Lecture Notes in Computer Science, doi:10.1007/978-3-030-79025-7_4. short: 'L.M. Witschen, T. Wiersema, M. Raeisi Nafchi, A. Bockhorn, M. Platzner, in: F. Hannig, S. Derrien, P. Diniz, D. Chillet (Eds.), Proceedings of International Symposium on Applied Reconfigurable Computing (ARC’21), Springer Lecture Notes in Computer Science, n.d.' conference: end_date: 2021-07-01 location: Virtual conference name: International Symposium on Applied Reconfigurable Computing start_date: 2021-06-29 date_created: 2021-05-04T14:18:46Z date_updated: 2022-02-14T11:03:09Z department: - _id: '78' doi: 10.1007/978-3-030-79025-7_4 editor: - first_name: Frank full_name: Hannig, Frank last_name: Hannig - first_name: Steven full_name: Derrien, Steven last_name: Derrien - first_name: Pedro full_name: Diniz, Pedro last_name: Diniz - first_name: Daniel full_name: Chillet, Daniel last_name: Chillet language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Proceedings of International Symposium on Applied Reconfigurable Computing (ARC'21) publication_status: accepted publisher: Springer Lecture Notes in Computer Science series_title: 'Reconfigurable Computing: Architectures, Tools, and Applications' status: public title: Timing Optimization for Virtual FPGA Configurations type: conference user_id: '3118' year: '2021' ... --- _id: '27841' abstract: - lang: eng text: Verification of software and processor hardware usually proceeds separately, software analysis relying on the correctness of processors executing machine instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption. In this paper we present a novel formal approach for hardware/software co-verification targeting processors with custom instruction set extensions. We detail two different approaches for checking whether the hardware fulfills the requirements expected by the software analysis. The approaches are designed to explore a trade-off between generality of the verification and computational effort. Then, we describe the integration of software and hardware analyses for both techniques and describe a fully automated tool chain implementing the approaches. Finally, we demonstrate and compare the two approaches on example source code with custom instructions, using state-of-the-art software analysis and hardware verification techniques. author: - first_name: Marie-Christine full_name: Jakobs, Marie-Christine last_name: Jakobs - first_name: Felix full_name: Pauck, Felix id: '22398' last_name: Pauck - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema citation: ama: Jakobs M-C, Pauck F, Platzner M, Wehrheim H, Wiersema T. Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. Published online 2021. doi:10.1109/ACCESS.2021.3131213 apa: Jakobs, M.-C., Pauck, F., Platzner, M., Wehrheim, H., & Wiersema, T. (2021). Software/Hardware Co-Verification for Custom Instruction Set Processors. IEEE Access. https://doi.org/10.1109/ACCESS.2021.3131213 bibtex: '@article{Jakobs_Pauck_Platzner_Wehrheim_Wiersema_2021, title={Software/Hardware Co-Verification for Custom Instruction Set Processors}, DOI={10.1109/ACCESS.2021.3131213}, journal={IEEE Access}, publisher={IEEE}, author={Jakobs, Marie-Christine and Pauck, Felix and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2021} }' chicago: Jakobs, Marie-Christine, Felix Pauck, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” IEEE Access, 2021. https://doi.org/10.1109/ACCESS.2021.3131213. ieee: 'M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, and T. Wiersema, “Software/Hardware Co-Verification for Custom Instruction Set Processors,” IEEE Access, 2021, doi: 10.1109/ACCESS.2021.3131213.' mla: Jakobs, Marie-Christine, et al. “Software/Hardware Co-Verification for Custom Instruction Set Processors.” IEEE Access, IEEE, 2021, doi:10.1109/ACCESS.2021.3131213. short: M.-C. Jakobs, F. Pauck, M. Platzner, H. Wehrheim, T. Wiersema, IEEE Access (2021). date_created: 2021-11-25T14:12:22Z date_updated: 2023-01-18T08:34:50Z department: - _id: '78' doi: 10.1109/ACCESS.2021.3131213 funded_apc: '1' keyword: - Software Analysis - Abstract Interpretation - Custom Instruction - Hardware Verification language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 publication: IEEE Access publication_status: published publisher: IEEE quality_controlled: '1' status: public title: Software/Hardware Co-Verification for Custom Instruction Set Processors type: journal_article user_id: '22398' year: '2021' ... --- _id: '20681' abstract: - lang: eng text: The battle of developing hardware Trojans and corresponding countermeasures has taken adversaries towards ingenious ways of compromising hardware designs by circumventing even advanced testing and verification methods. Besides conventional methods of inserting Trojans into a design by a malicious entity, the design flow for field-programmable gate arrays (FPGAs) can also be surreptitiously compromised to assist the attacker to perform a successful malfunctioning or information leakage attack. The advanced stealthy malicious look-up-table (LUT) attack activates a Trojan only when generating the FPGA bitstream and can thus not be detected by register transfer and gate level testing and verification. However, also this attack was recently revealed by a bitstream-level proof-carrying hardware (PCH) approach. In this paper, we present a novel attack that leverages malicious routing of the inserted Trojan circuit to acquire a dormant state even in the generated and transmitted bitstream. The Trojan's payload is connected to primary inputs/outputs of the FPGA via a programmable interconnect point (PIP). The Trojan is detached from inputs/outputs during place-and-route and re-connected only when the FPGA is being programmed, thus activating the Trojan circuit without any need for a trigger logic. Since the Trojan is injected in a post-synthesis step and remains unconnected in the bitstream, the presented attack can currently neither be prevented by conventional testing and verification methods nor by recent bitstream-level verification techniques. author: - first_name: Qazi Arbab full_name: Ahmed, Qazi Arbab id: '72764' last_name: Ahmed orcid: 0000-0002-1837-2254 - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ahmed QA, Wiersema T, Platzner M. Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. In: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). 2021 Design, Automation and Test in Europe Conference (DATE); 2021. doi:10.23919/DATE51398.2021.9474026' apa: 'Ahmed, Q. A., Wiersema, T., & Platzner, M. (2021). Malicious Routing: Circumventing Bitstream-level Verification for FPGAs. 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France. https://doi.org/10.23919/DATE51398.2021.9474026' bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2021, place={Alpexpo | Grenoble, France}, title={Malicious Routing: Circumventing Bitstream-level Verification for FPGAs}, DOI={10.23919/DATE51398.2021.9474026}, booktitle={2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)}, publisher={2021 Design, Automation and Test in Europe Conference (DATE)}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, year={2021} }' chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” In 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). Alpexpo | Grenoble, France: 2021 Design, Automation and Test in Europe Conference (DATE), 2021. https://doi.org/10.23919/DATE51398.2021.9474026.' ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Malicious Routing: Circumventing Bitstream-level Verification for FPGAs,” presented at the Design, Automation and Test in Europe Conference (DATE’21), Alpexpo | Grenoble, France, 2021, doi: 10.23919/DATE51398.2021.9474026.' mla: 'Ahmed, Qazi Arbab, et al. “Malicious Routing: Circumventing Bitstream-Level Verification for FPGAs.” 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), 2021, doi:10.23919/DATE51398.2021.9474026.' short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2021 Design, Automation and Test in Europe Conference (DATE), Alpexpo | Grenoble, France, 2021.' conference: end_date: 2021-02-05 location: Alpexpo | Grenoble, France name: Design, Automation and Test in Europe Conference (DATE'21) start_date: 2021-02-01 date_created: 2020-12-07T14:03:00Z date_updated: 2023-05-11T09:16:34Z ddc: - '006' department: - _id: '78' doi: 10.23919/DATE51398.2021.9474026 file: - access_level: closed content_type: application/pdf creator: qazi date_created: 2023-05-11T09:16:15Z date_updated: 2023-05-11T09:16:15Z file_id: '44752' file_name: 1812.pdf file_size: 394011 relation: main_file success: 1 file_date_updated: 2023-05-11T09:16:15Z has_accepted_license: '1' language: - iso: eng main_file_link: - open_access: '1' oa: '1' place: Alpexpo | Grenoble, France project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '3' name: SFB 901 - Project Area B - _id: '1' name: SFB 901 publication: 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE) publication_identifier: eisbn: - 978-3-9819263-5-4 publication_status: published publisher: 2021 Design, Automation and Test in Europe Conference (DATE) status: public title: 'Malicious Routing: Circumventing Bitstream-level Verification for FPGAs' type: conference user_id: '72764' year: '2021' ... --- _id: '17358' abstract: - lang: eng text: 'Approximate circuits trade-off computational accuracy against improvements in hardware area, delay, or energy consumption. IP core vendors who wish to create such circuits need to convince consumers of the resulting approximation quality. As a solution we propose proof-carrying approximate circuits: The vendor creates an approximate IP core together with a certificate that proves the approximation quality. The proof certificate is bundled with the approximate IP core and sent off to the consumer. The consumer can formally verify the approximation quality of the IP core at a fraction of the typical computational cost for formal verification. In this paper, we first make the case for proof-carrying approximate circuits and then demonstrate the feasibility of the approach by a set of synthesis experiments using an exemplary approximation framework.' article_type: original author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Witschen LM, Wiersema T, Platzner M. Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems. 2020;28(9):2084-2088. doi:10.1109/TVLSI.2020.3008061 apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2020). Proof-carrying Approximate Circuits. IEEE Transactions On Very Large Scale Integration Systems, 28(9), 2084–2088. https://doi.org/10.1109/TVLSI.2020.3008061 bibtex: '@article{Witschen_Wiersema_Platzner_2020, title={Proof-carrying Approximate Circuits}, volume={28}, DOI={10.1109/TVLSI.2020.3008061}, number={9}, journal={IEEE Transactions On Very Large Scale Integration Systems}, publisher={IEEE}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2020}, pages={2084–2088} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems 28, no. 9 (2020): 2084–88. https://doi.org/10.1109/TVLSI.2020.3008061.' ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Proof-carrying Approximate Circuits,” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, pp. 2084–2088, 2020. mla: Witschen, Linus Matthias, et al. “Proof-Carrying Approximate Circuits.” IEEE Transactions On Very Large Scale Integration Systems, vol. 28, no. 9, IEEE, 2020, pp. 2084–88, doi:10.1109/TVLSI.2020.3008061. short: L.M. Witschen, T. Wiersema, M. Platzner, IEEE Transactions On Very Large Scale Integration Systems 28 (2020) 2084–2088. date_created: 2020-07-06T11:21:30Z date_updated: 2022-01-06T06:53:09Z department: - _id: '78' doi: 10.1109/TVLSI.2020.3008061 funded_apc: '1' intvolume: ' 28' issue: '9' keyword: - Approximate circuit synthesis - approximate computing - error metrics - formal verification - proof-carrying hardware language: - iso: eng page: 2084 - 2088 project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '3' name: SFB 901 - Project Area B - _id: '1' name: SFB 901 publication: IEEE Transactions On Very Large Scale Integration Systems publication_identifier: eissn: - 1557-9999 issn: - 1063-8210 publication_status: published publisher: IEEE quality_controlled: '1' status: public title: Proof-carrying Approximate Circuits type: journal_article user_id: '49051' volume: 28 year: '2020' ... --- _id: '20748' abstract: - lang: eng text: "On the circuit level, the design paradigm Approximate Computing seeks to trade off computational accuracy against a target metric, e.g., energy consumption. This trade-off is possible for many applications due to their inherent resiliency against inaccuracies.\r\nIn the past, several automated approximation frameworks have been presented, which either utilize designated approximation techniques or libraries to replace approximable circuit parts with inaccurate versions. The frameworks invoke a search algorithm to iteratively explore the search space of performance degraded circuits, and validate their quality individually. \r\nIn this paper, we propose to reverse this procedure. Rather than exploring the search space, we delineate the approximate parts of the search space which are guaranteed to lead to valid approximate circuits. Our methodology is supported by formal verification and independent of approximation techniques. Eventually, the user is provided with quality bounds of the individual approximable circuit parts. Consequently, our approach guarantees that any approximate circuit which implements these parts within the determined quality constraints satisfies the global quality constraints, superseding a subsequent quality verification.\r\nIn our experimental results, we present the runtimes of our approach." author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Witschen LM, Wiersema T, Platzner M. Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020). apa: Witschen, L. M., Wiersema, T., & Platzner, M. (n.d.). Search Space Characterization for AxC Synthesis. Fifth Workshop on Approximate Computing (AxC 2020). bibtex: '@article{Witschen_Wiersema_Platzner, title={Search Space Characterization for AxC Synthesis}, journal={Fifth Workshop on Approximate Computing (AxC 2020)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco} }' chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020), n.d. ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Search Space Characterization for AxC Synthesis,” Fifth Workshop on Approximate Computing (AxC 2020). . mla: Witschen, Linus Matthias, et al. “Search Space Characterization for AxC Synthesis.” Fifth Workshop on Approximate Computing (AxC 2020). short: L.M. Witschen, T. Wiersema, M. Platzner, Fifth Workshop on Approximate Computing (AxC 2020) (n.d.). date_created: 2020-12-15T15:13:49Z date_updated: 2022-01-06T06:54:35Z ddc: - '000' department: - _id: '78' file: - access_level: closed content_type: application/pdf creator: witschen date_created: 2020-12-15T15:11:06Z date_updated: 2020-12-15T15:11:06Z file_id: '20749' file_name: witschen20_axc.pdf file_size: 250870 relation: main_file success: 1 file_date_updated: 2020-12-15T15:11:06Z has_accepted_license: '1' language: - iso: eng page: '2' project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '3' name: SFB 901 - Project Area B - _id: '1' name: SFB 901 publication: Fifth Workshop on Approximate Computing (AxC 2020) publication_status: accepted status: public title: Search Space Characterization for AxC Synthesis type: preprint user_id: '3118' year: '2020' ... --- _id: '3585' abstract: - lang: eng text: Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Muhammad full_name: Awais, Muhammad id: '64665' last_name: Awais orcid: https://orcid.org/0000-0003-4148-2969 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003' apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003' bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, volume={99}, DOI={10.1016/j.microrel.2019.04.003}, journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019): 277–90. https://doi.org/10.1016/j.microrel.2019.04.003.' ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Microelectronics Reliability, vol. 99, pp. 277–290, 2019.' mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Microelectronics Reliability, vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.' short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Microelectronics Reliability 99 (2019) 277–290. date_created: 2018-07-20T14:08:49Z date_updated: 2022-01-06T06:59:25Z department: - _id: '78' doi: 10.1016/j.microrel.2019.04.003 intvolume: ' 99' keyword: - Approximate Computing - Framework - Pareto Front - Accuracy language: - iso: eng page: 277-290 project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Microelectronics Reliability publication_identifier: issn: - 0026-2714 publication_status: published publisher: Elsevier status: public title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation' type: journal_article user_id: '49051' volume: 99 year: '2019' ... --- _id: '9913' abstract: - lang: eng text: Reconfigurable hardware has received considerable attention as a platform that enables dynamic hardware updates and thus is able to adapt new configurations at runtime. However, due to their dynamic nature, e.g., field-programmable gate arrays (FPGA) are subject to a constant possibility of attacks, since each new configuration might be compromised. Trojans for reconfigurable hardware that evade state-of-the-art detection techniques and even formal verification, are thus a large threat to these devices. One such stealthy hardware Trojan, that is inserted and activated in two stages by compromised electronic design automation (EDA) tools, has recently been presented and shown to evade all forms of classical pre-configuration detection techniques. This paper presents a successful pre-configuration countermeasure against this ``Malicious Look-up-table (LUT)''-hardware Trojan, by employing bitstream-level Proof-Carrying Hardware (PCH). We show that the method is able to alert innocent module creators to infected EDA tools, and to prohibit malicious ones to sell infected modules to unsuspecting customers. author: - first_name: Qazi Arbab full_name: Ahmed, Qazi Arbab id: '72764' last_name: Ahmed orcid: 0000-0002-1837-2254 - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Ahmed QA, Wiersema T, Platzner M. Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. In: Hochberger C, Nelson B, Koch A, Woods R, Diniz P, eds. Applied Reconfigurable Computing. Vol 11444. Lecture Notes in Computer Science. Springer International Publishing; 2019:127-136. doi:10.1007/978-3-030-17227-5_10' apa: Ahmed, Q. A., Wiersema, T., & Platzner, M. (2019). Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan. In C. Hochberger, B. Nelson, A. Koch, R. Woods, & P. Diniz (Eds.), Applied Reconfigurable Computing (Vol. 11444, pp. 127–136). Springer International Publishing. https://doi.org/10.1007/978-3-030-17227-5_10 bibtex: '@inproceedings{Ahmed_Wiersema_Platzner_2019, place={Cham}, series={Lecture Notes in Computer Science}, title={Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan}, volume={11444}, DOI={10.1007/978-3-030-17227-5_10}, booktitle={Applied Reconfigurable Computing}, publisher={Springer International Publishing}, author={Ahmed, Qazi Arbab and Wiersema, Tobias and Platzner, Marco}, editor={Hochberger, Christian and Nelson, Brent and Koch, Andreas and Woods, Roger and Diniz, Pedro}, year={2019}, pages={127–136}, collection={Lecture Notes in Computer Science} }' chicago: 'Ahmed, Qazi Arbab, Tobias Wiersema, and Marco Platzner. “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” In Applied Reconfigurable Computing, edited by Christian Hochberger, Brent Nelson, Andreas Koch, Roger Woods, and Pedro Diniz, 11444:127–36. Lecture Notes in Computer Science. Cham: Springer International Publishing, 2019. https://doi.org/10.1007/978-3-030-17227-5_10.' ieee: 'Q. A. Ahmed, T. Wiersema, and M. Platzner, “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan,” in Applied Reconfigurable Computing, Darmstadt, Germany, 2019, vol. 11444, pp. 127–136, doi: 10.1007/978-3-030-17227-5_10.' mla: Ahmed, Qazi Arbab, et al. “Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan.” Applied Reconfigurable Computing, edited by Christian Hochberger et al., vol. 11444, Springer International Publishing, 2019, pp. 127–36, doi:10.1007/978-3-030-17227-5_10. short: 'Q.A. Ahmed, T. Wiersema, M. Platzner, in: C. Hochberger, B. Nelson, A. Koch, R. Woods, P. Diniz (Eds.), Applied Reconfigurable Computing, Springer International Publishing, Cham, 2019, pp. 127–136.' conference: end_date: 2019-04-11 location: Darmstadt, Germany name: 15th International Symposium on Applied Reconfigurable Computing (ARC 2019) start_date: 2019-04-09 date_created: 2019-05-22T07:36:05Z date_updated: 2023-05-15T08:13:37Z ddc: - '000' department: - _id: '78' doi: 10.1007/978-3-030-17227-5_10 editor: - first_name: Christian full_name: Hochberger, Christian last_name: Hochberger - first_name: Brent full_name: Nelson, Brent last_name: Nelson - first_name: Andreas full_name: Koch, Andreas last_name: Koch - first_name: Roger full_name: Woods, Roger last_name: Woods - first_name: Pedro full_name: Diniz, Pedro last_name: Diniz file: - access_level: closed content_type: application/pdf creator: qazi date_created: 2023-05-11T09:12:33Z date_updated: 2023-05-11T09:12:33Z file_id: '44749' file_name: 978-3-030-17227-5_10.pdf file_size: 661354 relation: main_file success: 1 file_date_updated: 2023-05-11T09:12:33Z has_accepted_license: '1' intvolume: ' 11444' language: - iso: eng main_file_link: - open_access: '1' oa: '1' page: 127-136 place: Cham project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B publication: Applied Reconfigurable Computing publication_identifier: isbn: - 978-3-030-17227-5 publication_status: published publisher: Springer International Publishing series_title: Lecture Notes in Computer Science status: public title: Proof-Carrying Hardware Versus the Stealthy Malicious LUT Hardware Trojan type: conference user_id: '72764' volume: 11444 year: '2019' ... --- _id: '3586' abstract: - lang: eng text: Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments. author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Hassan full_name: Ghasemzadeh Mohammadi, Hassan id: '61186' last_name: Ghasemzadeh Mohammadi - first_name: Muhammad full_name: Awais, Muhammad id: '64665' last_name: Awais orcid: https://orcid.org/0000-0003-4148-2969 - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).' apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., & Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).' bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner, title={CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}, journal={Third Workshop on Approximate Computing (AxC 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco} }' chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi, Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018), n.d.' ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner, “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,” Third Workshop on Approximate Computing (AxC 2018). .' mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation.” Third Workshop on Approximate Computing (AxC 2018).' short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner, Third Workshop on Approximate Computing (AxC 2018) (n.d.). date_created: 2018-07-20T14:10:46Z date_updated: 2022-01-06T06:59:26Z ddc: - '000' department: - _id: '78' file: - access_level: closed content_type: application/pdf creator: tobias82 date_created: 2018-07-20T14:13:31Z date_updated: 2018-07-20T14:13:31Z file_id: '3587' file_name: WitschenWMAP2018.pdf file_size: 285348 relation: main_file success: 1 file_date_updated: 2018-07-20T14:13:31Z has_accepted_license: '1' keyword: - Approximate Computing - Framework - Pareto Front - Accuracy language: - iso: eng page: '6' project: - _id: '12' name: SFB 901 - Subproject B4 - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: Third Workshop on Approximate Computing (AxC 2018) publication_status: accepted status: public title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation' type: preprint user_id: '49051' year: '2018' ... --- _id: '1165' author: - first_name: Linus Matthias full_name: Witschen, Linus Matthias id: '49051' last_name: Witschen - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Witschen LM, Wiersema T, Platzner M. Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). 2018. apa: Witschen, L. M., Wiersema, T., & Platzner, M. (2018). Making the Case for Proof-carrying Approximate Circuits. 4th Workshop On Approximate Computing (WAPCO 2018). bibtex: '@article{Witschen_Wiersema_Platzner_2018, title={Making the Case for Proof-carrying Approximate Circuits}, journal={4th Workshop On Approximate Computing (WAPCO 2018)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Platzner, Marco}, year={2018} }' chicago: Witschen, Linus Matthias, Tobias Wiersema, and Marco Platzner. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018. ieee: L. M. Witschen, T. Wiersema, and M. Platzner, “Making the Case for Proof-carrying Approximate Circuits,” 4th Workshop On Approximate Computing (WAPCO 2018). 2018. mla: Witschen, Linus Matthias, et al. “Making the Case for Proof-Carrying Approximate Circuits.” 4th Workshop On Approximate Computing (WAPCO 2018), 2018. short: L.M. Witschen, T. Wiersema, M. Platzner, 4th Workshop On Approximate Computing (WAPCO 2018) (2018). date_created: 2018-02-01T14:24:54Z date_updated: 2022-01-06T06:51:06Z ddc: - '000' department: - _id: '7' - _id: '34' - _id: '78' file: - access_level: closed content_type: application/pdf creator: tobias82 date_created: 2018-11-26T08:00:53Z date_updated: 2018-11-26T08:00:53Z file_id: '5821' file_name: WitschenWP2018[1].pdf file_size: 287224 relation: main_file success: 1 file_date_updated: 2018-11-26T08:00:53Z has_accepted_license: '1' language: - iso: eng project: - _id: '1' name: SFB 901 - _id: '3' name: SFB 901 - Project Area B - _id: '12' name: SFB 901 - Subproject B4 - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: 4th Workshop On Approximate Computing (WAPCO 2018) status: public title: Making the Case for Proof-carrying Approximate Circuits type: preprint user_id: '49051' year: '2018' ... --- _id: '68' abstract: - lang: eng text: Proof-carrying hardware (PCH) is a principle for achieving safety for dynamically reconfigurable hardware systems. The producer of a hardware module spends huge effort when creating a proof for a safety policy. The proof is then transferred as a certificate together with the configuration bitstream to the consumer of the hardware module, who can quickly verify the given proof. Previous work utilized SAT solvers and resolution traces to set up a PCH technology and corresponding tool flows. In this article, we present a novel technology for PCH based on inductive invariants. For sequential circuits, our approach is fundamentally stronger than the previous SAT-based one since we avoid the limitations of bounded unrolling. We contrast our technology to existing ones and show that it fits into previously proposed tool flows. We conduct experiments with four categories of benchmark circuits and report consumer and producer runtime and peak memory consumption, as well as the size of the certificates and the distribution of the workload between producer and consumer. Experiments clearly show that our new induction-based technology is superior for sequential circuits, whereas the previous SAT-based technology is the better choice for combinational circuits. author: - first_name: Tobias full_name: Isenberg, Tobias last_name: Isenberg - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema citation: ama: Isenberg T, Platzner M, Wehrheim H, Wiersema T. Proof-Carrying Hardware via Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems. 2017;(4):61:1--61:23. doi:10.1145/3054743 apa: Isenberg, T., Platzner, M., Wehrheim, H., & Wiersema, T. (2017). Proof-Carrying Hardware via Inductive Invariants. ACM Transactions on Design Automation of Electronic Systems, (4), 61:1--61:23. https://doi.org/10.1145/3054743 bibtex: '@article{Isenberg_Platzner_Wehrheim_Wiersema_2017, title={Proof-Carrying Hardware via Inductive Invariants}, DOI={10.1145/3054743}, number={4}, journal={ACM Transactions on Design Automation of Electronic Systems}, publisher={ACM}, author={Isenberg, Tobias and Platzner, Marco and Wehrheim, Heike and Wiersema, Tobias}, year={2017}, pages={61:1--61:23} }' chicago: 'Isenberg, Tobias, Marco Platzner, Heike Wehrheim, and Tobias Wiersema. “Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design Automation of Electronic Systems, no. 4 (2017): 61:1--61:23. https://doi.org/10.1145/3054743.' ieee: T. Isenberg, M. Platzner, H. Wehrheim, and T. Wiersema, “Proof-Carrying Hardware via Inductive Invariants,” ACM Transactions on Design Automation of Electronic Systems, no. 4, pp. 61:1--61:23, 2017. mla: Isenberg, Tobias, et al. “Proof-Carrying Hardware via Inductive Invariants.” ACM Transactions on Design Automation of Electronic Systems, no. 4, ACM, 2017, pp. 61:1--61:23, doi:10.1145/3054743. short: T. Isenberg, M. Platzner, H. Wehrheim, T. Wiersema, ACM Transactions on Design Automation of Electronic Systems (2017) 61:1--61:23. date_created: 2017-10-17T12:41:04Z date_updated: 2022-01-06T07:03:20Z ddc: - '000' department: - _id: '77' - _id: '78' doi: 10.1145/3054743 file: - access_level: closed content_type: application/pdf creator: ups date_created: 2018-11-02T16:08:17Z date_updated: 2018-11-02T16:08:17Z file_id: '5324' file_name: a61-isenberg.pdf file_size: 806356 relation: main_file success: 1 file_date_updated: 2018-11-02T16:08:17Z has_accepted_license: '1' issue: '4' language: - iso: eng page: 61:1--61:23 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B - _id: '52' name: Computing Resources Provided by the Paderborn Center for Parallel Computing publication: ACM Transactions on Design Automation of Electronic Systems publisher: ACM status: public title: Proof-Carrying Hardware via Inductive Invariants type: journal_article user_id: '3118' year: '2017' ... --- _id: '222' abstract: - lang: eng text: Virtual field programmable gate arrays (FPGA) are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA, along with an analysis of the area and delay overheads involved. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Arne full_name: Bockhorn, Arne last_name: Bockhorn - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: Wiersema T, Bockhorn A, Platzner M. An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers & Electrical Engineering. 2016:112--122. doi:10.1016/j.compeleceng.2016.04.005 apa: Wiersema, T., Bockhorn, A., & Platzner, M. (2016). An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip. Computers & Electrical Engineering, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005 bibtex: '@article{Wiersema_Bockhorn_Platzner_2016, title={An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip}, DOI={10.1016/j.compeleceng.2016.04.005}, journal={Computers & Electrical Engineering}, publisher={Elsevier}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2016}, pages={112--122} }' chicago: Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical Engineering, 2016, 112--122. https://doi.org/10.1016/j.compeleceng.2016.04.005. ieee: T. Wiersema, A. Bockhorn, and M. Platzner, “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip,” Computers & Electrical Engineering, pp. 112--122, 2016. mla: Wiersema, Tobias, et al. “An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip.” Computers & Electrical Engineering, Elsevier, 2016, pp. 112--122, doi:10.1016/j.compeleceng.2016.04.005. short: T. Wiersema, A. Bockhorn, M. Platzner, Computers & Electrical Engineering (2016) 112--122. date_created: 2017-10-17T12:41:35Z date_updated: 2022-01-06T06:55:29Z ddc: - '040' department: - _id: '78' doi: 10.1016/j.compeleceng.2016.04.005 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T10:36:08Z date_updated: 2018-03-21T10:36:08Z file_id: '1511' file_name: 222-1-s2.0-S0045790616300684-main.pdf file_size: 931048 relation: main_file success: 1 file_date_updated: 2018-03-21T10:36:08Z has_accepted_license: '1' language: - iso: eng page: 112--122 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Computers & Electrical Engineering publisher: Elsevier status: public title: An Architecture and Design Tool Flow for Embedding a Virtual FPGA into a Reconfigurable System-on-Chip type: journal_article user_id: '477' year: '2016' ... --- _id: '132' abstract: - lang: eng text: Runtime reconfiguration can be used to replace hardware modules in the field and even to continuously improve them during operation. Runtime reconfiguration poses new challenges for validation, since the required properties of newly arriving modules may be difficult to check fast enough to sustain the intended system dynamics. In this paper we present a method for just-in-time verification of the worst-case completion time of a reconfigurable hardware module. We assume so-called run-to-completion modules that exhibit start and done signals indicating the start and end of execution, respectively. We present a formal verification approach that exploits the concept of proof-carrying hardware. The approach tasks the creator of a hardware module with constructing a proof of the worst-case completion time, which can then easily be checked by the user of the module, just prior to reconfiguration. After explaining the verification approach and a corresponding tool flow, we present results from two case studies, a short term synthesis filter and a multihead weigher. The resultsclearly show that cost of verifying the completion time of the module is paid by the creator instead of the user of the module. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wiersema T, Platzner M. Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016). ; 2016:1--8. doi:10.1109/ReCoSoC.2016.7533910' apa: Wiersema, T., & Platzner, M. (2016). Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware. In Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) (pp. 1--8). https://doi.org/10.1109/ReCoSoC.2016.7533910 bibtex: '@inproceedings{Wiersema_Platzner_2016, title={Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware}, DOI={10.1109/ReCoSoC.2016.7533910}, booktitle={Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016)}, author={Wiersema, Tobias and Platzner, Marco}, year={2016}, pages={1--8} }' chicago: Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” In Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 1--8, 2016. https://doi.org/10.1109/ReCoSoC.2016.7533910. ieee: T. Wiersema and M. Platzner, “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware,” in Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8. mla: Wiersema, Tobias, and Marco Platzner. “Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules Using Proof-Carrying Hardware.” Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8, doi:10.1109/ReCoSoC.2016.7533910. short: 'T. Wiersema, M. Platzner, in: Proceedings of the 11th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC 2016), 2016, pp. 1--8.' date_created: 2017-10-17T12:41:17Z date_updated: 2022-01-06T06:51:30Z ddc: - '040' department: - _id: '78' doi: 10.1109/ReCoSoC.2016.7533910 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T13:02:30Z date_updated: 2018-03-21T13:02:30Z file_id: '1562' file_name: 132-07533910.pdf file_size: 911171 relation: main_file success: 1 file_date_updated: 2018-03-21T13:02:30Z has_accepted_license: '1' language: - iso: eng page: 1--8 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2016) status: public title: Verifying Worst-Case Completion Times for Reconfigurable Hardware Modules using Proof-Carrying Hardware type: conference user_id: '477' year: '2016' ... --- _id: '269' abstract: - lang: eng text: Proof-carrying hardware is an approach that has recently been proposed for the efficient verification of reconfigurable modules. We present an application of proof-carrying hardware to guarantee the correct functionality of dynamically reconfigured image processing modules. Our prototype comprises a reconfigurable-system-on-chip with an embedded virtual FPGA fabric. This setup allows us to leverage open source FPGA synthesis and backend tools to produce FPGA configuration bitstreams with an open format and, thus, to demonstrate and experimentally evaluate proof-carrying hardware at the bitstream level. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Sen full_name: Wu, Sen last_name: Wu - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wiersema T, Wu S, Platzner M. On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In: Proceedings of the International Symposium in Reconfigurable Computing (ARC). LNCS. ; 2015:365--372. doi:10.1007/978-3-319-16214-0_32' apa: Wiersema, T., Wu, S., & Platzner, M. (2015). On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach. In Proceedings of the International Symposium in Reconfigurable Computing (ARC) (pp. 365--372). https://doi.org/10.1007/978-3-319-16214-0_32 bibtex: '@inproceedings{Wiersema_Wu_Platzner_2015, series={LNCS}, title={On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach}, DOI={10.1007/978-3-319-16214-0_32}, booktitle={Proceedings of the International Symposium in Reconfigurable Computing (ARC)}, author={Wiersema, Tobias and Wu, Sen and Platzner, Marco}, year={2015}, pages={365--372}, collection={LNCS} }' chicago: Wiersema, Tobias, Sen Wu, and Marco Platzner. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” In Proceedings of the International Symposium in Reconfigurable Computing (ARC), 365--372. LNCS, 2015. https://doi.org/10.1007/978-3-319-16214-0_32. ieee: T. Wiersema, S. Wu, and M. Platzner, “On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach,” in Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372. mla: Wiersema, Tobias, et al. “On-The-Fly Verification of Reconfigurable Image Processing Modules Based on a Proof-Carrying Hardware Approach.” Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372, doi:10.1007/978-3-319-16214-0_32. short: 'T. Wiersema, S. Wu, M. Platzner, in: Proceedings of the International Symposium in Reconfigurable Computing (ARC), 2015, pp. 365--372.' date_created: 2017-10-17T12:41:44Z date_updated: 2022-01-06T06:57:30Z ddc: - '040' department: - _id: '78' doi: 10.1007/978-3-319-16214-0_32 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-21T09:32:42Z date_updated: 2018-03-21T09:32:42Z file_id: '1477' file_name: 269-paper_53.pdf file_size: 344309 relation: main_file success: 1 file_date_updated: 2018-03-21T09:32:42Z has_accepted_license: '1' language: - iso: eng page: 365--372 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the International Symposium in Reconfigurable Computing (ARC) series_title: LNCS status: public title: On-The-Fly Verification of Reconfigurable Image Processing Modules based on a Proof-Carrying Hardware Approach type: conference user_id: '477' year: '2015' ... --- _id: '399' abstract: - lang: eng text: Ensuring memory access security is a challenge for reconfigurable systems with multiple cores. Previous work introduced access monitors attached to the memory subsystem to ensure that the cores adhere to pre-defined protocols when accessing memory. In this paper, we combine access monitors with a formal runtime verification technique known as proof-carrying hardware to guarantee memory security. We extend previous work on proof-carrying hardware by covering sequential circuits and demonstrate our approach with a prototype leveraging ReconOS/Zynq with an embedded ZUMA virtual FPGA overlay. Experiments show the feasibility of the approach and the capabilities of the prototype, which constitutes the first realization of proof-carrying hardware on real FPGAs. The area overheads for the virtual FPGA are measured as 2x-10x, depending on the resource type. The delay overhead is substantial with almost 100x, but this is an extremely pessimistic estimate that will be lowered once accurate timing analysis for FPGA overlays become available. Finally, reconfiguration time for the virtual FPGA is about one order of magnitude lower than for the native Zynq fabric. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Stephanie full_name: Drzevitzky, Stephanie last_name: Drzevitzky - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wiersema T, Drzevitzky S, Platzner M. Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In: Proceedings of the International Conference on Field-Programmable Technology (FPT). ; 2014:167-174. doi:10.1109/FPT.2014.7082771' apa: 'Wiersema, T., Drzevitzky, S., & Platzner, M. (2014). Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring. In Proceedings of the International Conference on Field-Programmable Technology (FPT) (pp. 167–174). https://doi.org/10.1109/FPT.2014.7082771' bibtex: '@inproceedings{Wiersema_Drzevitzky_Platzner_2014, title={Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring}, DOI={10.1109/FPT.2014.7082771}, booktitle={Proceedings of the International Conference on Field-Programmable Technology (FPT)}, author={Wiersema, Tobias and Drzevitzky, Stephanie and Platzner, Marco}, year={2014}, pages={167–174} }' chicago: 'Wiersema, Tobias, Stephanie Drzevitzky, and Marco Platzner. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” In Proceedings of the International Conference on Field-Programmable Technology (FPT), 167–74, 2014. https://doi.org/10.1109/FPT.2014.7082771.' ieee: 'T. Wiersema, S. Drzevitzky, and M. Platzner, “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring,” in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.' mla: 'Wiersema, Tobias, et al. “Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring.” Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–74, doi:10.1109/FPT.2014.7082771.' short: 'T. Wiersema, S. Drzevitzky, M. Platzner, in: Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp. 167–174.' date_created: 2017-10-17T12:42:09Z date_updated: 2022-01-06T07:00:05Z ddc: - '040' department: - _id: '78' doi: 10.1109/FPT.2014.7082771 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-20T06:57:44Z date_updated: 2018-03-20T06:57:44Z file_id: '1380' file_name: 399-wiersema14_fpt_IEEE_approved.pdf file_size: 404328 relation: main_file success: 1 file_date_updated: 2018-03-20T06:57:44Z has_accepted_license: '1' language: - iso: eng page: 167-174 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the International Conference on Field-Programmable Technology (FPT) status: public title: 'Memory Security in Reconfigurable Computers: Combining Formal Verification with Monitoring' type: conference user_id: '477' year: '2014' ... --- _id: '408' abstract: - lang: eng text: Verification of hardware and software usually proceeds separately, software analysis relying on the correctness of processors executing instructions. This assumption is valid as long as the software runs on standard CPUs that have been extensively validated and are in wide use. However, for processors exploiting custom instruction set extensions to meet performance and energy constraints the validation might be less extensive, challenging the correctness assumption.In this paper we present an approach for integrating software analyses with hardware verification, specifically targeting custom instruction set extensions. We propose three different techniques for deriving the properties to be proven for the hardware implementation of a custom instruction in order to support software analyses. The techniques are designed to explore the trade-off between generality and efficiency and span from proving functional equivalence over checking the rules of a particular analysis domain to verifying actual pre and post conditions resulting from program analysis. We demonstrate and compare the three techniques on example programs with custom instructions, using stateof-the-art software and hardware verification techniques. author: - first_name: Marie-Christine full_name: Jakobs, Marie-Christine last_name: Jakobs - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Heike full_name: Wehrheim, Heike id: '573' last_name: Wehrheim citation: ama: 'Jakobs M-C, Platzner M, Wiersema T, Wehrheim H. Integrating Software and Hardware Verification. In: Albert E, Sekerinski E, eds. Proceedings of the 11th International Conference on Integrated Formal Methods (IFM). LNCS. ; 2014:307-322. doi:10.1007/978-3-319-10181-1_19' apa: Jakobs, M.-C., Platzner, M., Wiersema, T., & Wehrheim, H. (2014). Integrating Software and Hardware Verification. In E. Albert & E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) (pp. 307–322). https://doi.org/10.1007/978-3-319-10181-1_19 bibtex: '@inproceedings{Jakobs_Platzner_Wiersema_Wehrheim_2014, series={LNCS}, title={Integrating Software and Hardware Verification}, DOI={10.1007/978-3-319-10181-1_19}, booktitle={Proceedings of the 11th International Conference on Integrated Formal Methods (iFM)}, author={Jakobs, Marie-Christine and Platzner, Marco and Wiersema, Tobias and Wehrheim, Heike}, editor={Albert, Elvira and Sekerinski, EmilEditors}, year={2014}, pages={307–322}, collection={LNCS} }' chicago: Jakobs, Marie-Christine, Marco Platzner, Tobias Wiersema, and Heike Wehrheim. “Integrating Software and Hardware Verification.” In Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 307–22. LNCS, 2014. https://doi.org/10.1007/978-3-319-10181-1_19. ieee: M.-C. Jakobs, M. Platzner, T. Wiersema, and H. Wehrheim, “Integrating Software and Hardware Verification,” in Proceedings of the 11th International Conference on Integrated Formal Methods (iFM), 2014, pp. 307–322. mla: Jakobs, Marie-Christine, et al. “Integrating Software and Hardware Verification.” Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), edited by Elvira Albert and Emil Sekerinski, 2014, pp. 307–22, doi:10.1007/978-3-319-10181-1_19. short: 'M.-C. Jakobs, M. Platzner, T. Wiersema, H. Wehrheim, in: E. Albert, E. Sekerinski (Eds.), Proceedings of the 11th International Conference on Integrated Formal Methods (IFM), 2014, pp. 307–322.' date_created: 2017-10-17T12:42:11Z date_updated: 2022-01-06T07:00:14Z ddc: - '040' department: - _id: '77' - _id: '78' doi: 10.1007/978-3-319-10181-1_19 editor: - first_name: Elvira full_name: Albert, Elvira last_name: Albert - first_name: Emil full_name: Sekerinski, Emil last_name: Sekerinski file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:35:28Z date_updated: 2018-03-16T11:35:28Z file_id: '1364' file_name: 408-jakobs14_ifm.pdf file_size: 561325 relation: main_file success: 1 file_date_updated: 2018-03-16T11:35:28Z has_accepted_license: '1' language: - iso: eng page: 307-322 project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the 11th International Conference on Integrated Formal Methods (iFM) series_title: LNCS status: public title: Integrating Software and Hardware Verification type: conference user_id: '477' year: '2014' ... --- _id: '433' abstract: - lang: eng text: Virtual FPGAs are overlay architectures realized on top of physical FPGAs. They are proposed to enhance or abstract away from the physical FPGA for experimenting with novel architectures and design tool flows. In this paper, we present an embedding of a ZUMA-based virtual FPGA fabric into a complete configurable system-on-chip. Such an embedding is required to fully harness the potential of virtual FPGAs, in particular to give the virtual circuits access to main memory and operating system services, and to enable a concurrent operation of virtualized and non-virtualized circuitry. We discuss our extension to ZUMA and its embedding into the ReconOS operating system for hardware/software systems. Furthermore, we present an open source tool flow to synthesize configurations for the virtual FPGA. author: - first_name: Tobias full_name: Wiersema, Tobias id: '3118' last_name: Wiersema - first_name: Arne full_name: Bockhorn, Arne last_name: Bockhorn - first_name: Marco full_name: Platzner, Marco id: '398' last_name: Platzner citation: ama: 'Wiersema T, Bockhorn A, Platzner M. Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig). ; 2014:1-6. doi:10.1109/ReConFig.2014.7032514' apa: 'Wiersema, T., Bockhorn, A., & Platzner, M. (2014). Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA. In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) (pp. 1–6). https://doi.org/10.1109/ReConFig.2014.7032514' bibtex: '@inproceedings{Wiersema_Bockhorn_Platzner_2014, title={Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA}, DOI={10.1109/ReConFig.2014.7032514}, booktitle={Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig)}, author={Wiersema, Tobias and Bockhorn, Arne and Platzner, Marco}, year={2014}, pages={1–6} }' chicago: 'Wiersema, Tobias, Arne Bockhorn, and Marco Platzner. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” In Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 1–6, 2014. https://doi.org/10.1109/ReConFig.2014.7032514.' ieee: 'T. Wiersema, A. Bockhorn, and M. Platzner, “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA,” in Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.' mla: 'Wiersema, Tobias, et al. “Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS Meets ZUMA.” Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6, doi:10.1109/ReConFig.2014.7032514.' short: 'T. Wiersema, A. Bockhorn, M. Platzner, in: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2014, pp. 1–6.' date_created: 2017-10-17T12:42:16Z date_updated: 2022-01-06T07:00:56Z ddc: - '040' department: - _id: '78' doi: 10.1109/ReConFig.2014.7032514 file: - access_level: closed content_type: application/pdf creator: florida date_created: 2018-03-16T11:30:58Z date_updated: 2018-03-16T11:30:58Z file_id: '1355' file_name: 433-wiersema14_reconfig_IEEE_approved.pdf file_size: 369333 relation: main_file success: 1 file_date_updated: 2018-03-16T11:30:58Z has_accepted_license: '1' language: - iso: eng page: '1-6 ' project: - _id: '1' name: SFB 901 - _id: '12' name: SFB 901 - Subprojekt B4 - _id: '3' name: SFB 901 - Project Area B publication: Proceedings of the International Conference on ReConFigurable Computing and FPGAs (ReConFig) status: public title: 'Embedding FPGA Overlays into Configurable Systems-on-Chip: ReconOS meets ZUMA' type: conference user_id: '477' year: '2014' ...