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Platzner, “Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms.” ."},"language":[{"iso":"eng"}],"main_file_link":[{"url":"https://arxiv.org/pdf/2306.12761.pdf"}],"_id":"46229","date_updated":"2023-07-31T11:59:58Z","publication_status":"accepted","date_created":"2023-07-31T11:56:47Z","status":"public","department":[{"_id":"78"}],"author":[{"full_name":"Lienen, Christian","first_name":"Christian","id":"60323","last_name":"Lienen"},{"last_name":"Nowosad","first_name":"Alexander Philipp","full_name":"Nowosad, Alexander Philipp"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"title":"Mapping and Optimizing Communication in ROS 2-based Applications on Configurable System-on-Chip Platforms","user_id":"60323"},{"_id":"45913","date_updated":"2023-08-03T13:49:50Z","type":"conference","citation":{"short":"L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, M. Platzner, in: Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC), 2023.","ieee":"L. Clausing, Z. Guetattfi, P. Kaufmann, C. Lienen, and M. Platzner, “On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64,” 2023.","apa":"Clausing, L., Guetattfi, Z., Kaufmann, P., Lienen, C., & Platzner, M. (2023). On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64. Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC).","ama":"Clausing L, Guetattfi Z, Kaufmann P, Lienen C, Platzner M. On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64. In: Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC). ; 2023.","chicago":"Clausing, Lennart, Zakarya Guetattfi, Paul Kaufmann, Christian Lienen, and Marco Platzner. “On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks under ReconOS64.” In Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC), 2023.","mla":"Clausing, Lennart, et al. “On Guaranteeing Schedulability of Periodic Real-Time Hardware Tasks under ReconOS64.” Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC), 2023.","bibtex":"@inproceedings{Clausing_Guetattfi_Kaufmann_Lienen_Platzner_2023, title={On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64}, booktitle={Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)}, author={Clausing, Lennart and Guetattfi, Zakarya and Kaufmann, Paul and Lienen, Christian and Platzner, Marco}, year={2023} }"},"year":"2023","language":[{"iso":"eng"}],"title":"On Guaranteeing Schedulability of Periodic Real-time Hardware Tasks under ReconOS64","user_id":"477","publication":"Proceedings of the 19th International Symposium on Applied Reconfigurable Computing (ARC)","department":[{"_id":"78"}],"author":[{"last_name":"Clausing","id":"74287","first_name":"Lennart","full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034"},{"full_name":"Guetattfi, Zakarya","first_name":"Zakarya","last_name":"Guetattfi"},{"last_name":"Kaufmann","full_name":"Kaufmann, Paul","first_name":"Paul"},{"last_name":"Lienen","id":"60323","first_name":"Christian","full_name":"Lienen, Christian"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"project":[{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"_id":"82","name":"SFB 901 - T: SFB 901 - Project Area T"},{"grant_number":"160364472","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","_id":"1"}],"date_created":"2023-07-09T12:50:32Z","status":"public"},{"page":"247","citation":{"mla":"Haake, Claus-Jochen, et al. On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets. Heinz Nixdorf Institut, Universität Paderborn, 2023, doi:10.17619/UNIPB/1-1797.","bibtex":"@book{Haake_Meyer auf der Heide_Platzner_Wachsmuth_Wehrheim_2023, place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts}, title={On-The-Fly Computing -- Individualized IT-services in dynamic markets}, volume={412}, DOI={10.17619/UNIPB/1-1797}, publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts} }","apa":"Haake, C.-J., Meyer auf der Heide, F., Platzner, M., Wachsmuth, H., & Wehrheim, H. (2023). On-The-Fly Computing -- Individualized IT-services in dynamic markets (Vol. 412). Heinz Nixdorf Institut, Universität Paderborn. https://doi.org/10.17619/UNIPB/1-1797","ama":"Haake C-J, Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H. On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets. Vol 412. Heinz Nixdorf Institut, Universität Paderborn; 2023. doi:10.17619/UNIPB/1-1797","chicago":"Haake, Claus-Jochen, Friedhelm Meyer auf der Heide, Marco Platzner, Henning Wachsmuth, and Heike Wehrheim. On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets. Vol. 412. Verlagsschriftenreihe Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023. https://doi.org/10.17619/UNIPB/1-1797.","ieee":"C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and H. Wehrheim, On-The-Fly Computing -- Individualized IT-services in dynamic markets, vol. 412. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023.","short":"C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim, On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets, Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023."},"year":"2023","type":"book","intvolume":" 412","_id":"45863","file":[{"file_id":"45864","creator":"ups","file_size":15480050,"relation":"main_file","content_type":"application/pdf","date_updated":"2023-07-05T07:19:14Z","date_created":"2023-07-05T07:15:55Z","file_name":"SFB-Buch-Final.pdf","access_level":"open_access"}],"file_date_updated":"2023-07-05T07:19:14Z","publisher":"Heinz Nixdorf Institut, Universität Paderborn","author":[{"id":"20801","last_name":"Haake","full_name":"Haake, Claus-Jochen","first_name":"Claus-Jochen"},{"first_name":"Friedhelm","full_name":"Meyer auf der Heide, Friedhelm","last_name":"Meyer auf der Heide","id":"15523"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"},{"id":"3900","last_name":"Wachsmuth","full_name":"Wachsmuth, Henning","first_name":"Henning"},{"full_name":"Wehrheim, Heike","first_name":"Heike","id":"573","last_name":"Wehrheim"}],"date_created":"2023-07-05T07:16:51Z","has_accepted_license":"1","status":"public","volume":412,"alternative_title":["Collaborative Research Centre 901 (2011 – 2023)"],"abstract":[{"lang":"eng","text":"In the proposal for our CRC in 2011, we formulated a vision of markets for\r\nIT services that describes an approach to the provision of such services\r\nthat was novel at that time and, to a large extent, remains so today:\r\n„Our vision of on-the-fly computing is that of IT services individually and\r\nautomatically configured and brought to execution from flexibly combinable\r\nservices traded on markets. At the same time, we aim at organizing\r\nmarkets whose participants maintain a lively market of services through\r\nappropriate entrepreneurial actions.“\r\nOver the last 12 years, we have developed methods and techniques to\r\naddress problems critical to the convenient, efficient, and secure use of\r\non-the-fly computing. Among other things, we have made the description\r\nof services more convenient by allowing natural language input,\r\nincreased the quality of configured services through (natural language)\r\ninteraction and more efficient configuration processes and analysis\r\nprocedures, made the quality of (the products of) providers in the\r\nmarketplace transparent through reputation systems, and increased the\r\nresource efficiency of execution through reconfigurable heterogeneous\r\ncomputing nodes and an integrated treatment of service description and\r\nconfiguration. We have also developed network infrastructures that have\r\na high degree of adaptivity, scalability, efficiency, and reliability, and\r\nprovide cryptographic guarantees of anonymity and security for market\r\nparticipants and their products and services.\r\nTo demonstrate the pervasiveness of the OTF computing approach, we\r\nhave implemented a proof-of-concept for OTF computing that can run\r\ntypical scenarios of an OTF market. We illustrated the approach using\r\na cutting-edge application scenario – automated machine learning (AutoML).\r\nFinally, we have been pushing our work for the perpetuation of\r\nOn-The-Fly Computing beyond the SFB and sharing the expertise gained\r\nin the SFB in events with industry partners as well as transfer projects.\r\nThis work required a broad spectrum of expertise. Computer scientists\r\nand economists with research interests such as computer networks and\r\ndistributed algorithms, security and cryptography, software engineering\r\nand verification, configuration and machine learning, computer engineering\r\nand HPC, microeconomics and game theory, business informatics\r\nand management have successfully collaborated here."}],"user_id":"477","ddc":["000"],"series_title":"Verlagsschriftenreihe des Heinz Nixdorf Instituts","language":[{"iso":"eng"}],"date_updated":"2023-08-29T06:44:36Z","oa":"1","doi":"10.17619/UNIPB/1-1797","department":[{"_id":"7"}],"project":[{"_id":"1","name":"SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen in dynamischen Märkten ","grant_number":"160364472"},{"name":"SFB 901 - A: SFB 901 - Project Area A","_id":"2"},{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"},{"grant_number":"160364472","name":"SFB 901 - A1: SFB 901 - Möglichkeiten und Grenzen lokaler Strategien in dynamischen Netzen (Subproject A1)","_id":"5"},{"_id":"7","name":"SFB 901 - A3: SFB 901 - Der Markt für Services: Anreize, Algorithmen, Implementation (Subproject A3)","grant_number":"160364472"},{"_id":"8","name":"SFB 901 - A4: SFB 901 - Empirische Analysen in Märkten für OTF Dienstleistungen (Subproject A4)","grant_number":"160364472"},{"_id":"9","name":"SFB 901 - B1: SFB 901 - Parametrisierte Servicespezifikation (Subproject B1)","grant_number":"160364472"},{"grant_number":"160364472","name":"SFB 901 - B2: Konfiguration und Bewertung (B02)","_id":"10"},{"name":"SFB 901 - B3: SFB 901 - Subproject B3","_id":"11"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"},{"name":"SFB 901 - C1: SFB 901 - Subproject C1","_id":"13"},{"grant_number":"160364472","name":"SFB 901 - C2: SFB 901 - On-The-Fly Compute Centers I: Heterogene Ausführungsumgebungen (Subproject C2)","_id":"14"},{"_id":"16","grant_number":"160364472","name":"SFB 901 - C4: SFB 901 - On-The-Fly Compute Centers II: Ausführung komponierter Dienste in konfigurierbaren Rechenzentren (Subproject C4)"},{"name":"SFB 901 - C5: SFB 901 - Subproject C5","_id":"17"},{"_id":"83","name":"SFB 901 - T1: SFB 901 -Subproject T1"},{"_id":"84","name":"SFB 901 - T2: SFB 901 -Subproject T2"}],"publication_identifier":{"unknown":["978-3-947647-31-6"]},"place":"Paderborn","title":"On-The-Fly Computing -- Individualized IT-services in dynamic markets"},{"status":"public","date_created":"2022-02-22T07:51:38Z","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"name":"SFB 901 - B4: SFB 901 - Subproject B4","_id":"12"}],"publication_status":"accepted","author":[{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"first_name":"Lucas David","full_name":"Reuter, Lucas David","last_name":"Reuter"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"department":[{"_id":"78"}],"publication":"2022 59th ACM/IEEE Design Automation Conference (DAC)","user_id":"49051","title":"Search Space Characterization for Approximate Logic Synthesis ","language":[{"iso":"eng"}],"citation":{"ieee":"L. M. Witschen, T. Wiersema, L. D. Reuter, and M. Platzner, “Search Space Characterization for Approximate Logic Synthesis ,” presented at the 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.","short":"L.M. Witschen, T. Wiersema, L.D. Reuter, M. Platzner, in: 2022 59th ACM/IEEE Design Automation Conference (DAC), n.d.","bibtex":"@inproceedings{Witschen_Wiersema_Reuter_Platzner, title={Search Space Characterization for Approximate Logic Synthesis }, booktitle={2022 59th ACM/IEEE Design Automation Conference (DAC)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Reuter, Lucas David and Platzner, Marco} }","mla":"Witschen, Linus Matthias, et al. “Search Space Characterization for Approximate Logic Synthesis .” 2022 59th ACM/IEEE Design Automation Conference (DAC).","apa":"Witschen, L. M., Wiersema, T., Reuter, L. D., & Platzner, M. (n.d.). Search Space Characterization for Approximate Logic Synthesis . 2022 59th ACM/IEEE Design Automation Conference (DAC). 2022 59th ACM/IEEE Design Automation Conference (DAC), San Francisco, USA.","ama":"Witschen LM, Wiersema T, Reuter LD, Platzner M. Search Space Characterization for Approximate Logic Synthesis . In: 2022 59th ACM/IEEE Design Automation Conference (DAC).","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Lucas David Reuter, and Marco Platzner. “Search Space Characterization for Approximate Logic Synthesis .” In 2022 59th ACM/IEEE Design Automation Conference (DAC), n.d."},"year":"2022","type":"conference","_id":"29945","date_updated":"2022-02-22T07:51:42Z","conference":{"location":"San Francisco, USA","name":"2022 59th ACM/IEEE Design Automation Conference (DAC)","start_date":"2022-07-10","end_date":"2022-07-14"}},{"language":[{"iso":"eng"}],"citation":{"ieee":"L. M. Witschen, T. Wiersema, M. Artmann, and M. Platzner, “MUSCAT: MUS-based Circuit Approximation Technique,” presented at the Design, Automation and Test in Europe (DATE), Online.","short":"L.M. Witschen, T. Wiersema, M. Artmann, M. Platzner, in: Design, Automation and Test in Europe (DATE), n.d.","mla":"Witschen, Linus Matthias, et al. “MUSCAT: MUS-Based Circuit Approximation Technique.” Design, Automation and Test in Europe (DATE).","bibtex":"@inproceedings{Witschen_Wiersema_Artmann_Platzner, title={MUSCAT: MUS-based Circuit Approximation Technique}, booktitle={Design, Automation and Test in Europe (DATE)}, author={Witschen, Linus Matthias and Wiersema, Tobias and Artmann, Matthias and Platzner, Marco} }","apa":"Witschen, L. M., Wiersema, T., Artmann, M., & Platzner, M. (n.d.). MUSCAT: MUS-based Circuit Approximation Technique. Design, Automation and Test in Europe (DATE). Design, Automation and Test in Europe (DATE), Online.","ama":"Witschen LM, Wiersema T, Artmann M, Platzner M. MUSCAT: MUS-based Circuit Approximation Technique. In: Design, Automation and Test in Europe (DATE).","chicago":"Witschen, Linus Matthias, Tobias Wiersema, Matthias Artmann, and Marco Platzner. “MUSCAT: MUS-Based Circuit Approximation Technique.” In Design, Automation and Test in Europe (DATE), n.d."},"year":"2022","type":"conference","_id":"29865","date_updated":"2022-02-22T07:52:01Z","conference":{"name":"Design, Automation and Test in Europe (DATE)","location":"Online"},"author":[{"first_name":"Linus Matthias","full_name":"Witschen, Linus Matthias","last_name":"Witschen","id":"49051"},{"full_name":"Wiersema, Tobias","first_name":"Tobias","id":"3118","last_name":"Wiersema"},{"first_name":"Matthias","full_name":"Artmann, Matthias","last_name":"Artmann"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"publication":"Design, Automation and Test in Europe (DATE)","department":[{"_id":"78"}],"status":"public","project":[{"name":"SFB 901: SFB 901","_id":"1"},{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"_id":"12","name":"SFB 901 - B4: SFB 901 - Subproject B4"},{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"date_created":"2022-02-16T16:22:23Z","publication_status":"accepted","user_id":"49051","title":"MUSCAT: MUS-based Circuit Approximation Technique"},{"language":[{"iso":"eng"}],"series_title":"Lecture Notes in Computer Science","doi":"10.1007/978-3-031-02462-7_25","date_updated":"2022-04-28T10:24:18Z","project":[{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"},{"_id":"1","name":"SFB 901: SFB 901"}],"publication_identifier":{"issn":["0302-9743","1611-3349"],"isbn":["9783031024610","9783031024627"]},"publication_status":"published","department":[{"_id":"78"}],"title":"Integrating Safety Guarantees into the Learning Classifier System XCS","type":"conference","citation":{"ama":"Hansmeier T, Platzner M. Integrating Safety Guarantees into the Learning Classifier System XCS. In: Applications of Evolutionary Computation, EvoApplications 2022, Proceedings. Vol 13224. Lecture Notes in Computer Science. Springer International Publishing; 2022:386-401. doi:10.1007/978-3-031-02462-7_25","apa":"Hansmeier, T., & Platzner, M. (2022). Integrating Safety Guarantees into the Learning Classifier System XCS. Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, 13224, 386–401. https://doi.org/10.1007/978-3-031-02462-7_25","chicago":"Hansmeier, Tim, and Marco Platzner. “Integrating Safety Guarantees into the Learning Classifier System XCS.” In Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, 13224:386–401. Lecture Notes in Computer Science. Springer International Publishing, 2022. https://doi.org/10.1007/978-3-031-02462-7_25.","mla":"Hansmeier, Tim, and Marco Platzner. “Integrating Safety Guarantees into the Learning Classifier System XCS.” Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, vol. 13224, Springer International Publishing, 2022, pp. 386–401, doi:10.1007/978-3-031-02462-7_25.","bibtex":"@inproceedings{Hansmeier_Platzner_2022, series={Lecture Notes in Computer Science}, title={Integrating Safety Guarantees into the Learning Classifier System XCS}, volume={13224}, DOI={10.1007/978-3-031-02462-7_25}, booktitle={Applications of Evolutionary Computation, EvoApplications 2022, Proceedings}, publisher={Springer International Publishing}, author={Hansmeier, Tim and Platzner, Marco}, year={2022}, pages={386–401}, collection={Lecture Notes in Computer Science} }","short":"T. Hansmeier, M. Platzner, in: Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, Springer International Publishing, 2022, pp. 386–401.","ieee":"T. Hansmeier and M. Platzner, “Integrating Safety Guarantees into the Learning Classifier System XCS,” in Applications of Evolutionary Computation, EvoApplications 2022, Proceedings, Madrid, 2022, vol. 13224, pp. 386–401, doi: 10.1007/978-3-031-02462-7_25."},"year":"2022","page":"386-401","_id":"30971","intvolume":" 13224","conference":{"end_date":"2022-04-22","start_date":"2022-04-20","name":"25th International Conference on Applications of Evolutionary Computation, EvoApplications 2022","location":"Madrid"},"status":"public","date_created":"2022-04-28T09:42:33Z","volume":13224,"author":[{"orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","first_name":"Tim","id":"49992","last_name":"Hansmeier"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"publisher":"Springer International Publishing","publication":"Applications of Evolutionary Computation, EvoApplications 2022, Proceedings","user_id":"49992"},{"language":[{"iso":"eng"}],"page":"120-127","citation":{"short":"L. Clausing, M. Platzner, in: 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–127.","ieee":"L. Clausing and M. Platzner, “ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support,” in 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), Lyon, France, 2022, pp. 120–127, doi: 10.1109/ipdpsw55747.2022.00029.","apa":"Clausing, L., & Platzner, M. (2022). ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support. 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 120–127. https://doi.org/10.1109/ipdpsw55747.2022.00029","ama":"Clausing L, Platzner M. ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support. In: 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW). IEEE; 2022:120-127. doi:10.1109/ipdpsw55747.2022.00029","chicago":"Clausing, Lennart, and Marco Platzner. “ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support.” In 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 120–27. IEEE, 2022. https://doi.org/10.1109/ipdpsw55747.2022.00029.","mla":"Clausing, Lennart, and Marco Platzner. “ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support.” 2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), IEEE, 2022, pp. 120–27, doi:10.1109/ipdpsw55747.2022.00029.","bibtex":"@inproceedings{Clausing_Platzner_2022, title={ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support}, DOI={10.1109/ipdpsw55747.2022.00029}, booktitle={2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)}, publisher={IEEE}, author={Clausing, Lennart and Platzner, Marco}, year={2022}, pages={120–127} }"},"year":"2022","type":"conference","doi":"10.1109/ipdpsw55747.2022.00029","conference":{"end_date":"2022-06-03","location":" Lyon, France","name":"2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","start_date":"2022-05-30"},"_id":"32855","date_updated":"2022-11-18T09:36:00Z","date_created":"2022-08-16T09:58:34Z","project":[{"name":"SFB 901 - T1: SFB 901 -Subproject T1","_id":"83"},{"_id":"1","name":"SFB 901: SFB 901"},{"name":"SFB 901 - T: SFB 901 - Project Area T","_id":"82"}],"status":"public","publication_status":"published","publication_identifier":{"eisbn":["978-1-6654-9747-3"]},"publication":"2022 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)","department":[{"_id":"78"}],"publisher":"IEEE","author":[{"full_name":"Clausing, Lennart","orcid":"0000-0003-3789-6034","first_name":"Lennart","id":"74287","last_name":"Clausing"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"477","title":"ReconOS64: A Hardware Operating System for Modern Platform FPGAs with 64-Bit Support"},{"publisher":"Association for Computing Machinery (ACM)","author":[{"orcid":"0000-0003-1377-3339","full_name":"Hansmeier, Tim","first_name":"Tim","id":"49992","last_name":"Hansmeier"},{"first_name":"Mathis","full_name":"Brede, Mathis","last_name":"Brede"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publication":"GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion","department":[{"_id":"78"}],"status":"public","date_created":"2022-09-02T11:47:17Z","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"14","name":"SFB 901 - C2: SFB 901 - Subproject C2"},{"_id":"4","name":"SFB 901 - C: SFB 901 - Project Area C"}],"publication_status":"published","place":"New York, NY, United States","user_id":"477","title":"XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion","language":[{"iso":"eng"}],"type":"conference","citation":{"bibtex":"@inproceedings{Hansmeier_Brede_Platzner_2022, place={New York, NY, United States}, title={XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion}, DOI={10.1145/3520304.3533977}, booktitle={GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion}, publisher={Association for Computing Machinery (ACM)}, author={Hansmeier, Tim and Brede, Mathis and Platzner, Marco}, year={2022}, pages={2071–2079} }","mla":"Hansmeier, Tim, et al. “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion.” GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), 2022, pp. 2071–79, doi:10.1145/3520304.3533977.","ama":"Hansmeier T, Brede M, Platzner M. XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion. In: GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion. Association for Computing Machinery (ACM); 2022:2071-2079. doi:10.1145/3520304.3533977","apa":"Hansmeier, T., Brede, M., & Platzner, M. (2022). XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion. GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2071–2079. https://doi.org/10.1145/3520304.3533977","chicago":"Hansmeier, Tim, Mathis Brede, and Marco Platzner. “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion.” In GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, 2071–79. New York, NY, United States: Association for Computing Machinery (ACM), 2022. https://doi.org/10.1145/3520304.3533977.","ieee":"T. Hansmeier, M. Brede, and M. Platzner, “XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion,” in GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Boston, MA, USA, 2022, pp. 2071–2079, doi: 10.1145/3520304.3533977.","short":"T. Hansmeier, M. Brede, M. Platzner, in: GECCO ’22: Proceedings of the Genetic and Evolutionary Computation Conference Companion, Association for Computing Machinery (ACM), New York, NY, United States, 2022, pp. 2071–2079."},"year":"2022","page":"2071-2079","_id":"33253","date_updated":"2022-11-18T10:13:22Z","conference":{"end_date":"2022-07-13","name":"International Workshop on Learning Classifier Systems (IWLCS 2022)","start_date":"2022-07-09","location":"Boston, MA, USA"},"doi":"10.1145/3520304.3533977"},{"date_updated":"2022-01-28T08:30:16Z","_id":"29541","main_file_link":[{"url":"https://arxiv.org/abs/2201.07454"}],"language":[{"iso":"eng"}],"type":"preprint","citation":{"mla":"Lienen, Christian, and Marco Platzner. ReconROS Executor: Event-Driven Programming of FPGA-Accelerated ROS 2 Applications. 2022.","bibtex":"@article{Lienen_Platzner_2022, title={ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications}, author={Lienen, Christian and Platzner, Marco}, year={2022} }","chicago":"Lienen, Christian, and Marco Platzner. “ReconROS Executor: Event-Driven Programming of FPGA-Accelerated ROS 2 Applications,” 2022.","apa":"Lienen, C., & Platzner, M. (2022). ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.","ama":"Lienen C, Platzner M. ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications. Published online 2022.","ieee":"C. Lienen and M. Platzner, “ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications.” 2022.","short":"C. Lienen, M. Platzner, (2022)."},"year":"2022","user_id":"60323","title":"ReconROS Executor: Event-Driven Programming of FPGA-accelerated ROS 2 Applications","department":[{"_id":"78"}],"author":[{"first_name":"Christian","full_name":"Lienen, Christian","last_name":"Lienen","id":"60323"},{"full_name":"Platzner, Marco","first_name":"Marco","id":"398","last_name":"Platzner"}],"date_created":"2022-01-26T08:52:20Z","status":"public"},{"user_id":"60323","title":"Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS","department":[{"_id":"78"}],"author":[{"first_name":"Christian","full_name":"Lienen, Christian","last_name":"Lienen","id":"60323"},{"first_name":"Marco","full_name":"Platzner, Marco","last_name":"Platzner","id":"398"}],"date_created":"2022-11-04T09:26:42Z","status":"public","publication_status":"accepted","conference":{"location":"Neaples, Italy","name":"2022 Sixth IEEE International Conference on Robotic Computing (IRC) "},"_id":"34007","date_updated":"2022-11-04T09:26:47Z","language":[{"iso":"eng"}],"citation":{"short":"C. Lienen, M. Platzner, in: n.d.","ieee":"C. Lienen and M. Platzner, “Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS,” presented at the 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.","apa":"Lienen, C., & Platzner, M. (n.d.). Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS. 2022 Sixth IEEE International Conference on Robotic Computing (IRC) , Neaples, Italy.","ama":"Lienen C, Platzner M. Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS.","chicago":"Lienen, Christian, and Marco Platzner. “Task Mapping for Hardware-Accelerated Robotics Applications Using ReconROS,” n.d.","mla":"Lienen, Christian, and Marco Platzner. Task Mapping for Hardware-Accelerated Robotics Applications Using ReconROS.","bibtex":"@inproceedings{Lienen_Platzner, title={Task Mapping for Hardware-Accelerated Robotics Applications using ReconROS}, author={Lienen, Christian and Platzner, Marco} }"},"type":"conference","year":"2022"},{"language":[{"iso":"eng"}],"type":"conference","year":"2022","citation":{"ieee":"C. Lienen and M. Platzner, “Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications,” presented at the 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain, doi: 10.1109/DSD57027.2022.00088.","short":"C. Lienen, M. Platzner, in: 2022 25th Euromicro Conference on Digital System Design (DSD), n.d.","bibtex":"@inproceedings{Lienen_Platzner, title={Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications}, DOI={10.1109/DSD57027.2022.00088}, booktitle={2022 25th Euromicro Conference on Digital System Design (DSD)}, author={Lienen, Christian and Platzner, Marco} }","mla":"Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated ROS 2 Robotics Applications.” 2022 25th Euromicro Conference on Digital System Design (DSD), doi:10.1109/DSD57027.2022.00088.","ama":"Lienen C, Platzner M. Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. In: 2022 25th Euromicro Conference on Digital System Design (DSD). doi:10.1109/DSD57027.2022.00088","apa":"Lienen, C., & Platzner, M. (n.d.). Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications. 2022 25th Euromicro Conference on Digital System Design (DSD). 25th Euromicro Conference on Digital System Design (DSD), Maspalomas, Gran Canaria, Spain. https://doi.org/10.1109/DSD57027.2022.00088","chicago":"Lienen, Christian, and Marco Platzner. “Event-Driven Programming of FPGA-Accelerated ROS 2 Robotics Applications.” In 2022 25th Euromicro Conference on Digital System Design (DSD), n.d. https://doi.org/10.1109/DSD57027.2022.00088."},"doi":"10.1109/DSD57027.2022.00088","conference":{"location":"Maspalomas, Gran Canaria, Spain","name":"25th Euromicro Conference on Digital System Design (DSD)"},"_id":"34005","date_updated":"2023-01-06T06:38:27Z","date_created":"2022-11-04T09:24:47Z","status":"public","publication_status":"accepted","publication":"2022 25th Euromicro Conference on Digital System Design (DSD)","department":[{"_id":"78"}],"author":[{"last_name":"Lienen","id":"60323","first_name":"Christian","full_name":"Lienen, Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"user_id":"60323","title":"Event-Driven Programming of FPGA-accelerated ROS 2 Robotics Applications"},{"date_updated":"2023-04-19T15:04:30Z","_id":"32342","conference":{"start_date":" July 4, 2022","name":"IEEE Computer Society Annual Symposium on VLSI Aliathon Resort,","location":"Pafos, Cyprus","end_date":"July 6, 2022"},"citation":{"short":"Q.A. Ahmed, M. Platzner, in: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), Pafos, Cyprus, 2022.","ieee":"Q. A. Ahmed and M. Platzner, “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs,” presented at the IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus, 2022.","ama":"Ahmed QA, Platzner M. On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs. In: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022); 2022.","apa":"Ahmed, Q. A., & Platzner, M. (2022). On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs. IEEE Computer Society Annual Symposium on VLSI Aliathon Resort, Pafos, Cyprus.","chicago":"Ahmed, Qazi Arbab, and Marco Platzner. “On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs.” Pafos, Cyprus: IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), 2022.","bibtex":"@inproceedings{Ahmed_Platzner_2022, place={Pafos, Cyprus}, title={On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs}, publisher={IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)}, author={Ahmed, Qazi Arbab and Platzner, Marco}, year={2022} }","mla":"Ahmed, Qazi Arbab, and Marco Platzner. On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs. IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022), 2022."},"year":"2022","type":"conference","language":[{"iso":"eng"}],"title":"On the Detection and Circumvention of Bitstream-Level Trojans in FPGAs","user_id":"72764","place":"Pafos, Cyprus","status":"public","date_created":"2022-07-12T19:56:48Z","project":[{"_id":"1","name":"SFB 901: SFB 901"},{"_id":"3","name":"SFB 901 - B: SFB 901 - Project Area B"},{"name":"SFB 901 - B4: SFB 901 - Subproject B4","_id":"12"}],"author":[{"id":"72764","last_name":"Ahmed","orcid":"0000-0002-1837-2254","full_name":"Ahmed, Qazi Arbab","first_name":"Qazi Arbab"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE Computer Society Annual Symposium on VLSI (ISVLSI,2022)","department":[{"_id":"78"}]},{"project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"publication_status":"published","department":[{"_id":"78"}],"title":"RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures","language":[{"iso":"eng"}],"doi":"10.1109/MM.2022.3202091","date_updated":"2023-04-04T15:09:17Z","date_created":"2022-11-03T14:42:16Z","status":"public","volume":42,"publication":"IEEE Micro","author":[{"full_name":"Jentzsch, Felix","orcid":"0000-0003-4987-5708","first_name":"Felix","id":"55631","last_name":"Jentzsch"},{"full_name":"Umuroglu, Yaman","first_name":"Yaman","last_name":"Umuroglu"},{"first_name":"Alessandro","full_name":"Pappalardo, Alessandro","last_name":"Pappalardo"},{"full_name":"Blott, Michaela","first_name":"Michaela","last_name":"Blott"},{"id":"398","last_name":"Platzner","full_name":"Platzner, Marco","first_name":"Marco"}],"publisher":"IEEE","user_id":"55631","abstract":[{"text":"Deep neural networks (DNNs) are penetrating into a broad spectrum of applications and replacing manual algorithmic implementations, including the radio frequency communications domain with classical signal processing algorithms. However, the high throughput (gigasamples per second) and low latency requirements of this application domain pose a significant hurdle for adopting computationally demanding DNNs. In this article, we explore highly specialized DNN inference accelerator approaches on field-programmable gate arrays (FPGAs) for RadioML modulation classification. Using an automated end-to-end flow for the generation of the FPGA solution, we can easily explore a spectrum of solutions that optimize for different design targets, including accuracy, power efficiency, resources, throughput, and latency. By leveraging reduced precision arithmetic and customized streaming dataflow, we demonstrate a solution that meets the application requirements and outperforms alternative FPGA efforts by 3.5x in terms of throughput. Against modern embedded graphics processing units (GPUs), we measure >10x higher throughput and >100x lower latency under comparable accuracy and power envelopes.","lang":"eng"}],"page":"125-133","year":"2022","citation":{"mla":"Jentzsch, Felix, et al. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.” IEEE Micro, vol. 42, no. 6, IEEE, 2022, pp. 125–33, doi:10.1109/MM.2022.3202091.","bibtex":"@article{Jentzsch_Umuroglu_Pappalardo_Blott_Platzner_2022, title={RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures}, volume={42}, DOI={10.1109/MM.2022.3202091}, number={6}, journal={IEEE Micro}, publisher={IEEE}, author={Jentzsch, Felix and Umuroglu, Yaman and Pappalardo, Alessandro and Blott, Michaela and Platzner, Marco}, year={2022}, pages={125–133} }","chicago":"Jentzsch, Felix, Yaman Umuroglu, Alessandro Pappalardo, Michaela Blott, and Marco Platzner. “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures.” IEEE Micro 42, no. 6 (2022): 125–33. https://doi.org/10.1109/MM.2022.3202091.","apa":"Jentzsch, F., Umuroglu, Y., Pappalardo, A., Blott, M., & Platzner, M. (2022). RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. IEEE Micro, 42(6), 125–133. https://doi.org/10.1109/MM.2022.3202091","ama":"Jentzsch F, Umuroglu Y, Pappalardo A, Blott M, Platzner M. RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures. IEEE Micro. 2022;42(6):125-133. doi:10.1109/MM.2022.3202091","ieee":"F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, and M. Platzner, “RadioML Meets FINN: Enabling Future RF Applications With FPGA Streaming Architectures,” IEEE Micro, vol. 42, no. 6, pp. 125–133, 2022, doi: 10.1109/MM.2022.3202091.","short":"F. Jentzsch, Y. Umuroglu, A. Pappalardo, M. Blott, M. Platzner, IEEE Micro 42 (2022) 125–133."},"type":"journal_article","main_file_link":[{"url":"https://ieeexplore.ieee.org/document/9933377"}],"issue":"6","_id":"33990","intvolume":" 42"},{"date_updated":"2022-01-06T06:58:46Z","_id":"29150","doi":"10.1145/3494571","language":[{"iso":"eng"}],"page":"1-20","citation":{"ieee":"C. Lienen and M. Platzner, “Design of Distributed Reconfigurable Robotics Systems with ReconROS,” ACM Transactions on Reconfigurable Technology and Systems, pp. 1–20, 2021, doi: 10.1145/3494571.","short":"C. Lienen, M. Platzner, ACM Transactions on Reconfigurable Technology and Systems (2021) 1–20.","bibtex":"@article{Lienen_Platzner_2021, title={Design of Distributed Reconfigurable Robotics Systems with ReconROS}, DOI={10.1145/3494571}, journal={ACM Transactions on Reconfigurable Technology and Systems}, author={Lienen, Christian and Platzner, Marco}, year={2021}, pages={1–20} }","mla":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” ACM Transactions on Reconfigurable Technology and Systems, 2021, pp. 1–20, doi:10.1145/3494571.","ama":"Lienen C, Platzner M. Design of Distributed Reconfigurable Robotics Systems with ReconROS. ACM Transactions on Reconfigurable Technology and Systems. Published online 2021:1-20. doi:10.1145/3494571","apa":"Lienen, C., & Platzner, M. (2021). Design of Distributed Reconfigurable Robotics Systems with ReconROS. ACM Transactions on Reconfigurable Technology and Systems, 1–20. https://doi.org/10.1145/3494571","chicago":"Lienen, Christian, and Marco Platzner. “Design of Distributed Reconfigurable Robotics Systems with ReconROS.” ACM Transactions on Reconfigurable Technology and Systems, 2021, 1–20. https://doi.org/10.1145/3494571."},"type":"journal_article","year":"2021","abstract":[{"lang":"eng","text":"Robotics applications process large amounts of data in real time and require compute platforms that provide high performance and energy efficiency. FPGAs are well suited for many of these applications, but there is a reluctance in the robotics community to use hardware acceleration due to increased design complexity and a lack of consistent programming models across the software/hardware boundary. In this article, we present ReconROS, a framework that integrates the widely used robot operating system (ROS) with ReconOS, which features multithreaded programming of hardware and software threads for reconfigurable computers. This unique combination gives ROS 2 developers the flexibility to transparently accelerate parts of their robotics applications in hardware. We elaborate on the architecture and the design flow for ReconROS and report on a set of experiments that underline the feasibility and flexibility of our approach."}],"user_id":"60323","title":"Design of Distributed Reconfigurable Robotics Systems with ReconROS","department":[{"_id":"78"}],"publication":"ACM Transactions on Reconfigurable Technology and Systems","author":[{"id":"60323","last_name":"Lienen","full_name":"Lienen, Christian","first_name":"Christian"},{"last_name":"Platzner","id":"398","first_name":"Marco","full_name":"Platzner, Marco"}],"date_created":"2022-01-04T08:30:10Z","status":"public","publication_identifier":{"issn":["1936-7406","1936-7414"]},"publication_status":"published"}]