Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine - Dyer, Matthias; Platzner, Marco; Thiele, Lothar (Proceedings 12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM))

TKDM – A Reconfigurable Co-processor in a PC's Memory Slot - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Technology (ICFPT))
This paper presents TKDM, a PC-based high-performance reconfigurable computing environment. The TKDM hardware consists of an FPGA module that uses the DIMM (dual inline memory module) bus for high-bandwidth and low-latency communication with the host CPU. The system's firmware is integrated with the Linux host operating system and offers functions for data communication and FPGA reconfiguration. The intended use of TKDM is that of a dynamically reconfigurable co-processor for data streaming applications. The system's firmware can be customized for specific application domains to facilitate simple and easy-to-use programming interfaces.
Keywords: coprocessor; DIMM; memory bus; FPGA; high performance computing

The Case for Reconfigurable Hardware in Wearable Computing - Plessl, Christian; Enzler, Rolf; Walder, Herbert; Beutel, Jan; Platzner, Marco; Thiele, Lothar; Tröster, Gerhard (Personal and Ubiquitous Computing)
Wearable computers are embedded into the mobile environment of their users. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with the low energy consumption required to maximise battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we present an experiment with an operating system layer for WURM.

Instance-Specific Accelerators for Minimum Covering - Plessl, Christian; Platzner, Marco (Journal of Supercomputing)
This paper presents the acceleration of minimum-cost covering problems by instance-specific hardware. First, we formulate the minimum-cost covering problem and discuss a branch & bound algorithm to solve it. Then we describe instance-specific hardware architectures that implement branch & bound in 3-valued logic and use reduction techniques similar to those found in software solvers. We further present prototypical accelerator implementations and a corresponding design tool flow. Our experiments reveal significant raw speedups up to five orders of magnitude for a set of smaller unate covering problems. Provided that hardware compilation times can be reduced, we conclude that instance-specific acceleration of hard minimum-cost covering problems will lead to substantial overall speedups.
Keywords: reconfigurable computing; instance-specific acceleration; minimum covering

Virtualizing Hardware with Multi-Context Reconfigurable Arrays - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
In contrast to processors, current reconfigurable devices totally lack programming models that would allow for device independent compilation and forward compatibility. The key to overcome this limitation is hardware virtualization. In this paper, we resort to a macro-pipelined execution model to achieve hardware virtualization for data streaming applications. As a hardware implementation we present a hybrid multi-context architecture that attaches a coarse-grained reconfigurable array to a host CPU. A co-simulation framework enables cycle-accurate simulation of the complete architecture. As a case study we map an FIR filter to our virtualized hardware model and evaluate different designs. We discuss the impact of the number of contexts and the feature of context state on the speedup and the CPU load.
Keywords: Zippy; multi-context; FPGA

Co-simulation of a Hybrid Multi-Context Architecture - Enzler, Rolf; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
Reconfigurable computing architectures aim to dynamically adapt their hardware to the application at hand. As research shows, the time it takes to reconfigure the hardware forms an overhead that can significantly impair the benefits of hardware customization. Multi-context devices are one promising approach to overcome the limitations posed by long reconfiguration times. In contrast to more traditional reconfigurable architectures, multi-context devices hold several configurations on-chip. On demand, the device can quickly switch to another context. In this paper we present a co-simulation environment to investigate design trade-offs for hybrid multi-context architectures. Our architectural model comprises a reconfigurable unit closely coupled to a CPU core. As a case study, we discuss the implementation of a FIR filter partitioned into several contexts. We outline the mapping process and present simulation results for single- and multi-context reconfigurable units coupled with both embedded and high-end CPUs.
Keywords: Zippy; co-simulation

Online scheduling for block-partitioned reconfigurable devices - Walder, Herbert; Platzner, Marco (Proceedings Design, Automation and Test in Europe Conference (DATE))

Fast online task placement on FPGAs: free space partitioning and 2D-hashing - Walder, Herbert; Steiger, Christoph; Platzner, Marco (Proceedings International Parallel and Distributed Processing Symposium)

Reconfigurable Hardware Operating Systems: From Design Concepts to Realizations - Walder, Herbert; Platzner, Marco (Proceedings of the 3rd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Heuristics for Online Scheduling Real-Time Tasks to Partially Reconfigurable Devices - Steiger, Christoph; Walder, Herbert; Platzner, Marco (Proceedings of the 13th International Conference on Field Programmable Logic and Applications (FPL))

Online scheduling and placement of real-time tasks to partially reconfigurable devices - Steiger, Christoph; Walder, Herbert; Platzner, Marco; Thiele, Lothar (Proceedings 24th IEEE International Real-Time Systems Symposium (RTSS))

Reconfigurable Hardware in Wearable Computing Nodes - Plessl, Christian; Enzler, Rolf; Walder, Herbert; Beutel, Jan; Platzner, Marco; Thiele, Lothar (Proc. Int. Symp. on Wearable Computers (ISWC))
Wearable computers are embedded into the mobile environment of the human body. A design challenge for wearable systems is to combine the high performance required for tasks such as video decoding with low energy consumption required to maximize battery runtimes and the flexibility demanded by the dynamics of the environment and the applications. In this paper, we demonstrate that reconfigurable hardware technology is able to answer this challenge. We present the concept and the prototype implementation of an autonomous wearable unit with reconfigurable modules (WURM). We discuss two experiments that show the uses of reconfigurable hardware in WURM: ASICs-on-demand and adaptive interfaces. Finally, we develop and evaluate task placement techniques used in the operating system layer of WURM.
Keywords: wearable computing

Partially Reconfigurable Cores for Xilinx Virtex - Dyer, Matthias; Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Field Programmable Logic and Applications (FPL))
Recent generations of high-density and high-speed FPGAs provide a sufficient capacity for implementing complete configurable systems on a chip (CSoCs). Hybrid CPUs that combine standard CPU cores with reconfigurable coprocessors are an important subclass of CSoCs. With partially reconfigurable FPGAs, coprocessors can be loaded on demand while the CPU remains running. However, the lack of high-level design tools for partial reconfiguration makes practical implementations a challenging task. In this paper, we introduce a design flow to implement hybrid processors on Xilinx Virtex. The design flow is based on two techniques, virtual sockets and feed-through components, and can efficiently generate partial configurations from industry-quality cores. We discuss the design flow and present a fully operational audio streaming prototype to demonstrate its feasibility.
Keywords: partial reconfiguration

Custom Computing Machines for the Set Covering Problem - Plessl, Christian; Platzner, Marco (Proc. Int. Symp. on Field-Programmable Custom Computing Machines (FCCM))
We present instance-specific custom computing machines for the set covering problem. Four accelerator architectures are developed that implement branch & bound in 3-valued logic and many of the deduction techniques found in software solvers. We use set covering benchmarks from two-level logic minimization and Steiner triple systems to derive and discuss experimental results. The resulting raw speedups are in the order of four magnitudes on average. Finally, we propose a hybrid solver architecture that combines the raw speed of instance-specific reconfigurable hardware with flexible bounding schemes implemented in software.

A Framework for Run-time Reconfigurable Systems - Eisenring, Michael; Platzner, Marco (The Journal of Supercomputing)

Non-preemptive Multitasking on FPGAs: Task Placement and Footprint Transform - Walder, Herbert; Platzner, Marco (Proceedings of the 2nd International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA))

Instance-Specific Accelerators for Minimum Covering - Plessl, Christian; Platzner, Marco (Proc. Int. Conf. on Engineering of Reconfigurable Systems and Algorithms (ERSA))
In this paper we present instance-specific accelerators for minimum-cost covering problems. We first define the covering problem and discuss a branch&bound algorithm to solve it. Then we describe an instance-specific hardware architecture that implements branch&bound in 3-valued logic and uses reduction techniques usually found in software solvers. Results for small unate covering problems reveal significant raw speedups.
Keywords: minimum covering; accelerator; funding-sundance

Reconfigurable Processors for Handhelds and Wearables: Application Analysis - Enzler, Rolf; Platzner, Marco; Plessl, Christian; Thiele, Lothar; Tröster, Gerhard (Reconfigurable Technology: FPGAs and Reconfigurable Processors for Computing and Communications III)
In this paper, we present the analysis of applications from the domain of handheld and wearable computing. This analysis is the first step to derive and evaluate design parameters for dynamically reconfigurable processors. We discuss the selection of representative benchmarks for handhelds and wearables and group the applications into multimedia, communications, and cryptography programs. We simulate the applications on a cycle-accurate processor simulator and gather statistical data such as instruction mix, cache hit rates and memory requirements for an embedded processor model. A breakdown of the executed cycles into different functions identifies the most compute-intensive code sections - the kernels. Then, we analyze the applications and discuss parameters that strongly influence the design of dynamically reconfigurable processors. Finally, we outline the construction of a parameterizable simulation model for a reconfigurable unit that is attached to a processor core.
Keywords: benchmark

Object-oriented domain specific compilers for programming FPGAs - Mencer, Oskar; Platzner, Marco; Morf, Martin; J. Flynn, Michael (IEEE Transactions on Very Large Scale Integration (VLSI) Systems)

Dynamically Reconfigurable Processors - Enzler, Rolf; Platzner, Marco