@article{62148,
  author       = {{Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt, J. Christoph}},
  issn         = {{1063-8210}},
  journal      = {{IEEE Transactions on Very Large Scale Integration (VLSI) Systems}},
  publisher    = {{IEEE}},
  title        = {{{60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design}}},
  doi          = {{10.1109/TVLSI.2025.3625787}},
  year         = {{2025}},
}

@inproceedings{62126,
  author       = {{Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{IEEE Nordic Circuits and Systems Conference (NORCAS)}},
  location     = {{Riga, Latvia}},
  title        = {{{A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology}}},
  doi          = {{10.1109/NorCAS66540.2025.11231203}},
  year         = {{2025}},
}

@inproceedings{53579,
  author       = {{Palomero Bernardo, Paul and Schmid, Patrick and Bringmann, Oliver and Iftekhar, Mohammed and Sadiye, Babak and Müller, Wolfgang and Koch, Andreas and Jentsch, Eyck and Sauer, Axel and Feldner, Ingo and Ecker, Wolfgang}},
  booktitle    = {{DATE 24 - Design Automation and Test in Europe}},
  location     = {{Valencia, Spain}},
  title        = {{{A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing}}},
  year         = {{2024}},
}

@misc{48631,
  author       = {{Iftekhar, Mohammed and Scheytt, J. Christoph}},
  title        = {{{ ENHANCED PLL CIRCUIT}}},
  year         = {{2023}},
}

@inproceedings{48961,
  author       = {{Iftekhar, Mohammed and Gowda, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, Christoph}},
  booktitle    = {{2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)}},
  location     = {{Monterey, CA, USA}},
  title        = {{{A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology}}},
  doi          = {{10.1109/BCICTS54660.2023.10310954}},
  year         = {{2023}},
}

@inproceedings{47064,
  author       = {{Iftekhar, Mohammed and Nagaraju, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}},
  booktitle    = {{BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium}},
  location     = {{MONTEREY, CALIFORNIA, USA}},
  title        = {{{A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology }}},
  year         = {{2023}},
}

@inproceedings{29770,
  author       = {{Abughannam, Saed and Kruse, Stephan and Iftekhar, Mohammed and Scheytt, J. Christoph}},
  booktitle    = {{German Microwave Conference 2022 (GeMiC 2022)}},
  title        = {{{Design and Measurements of a Low-power Low-Date-rate Direct-detection Wireless Receiver with Improved Co-channel Interference Robustness}}},
  year         = {{2022}},
}

@inproceedings{29213,
  abstract     = {{This paper presents a technique to extend the frequency acquisition range for bang-bang phase-detector-based clock and data recovery (CDR) circuits without an additional frequency acquisition loop or lock detection circuit. The per-manent modulation of the offset current in the CDR's integral branch enhances the acquisition range by nearly 4 times, covering the entire tuning range of the voltage controlled oscillator. The increase in power dissipation and the chip area are negligible. This technique was implemented and measured in a 28 Gbps NRZ bang-bang CDR chip to confirm the working principle. In addition to the increased acquisition range, the CDR also surpasses jitter related specifications from the OIF CEI-28G-VSR standard.}},
  author       = {{Iftekhar, Mohammed and Gudyriev, Sergiy and Scheytt, J. Christoph}},
  booktitle    = {{The 2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium}},
  title        = {{{Reference-less Bang-bang CDR with Enhanced Frequency Acquisition Range Using Static and Modulated Integral Branch Offset Currents}}},
  doi          = {{10.1109/BCICTS50416.2021.9682207}},
  year         = {{2021}},
}

@inproceedings{24028,
  abstract     = {{A 28 Gbps NRZ bang-bang clock and data recovery (CDR) chip for 100G PSM4 is presented. It exhibits an adaptable loop filter transfer function with independently tunable proportional and integral parameters. This allows to optimize the jitter transfer, jitter tolerance, and locking range of the CDR according to system requirements. The CDR represents a key component for a single-chip 8-channel electronic-photonic PSM4 transceiver. A CDR chip was manufactured in a 0.25 μm monolithic photonic BiCMOS technology. The core chip area is 0.51 mm 2 and it dissipates 330 mW from 2.5 V and 3.3 V power supplies.}},
  author       = {{Iftekhar, Mohammed and Gudyriev, Sergiy and Scheytt, Christoph}},
  booktitle    = {{2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)}},
  publisher    = {{IEEE}},
  title        = {{{28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop Filter in 0.25 µm Photonic BiCMOS Technology}}},
  doi          = {{10.1109/SIRF46766.2020.9040190}},
  year         = {{2020}},
}