---
_id: '62148'
author:
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Sadiye B, Iftekhar M, Müller W, Scheytt JC. 60-Gb/s 1:4 Demultiplexer in 22-nm
FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. Published
online 2025. doi:10.1109/TVLSI.2025.3625787'
apa: 'Sadiye, B., Iftekhar, M., Müller, W., & Scheytt, J. C. (2025). 60-Gb/s
1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design. IEEE Transactions on Very Large Scale Integration (VLSI)
Systems. https://doi.org/10.1109/TVLSI.2025.3625787'
bibtex: '@article{Sadiye_Iftekhar_Müller_Scheytt_2025, title={60-Gb/s 1:4 Demultiplexer
in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis
and Design}, DOI={10.1109/TVLSI.2025.3625787},
journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems}, publisher={IEEE},
author={Sadiye, Babak and Iftekhar, Mohammed and Müller, Wolfgang and Scheytt,
J. Christoph}, year={2025} }'
chicago: 'Sadiye, Babak, Mohammed Iftekhar, Wolfgang Müller, and J. Christoph Scheytt.
“60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design.” IEEE Transactions on Very Large Scale Integration (VLSI)
Systems, 2025. https://doi.org/10.1109/TVLSI.2025.3625787.'
ieee: 'B. Sadiye, M. Iftekhar, W. Müller, and J. C. Scheytt, “60-Gb/s 1:4 Demultiplexer
in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level Analysis
and Design,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems,
2025, doi: 10.1109/TVLSI.2025.3625787.'
mla: 'Sadiye, Babak, et al. “60-Gb/s 1:4 Demultiplexer in 22-Nm FD-SOI Technology
Using TSPC Logic: A Circuit-to-System-Level Analysis and Design.” IEEE Transactions
on Very Large Scale Integration (VLSI) Systems, IEEE, 2025, doi:10.1109/TVLSI.2025.3625787.'
short: B. Sadiye, M. Iftekhar, W. Müller, J.C. Scheytt, IEEE Transactions on Very
Large Scale Integration (VLSI) Systems (2025).
date_created: 2025-11-10T08:31:47Z
date_updated: 2025-11-10T08:38:07Z
department:
- _id: '58'
doi: 10.1109/TVLSI.2025.3625787
language:
- iso: eng
project:
- _id: '325'
name: 'Scale4Edge: Skalierbare Infrastruktur für Edge-Computing'
publication: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
publication_identifier:
issn:
- 1063-8210
publication_status: published
publisher: IEEE
status: public
title: '60-Gb/s 1:4 Demultiplexer in 22-nm FD-SOI Technology Using TSPC Logic: A Circuit-to-System-Level
Analysis and Design'
type: journal_article
user_id: '93634'
year: '2025'
...
---
_id: '62126'
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Iftekhar M, Sadiye B, Müller W, Scheytt JC. A 50 Gbps Reference-less NRZ Full-rate
Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C BiCMOS Technology.
In: IEEE Nordic Circuits and Systems Conference (NORCAS). ; 2025. doi:10.1109/NorCAS66540.2025.11231203'
apa: Iftekhar, M., Sadiye, B., Müller, W., & Scheytt, J. C. (2025). A 50 Gbps
Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition
in 130 nm SiGe:C BiCMOS Technology. IEEE Nordic Circuits and Systems Conference
(NORCAS). IEEE Nordic Circuits and Systems Conference (NORCAS), Riga, Latvia.
https://doi.org/10.1109/NorCAS66540.2025.11231203
bibtex: '@inproceedings{Iftekhar_Sadiye_Müller_Scheytt_2025, title={A 50 Gbps Reference-less
NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C
BiCMOS Technology}, DOI={10.1109/NorCAS66540.2025.11231203},
booktitle={IEEE Nordic Circuits and Systems Conference (NORCAS)}, author={Iftekhar,
Mohammed and Sadiye, Babak and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025}
}'
chicago: Iftekhar, Mohammed, Babak Sadiye, Wolfgang Müller, and J. Christoph Scheytt.
“A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang CDR with Automatic Frequency
Acquisition in 130 Nm SiGe:C BiCMOS Technology.” In IEEE Nordic Circuits and
Systems Conference (NORCAS), 2025. https://doi.org/10.1109/NorCAS66540.2025.11231203.
ieee: 'M. Iftekhar, B. Sadiye, W. Müller, and J. C. Scheytt, “A 50 Gbps Reference-less
NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130 nm SiGe:C
BiCMOS Technology,” presented at the IEEE Nordic Circuits and Systems Conference
(NORCAS), Riga, Latvia, 2025, doi: 10.1109/NorCAS66540.2025.11231203.'
mla: Iftekhar, Mohammed, et al. “A 50 Gbps Reference-Less NRZ Full-Rate Bang-Bang
CDR with Automatic Frequency Acquisition in 130 Nm SiGe:C BiCMOS Technology.”
IEEE Nordic Circuits and Systems Conference (NORCAS), 2025, doi:10.1109/NorCAS66540.2025.11231203.
short: 'M. Iftekhar, B. Sadiye, W. Müller, J.C. Scheytt, in: IEEE Nordic Circuits
and Systems Conference (NORCAS), 2025.'
conference:
end_date: 2025-10-29
location: Riga, Latvia
name: IEEE Nordic Circuits and Systems Conference (NORCAS)
start_date: 2025-10-28
date_created: 2025-11-07T10:41:45Z
date_updated: 2025-11-20T10:34:13Z
department:
- _id: '58'
doi: 10.1109/NorCAS66540.2025.11231203
language:
- iso: eng
project:
- _id: '325'
name: 'Scale4Edge: Skalierbare Infrastruktur für Edge-Computing'
publication: IEEE Nordic Circuits and Systems Conference (NORCAS)
status: public
title: A 50 Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency
Acquisition in 130 nm SiGe:C BiCMOS Technology
type: conference
user_id: '47944'
year: '2025'
...
---
_id: '53579'
author:
- first_name: Paul
full_name: Palomero Bernardo, Paul
last_name: Palomero Bernardo
- first_name: Patrick
full_name: Schmid, Patrick
last_name: Schmid
- first_name: Oliver
full_name: Bringmann, Oliver
last_name: Bringmann
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Andreas
full_name: Koch, Andreas
last_name: Koch
- first_name: Eyck
full_name: Jentsch, Eyck
last_name: Jentsch
- first_name: Axel
full_name: Sauer, Axel
last_name: Sauer
- first_name: Ingo
full_name: Feldner, Ingo
last_name: Feldner
- first_name: Wolfgang
full_name: Ecker, Wolfgang
last_name: Ecker
citation:
ama: 'Palomero Bernardo P, Schmid P, Bringmann O, et al. A Scalable RISC-V Hardware
Platform for Intelligent Sensor Processing. In: DATE 24 - Design Automation
and Test in Europe. ; 2024.'
apa: Palomero Bernardo, P., Schmid, P., Bringmann, O., Iftekhar, M., Sadiye, B.,
Müller, W., Koch, A., Jentsch, E., Sauer, A., Feldner, I., & Ecker, W. (2024).
A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing. DATE
24 - Design Automation and Test in Europe.
bibtex: '@inproceedings{Palomero Bernardo_Schmid_Bringmann_Iftekhar_Sadiye_Müller_Koch_Jentsch_Sauer_Feldner_et
al._2024, title={A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing},
booktitle={DATE 24 - Design Automation and Test in Europe}, author={Palomero Bernardo,
Paul and Schmid, Patrick and Bringmann, Oliver and Iftekhar, Mohammed and Sadiye,
Babak and Müller, Wolfgang and Koch, Andreas and Jentsch, Eyck and Sauer, Axel
and Feldner, Ingo and et al.}, year={2024} }'
chicago: Palomero Bernardo, Paul, Patrick Schmid, Oliver Bringmann, Mohammed Iftekhar,
Babak Sadiye, Wolfgang Müller, Andreas Koch, et al. “A Scalable RISC-V Hardware
Platform for Intelligent Sensor Processing.” In DATE 24 - Design Automation
and Test in Europe, 2024.
ieee: P. Palomero Bernardo et al., “A Scalable RISC-V Hardware Platform for
Intelligent Sensor Processing,” Valencia, Spain, 2024.
mla: Palomero Bernardo, Paul, et al. “A Scalable RISC-V Hardware Platform for Intelligent
Sensor Processing.” DATE 24 - Design Automation and Test in Europe, 2024.
short: 'P. Palomero Bernardo, P. Schmid, O. Bringmann, M. Iftekhar, B. Sadiye, W.
Müller, A. Koch, E. Jentsch, A. Sauer, I. Feldner, W. Ecker, in: DATE 24 - Design
Automation and Test in Europe, 2024.'
conference:
location: Valencia, Spain
date_created: 2024-04-18T20:25:23Z
date_updated: 2024-04-18T20:25:29Z
department:
- _id: '58'
language:
- iso: eng
publication: DATE 24 - Design Automation and Test in Europe
status: public
title: A Scalable RISC-V Hardware Platform for Intelligent Sensor Processing
type: conference
user_id: '16243'
year: '2024'
...
---
_id: '48631'
application_date: 2022-12-01
application_number: PCT/EP2022/083987
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: Iftekhar M, Scheytt JC. ENHANCED PLL CIRCUIT. Published online 2023.
apa: Iftekhar, M., & Scheytt, J. C. (2023). ENHANCED PLL CIRCUIT.
bibtex: '@article{Iftekhar_Scheytt_2023, title={ ENHANCED PLL CIRCUIT}, author={Iftekhar,
Mohammed and Scheytt, J. Christoph}, year={2023} }'
chicago: Iftekhar, Mohammed, and J. Christoph Scheytt. “ ENHANCED PLL CIRCUIT,”
2023.
ieee: M. Iftekhar and J. C. Scheytt, “ ENHANCED PLL CIRCUIT.” 2023.
mla: Iftekhar, Mohammed, and J. Christoph Scheytt. ENHANCED PLL CIRCUIT.
2023.
short: M. Iftekhar, J.C. Scheytt, (2023).
date_created: 2023-11-06T12:14:10Z
date_updated: 2023-11-06T12:14:44Z
ipc: H03L7/0807(2006.1), H03L7/08(2006.1), H03L7/089(2006.1), H03L7/093(2006.1)
ipn: WO/2023/099639
main_file_link:
- open_access: '1'
url: https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2023099639
oa: '1'
publication_date: 2023-06-08
status: public
title: ' ENHANCED PLL CIRCUIT'
type: patent
user_id: '47944'
year: '2023'
...
---
_id: '48961'
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Harshan
full_name: Gowda, Harshan
last_name: Gowda
- first_name: Pascal
full_name: Kneuper, Pascal
id: '47367'
last_name: Kneuper
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Iftekhar M, Gowda H, Kneuper P, Sadiye B, Müller W, Scheytt C. A 28-Gb/s 27.2mW
NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology.
In: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology
Symposium (BCICTS). ; 2023. doi:10.1109/BCICTS54660.2023.10310954'
apa: Iftekhar, M., Gowda, H., Kneuper, P., Sadiye, B., Müller, W., & Scheytt,
C. (2023). A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in
22 nm FD-SOI CMOS Technology. 2023 IEEE BiCMOS and Compound Semiconductor Integrated
Circuits and Technology Symposium (BCICTS). 2023 IEEE BiCMOS und Compound
Semiconductor Integrated Circuits and Technology Symposium (BCICTS), Monterey,
CA, USA. https://doi.org/10.1109/BCICTS54660.2023.10310954
bibtex: '@inproceedings{Iftekhar_Gowda_Kneuper_Sadiye_Müller_Scheytt_2023, title={A
28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology}, DOI={10.1109/BCICTS54660.2023.10310954},
booktitle={2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and
Technology Symposium (BCICTS)}, author={Iftekhar, Mohammed and Gowda, Harshan
and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and Scheytt, Christoph},
year={2023} }'
chicago: Iftekhar, Mohammed, Harshan Gowda, Pascal Kneuper, Babak Sadiye, Wolfgang
Müller, and Christoph Scheytt. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock
and Data Recovery in 22 Nm FD-SOI CMOS Technology.” In 2023 IEEE BiCMOS and
Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS),
2023. https://doi.org/10.1109/BCICTS54660.2023.10310954.
ieee: 'M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, and C. Scheytt,
“A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology,” presented at the 2023 IEEE BiCMOS und Compound Semiconductor
Integrated Circuits and Technology Symposium (BCICTS), Monterey, CA, USA, 2023,
doi: 10.1109/BCICTS54660.2023.10310954.'
mla: Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock
and Data Recovery in 22 Nm FD-SOI CMOS Technology.” 2023 IEEE BiCMOS and Compound
Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2023,
doi:10.1109/BCICTS54660.2023.10310954.
short: 'M. Iftekhar, H. Gowda, P. Kneuper, B. Sadiye, W. Müller, C. Scheytt, in:
2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology
Symposium (BCICTS), 2023.'
conference:
end_date: 2023-10-18
location: Monterey, CA, USA
name: 2023 IEEE BiCMOS und Compound Semiconductor Integrated Circuits and Technology
Symposium (BCICTS)
start_date: 2023-10-16
date_created: 2023-11-16T11:04:41Z
date_updated: 2024-04-19T11:43:21Z
department:
- _id: '58'
doi: 10.1109/BCICTS54660.2023.10310954
language:
- iso: eng
publication: 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology
Symposium (BCICTS)
publication_identifier:
eisbn:
- 979-8-3503-0764-1
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/10310954
status: public
title: A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology
type: conference_abstract
user_id: '15931'
year: '2023'
...
---
_id: '47064'
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Harshan
full_name: Nagaraju, Harshan
last_name: Nagaraju
- first_name: Pascal
full_name: Kneuper, Pascal
id: '47367'
last_name: Kneuper
- first_name: Babak
full_name: Sadiye, Babak
id: '93634'
last_name: Sadiye
- first_name: Wolfgang
full_name: Müller, Wolfgang
id: '16243'
last_name: Müller
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Iftekhar M, Nagaraju H, Kneuper P, Sadiye B, Müller W, Scheytt JC. A 28-Gb/s
27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI CMOS Technology
. In: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits
and Technology Symposium. ; 2023.'
apa: Iftekhar, M., Nagaraju, H., Kneuper, P., Sadiye, B., Müller, W., & Scheytt,
J. C. (2023). A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery
in 22 nm FD-SOI CMOS Technology . BCICTS 2023 IEEE BiCMOS and Compound Semiconductor
Integrated Circuits and Technology Symposium.
bibtex: '@inproceedings{Iftekhar_Nagaraju_Kneuper_Sadiye_Müller_Scheytt_2023, title={A
28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology }, booktitle={BCICTS 2023 IEEE BiCMOS and Compound Semiconductor
Integrated Circuits and Technology Symposium}, author={Iftekhar, Mohammed and
Nagaraju, Harshan and Kneuper, Pascal and Sadiye, Babak and Müller, Wolfgang and
Scheytt, J. Christoph}, year={2023} }'
chicago: Iftekhar, Mohammed, Harshan Nagaraju, Pascal Kneuper, Babak Sadiye, Wolfgang
Müller, and J. Christoph Scheytt. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock
and Data Recovery in 22 Nm FD-SOI CMOS Technology .” In BCICTS 2023 IEEE BiCMOS
and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.
ieee: M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, and J. C. Scheytt,
“A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm FD-SOI
CMOS Technology ,” MONTEREY, CALIFORNIA, USA, 2023.
mla: Iftekhar, Mohammed, et al. “A 28-Gb/s 27.2 MW NRZ Full-Rate Bang-Bang Clock
and Data Recovery in 22 Nm FD-SOI CMOS Technology .” BCICTS 2023 IEEE BiCMOS
and Compound Semiconductor Integrated Circuits and Technology Symposium, 2023.
short: 'M. Iftekhar, H. Nagaraju, P. Kneuper, B. Sadiye, W. Müller, J.C. Scheytt,
in: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and
Technology Symposium, 2023.'
conference:
end_date: 2023-10-18
location: MONTEREY, CALIFORNIA, USA
start_date: 2023-10-15
date_created: 2023-09-14T11:30:36Z
date_updated: 2025-02-26T14:41:53Z
department:
- _id: '58'
language:
- iso: eng
publication: BCICTS 2023 IEEE BiCMOS and Compound Semiconductor Integrated Circuits
and Technology Symposium
related_material:
link:
- relation: contains
url: https://bcicts.org/
status: public
title: 'A 28-Gb/s 27.2 mW NRZ Full-Rate Bang-Bang Clock and Data Recovery in 22 nm
FD-SOI CMOS Technology '
type: conference_abstract
user_id: '15931'
year: '2023'
...
---
_id: '29770'
author:
- first_name: Saed
full_name: Abughannam, Saed
id: '37628'
last_name: Abughannam
- first_name: Stephan
full_name: Kruse, Stephan
id: '38254'
last_name: Kruse
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
orcid: '0000-0002-5950-6618 '
citation:
ama: 'Abughannam S, Kruse S, Iftekhar M, Scheytt JC. Design and Measurements of
a Low-power Low-Date-rate Direct-detection Wireless Receiver with Improved Co-channel
Interference Robustness. In: German Microwave Conference 2022 (GeMiC 2022).
; 2022.'
apa: Abughannam, S., Kruse, S., Iftekhar, M., & Scheytt, J. C. (2022). Design
and Measurements of a Low-power Low-Date-rate Direct-detection Wireless Receiver
with Improved Co-channel Interference Robustness. German Microwave Conference
2022 (GeMiC 2022).
bibtex: '@inproceedings{Abughannam_Kruse_Iftekhar_Scheytt_2022, place={Ulm, Germany},
title={Design and Measurements of a Low-power Low-Date-rate Direct-detection Wireless
Receiver with Improved Co-channel Interference Robustness}, booktitle={German
Microwave Conference 2022 (GeMiC 2022)}, author={Abughannam, Saed and Kruse, Stephan
and Iftekhar, Mohammed and Scheytt, J. Christoph}, year={2022} }'
chicago: Abughannam, Saed, Stephan Kruse, Mohammed Iftekhar, and J. Christoph Scheytt.
“Design and Measurements of a Low-Power Low-Date-Rate Direct-Detection Wireless
Receiver with Improved Co-Channel Interference Robustness.” In German Microwave
Conference 2022 (GeMiC 2022). Ulm, Germany, 2022.
ieee: S. Abughannam, S. Kruse, M. Iftekhar, and J. C. Scheytt, “Design and Measurements
of a Low-power Low-Date-rate Direct-detection Wireless Receiver with Improved
Co-channel Interference Robustness,” 2022.
mla: Abughannam, Saed, et al. “Design and Measurements of a Low-Power Low-Date-Rate
Direct-Detection Wireless Receiver with Improved Co-Channel Interference Robustness.”
German Microwave Conference 2022 (GeMiC 2022), 2022.
short: 'S. Abughannam, S. Kruse, M. Iftekhar, J.C. Scheytt, in: German Microwave
Conference 2022 (GeMiC 2022), Ulm, Germany, 2022.'
conference:
end_date: 2022.05.18
start_date: 2022.05.16
date_created: 2022-02-07T14:05:19Z
date_updated: 2025-02-25T06:02:05Z
department:
- _id: '58'
language:
- iso: eng
place: Ulm, Germany
publication: German Microwave Conference 2022 (GeMiC 2022)
related_material:
link:
- relation: research_paper
url: https://ieeexplore.ieee.org/document/9783610
status: public
title: Design and Measurements of a Low-power Low-Date-rate Direct-detection Wireless
Receiver with Improved Co-channel Interference Robustness
type: conference
user_id: '38254'
year: '2022'
...
---
_id: '29213'
abstract:
- lang: eng
text: This paper presents a technique to extend the frequency acquisition range
for bang-bang phase-detector-based clock and data recovery (CDR) circuits without
an additional frequency acquisition loop or lock detection circuit. The per-manent
modulation of the offset current in the CDR's integral branch enhances the acquisition
range by nearly 4 times, covering the entire tuning range of the voltage controlled
oscillator. The increase in power dissipation and the chip area are negligible.
This technique was implemented and measured in a 28 Gbps NRZ bang-bang CDR chip
to confirm the working principle. In addition to the increased acquisition range,
the CDR also surpasses jitter related specifications from the OIF CEI-28G-VSR
standard.
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Sergiy
full_name: Gudyriev, Sergiy
last_name: Gudyriev
- first_name: J. Christoph
full_name: Scheytt, J. Christoph
id: '37144'
last_name: Scheytt
citation:
ama: 'Iftekhar M, Gudyriev S, Scheytt JC. Reference-less Bang-bang CDR with Enhanced
Frequency Acquisition Range Using Static and Modulated Integral Branch Offset
Currents. In: The 2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits
and Technology Symposium. ; 2021. doi:10.1109/BCICTS50416.2021.9682207'
apa: Iftekhar, M., Gudyriev, S., & Scheytt, J. C. (2021). Reference-less Bang-bang
CDR with Enhanced Frequency Acquisition Range Using Static and Modulated Integral
Branch Offset Currents. The 2021 IEEE BiCMOS and Compound Semiconductor Integrated
Circuits and Technology Symposium. https://doi.org/10.1109/BCICTS50416.2021.9682207
bibtex: '@inproceedings{Iftekhar_Gudyriev_Scheytt_2021, title={Reference-less Bang-bang
CDR with Enhanced Frequency Acquisition Range Using Static and Modulated Integral
Branch Offset Currents}, DOI={10.1109/BCICTS50416.2021.9682207},
booktitle={The 2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits
and Technology Symposium}, author={Iftekhar, Mohammed and Gudyriev, Sergiy and
Scheytt, J. Christoph}, year={2021} }'
chicago: Iftekhar, Mohammed, Sergiy Gudyriev, and J. Christoph Scheytt. “Reference-Less
Bang-Bang CDR with Enhanced Frequency Acquisition Range Using Static and Modulated
Integral Branch Offset Currents.” In The 2021 IEEE BiCMOS and Compound Semiconductor
Integrated Circuits and Technology Symposium, 2021. https://doi.org/10.1109/BCICTS50416.2021.9682207.
ieee: 'M. Iftekhar, S. Gudyriev, and J. C. Scheytt, “Reference-less Bang-bang CDR
with Enhanced Frequency Acquisition Range Using Static and Modulated Integral
Branch Offset Currents,” 2021, doi: 10.1109/BCICTS50416.2021.9682207.'
mla: Iftekhar, Mohammed, et al. “Reference-Less Bang-Bang CDR with Enhanced Frequency
Acquisition Range Using Static and Modulated Integral Branch Offset Currents.”
The 2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology
Symposium, 2021, doi:10.1109/BCICTS50416.2021.9682207.
short: 'M. Iftekhar, S. Gudyriev, J.C. Scheytt, in: The 2021 IEEE BiCMOS and Compound
Semiconductor Integrated Circuits and Technology Symposium, 2021.'
date_created: 2022-01-11T07:23:37Z
date_updated: 2022-02-07T13:21:25Z
department:
- _id: '58'
doi: 10.1109/BCICTS50416.2021.9682207
language:
- iso: eng
publication: The 2021 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and
Technology Symposium
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/abstract/document/9682207
status: public
title: Reference-less Bang-bang CDR with Enhanced Frequency Acquisition Range Using
Static and Modulated Integral Branch Offset Currents
type: conference
user_id: '15931'
year: '2021'
...
---
_id: '24028'
abstract:
- lang: eng
text: A 28 Gbps NRZ bang-bang clock and data recovery (CDR) chip for 100G PSM4 is
presented. It exhibits an adaptable loop filter transfer function with independently
tunable proportional and integral parameters. This allows to optimize the jitter
transfer, jitter tolerance, and locking range of the CDR according to system requirements.
The CDR represents a key component for a single-chip 8-channel electronic-photonic
PSM4 transceiver. A CDR chip was manufactured in a 0.25 μm monolithic photonic
BiCMOS technology. The core chip area is 0.51 mm 2 and it dissipates 330 mW from
2.5 V and 3.3 V power supplies.
author:
- first_name: Mohammed
full_name: Iftekhar, Mohammed
id: '47944'
last_name: Iftekhar
- first_name: Sergiy
full_name: Gudyriev, Sergiy
last_name: Gudyriev
- first_name: Christoph
full_name: Scheytt, Christoph
id: '37144'
last_name: Scheytt
orcid: https://orcid.org/0000-0002-5950-6618
citation:
ama: 'Iftekhar M, Gudyriev S, Scheytt C. 28 Gbps Bang-Bang CDR for 100G PSM4 with
Independently Tunable Proportional and Integral Parameters of the Loop Filter
in 0.25 µm Photonic BiCMOS Technology. In: 2020 IEEE 20th Topical Meeting on
Silicon Monolithic Integrated Circuits in RF Systems (SiRF). IEEE; 2020. doi:10.1109/SIRF46766.2020.9040190'
apa: Iftekhar, M., Gudyriev, S., & Scheytt, C. (2020). 28 Gbps Bang-Bang CDR
for 100G PSM4 with Independently Tunable Proportional and Integral Parameters
of the Loop Filter in 0.25 µm Photonic BiCMOS Technology. 2020 IEEE 20th Topical
Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF). https://doi.org/10.1109/SIRF46766.2020.9040190
bibtex: '@inproceedings{Iftekhar_Gudyriev_Scheytt_2020, place={San Antonio, TX,
USA, USA}, title={28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable
Proportional and Integral Parameters of the Loop Filter in 0.25 µm Photonic BiCMOS
Technology}, DOI={10.1109/SIRF46766.2020.9040190},
booktitle={2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits
in RF Systems (SiRF)}, publisher={IEEE}, author={Iftekhar, Mohammed and Gudyriev,
Sergiy and Scheytt, Christoph}, year={2020} }'
chicago: 'Iftekhar, Mohammed, Sergiy Gudyriev, and Christoph Scheytt. “28 Gbps Bang-Bang
CDR for 100G PSM4 with Independently Tunable Proportional and Integral Parameters
of the Loop Filter in 0.25 Μm Photonic BiCMOS Technology.” In 2020 IEEE 20th
Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF).
San Antonio, TX, USA, USA: IEEE, 2020. https://doi.org/10.1109/SIRF46766.2020.9040190.'
ieee: 'M. Iftekhar, S. Gudyriev, and C. Scheytt, “28 Gbps Bang-Bang CDR for 100G
PSM4 with Independently Tunable Proportional and Integral Parameters of the Loop
Filter in 0.25 µm Photonic BiCMOS Technology,” 2020, doi: 10.1109/SIRF46766.2020.9040190.'
mla: Iftekhar, Mohammed, et al. “28 Gbps Bang-Bang CDR for 100G PSM4 with Independently
Tunable Proportional and Integral Parameters of the Loop Filter in 0.25 Μm Photonic
BiCMOS Technology.” 2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated
Circuits in RF Systems (SiRF), IEEE, 2020, doi:10.1109/SIRF46766.2020.9040190.
short: 'M. Iftekhar, S. Gudyriev, C. Scheytt, in: 2020 IEEE 20th Topical Meeting
on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), IEEE, San Antonio,
TX, USA, USA, 2020.'
date_created: 2021-09-09T11:50:21Z
date_updated: 2023-01-10T13:11:54Z
department:
- _id: '58'
- _id: '230'
doi: 10.1109/SIRF46766.2020.9040190
language:
- iso: eng
place: San Antonio, TX, USA, USA
publication: 2020 IEEE 20th Topical Meeting on Silicon Monolithic Integrated Circuits
in RF Systems (SiRF)
publisher: IEEE
related_material:
link:
- relation: confirmation
url: https://ieeexplore.ieee.org/document/9040190
status: public
title: 28 Gbps Bang-Bang CDR for 100G PSM4 with Independently Tunable Proportional
and Integral Parameters of the Loop Filter in 0.25 µm Photonic BiCMOS Technology
type: conference
user_id: '15931'
year: '2020'
...