@inbook{45893,
  author       = {{Hansmeier, Tim and Kenter, Tobias and Meyer, Marius and Riebler, Heinrich and Platzner, Marco and Plessl, Christian}},
  booktitle    = {{On-The-Fly Computing -- Individualized IT-services in dynamic markets}},
  editor       = {{Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}},
  pages        = {{165--182}},
  publisher    = {{Heinz Nixdorf Institut, Universität Paderborn}},
  title        = {{{Compute Centers I: Heterogeneous Execution Environments}}},
  doi          = {{10.5281/zenodo.8068642}},
  volume       = {{412}},
  year         = {{2023}},
}

@inproceedings{30971,
  author       = {{Hansmeier, Tim and Platzner, Marco}},
  booktitle    = {{Applications of Evolutionary Computation, EvoApplications 2022, Proceedings}},
  isbn         = {{9783031024610}},
  issn         = {{0302-9743}},
  location     = {{Madrid}},
  pages        = {{386--401}},
  publisher    = {{Springer International Publishing}},
  title        = {{{Integrating Safety Guarantees into the Learning Classifier System XCS}}},
  doi          = {{10.1007/978-3-031-02462-7_25}},
  volume       = {{13224}},
  year         = {{2022}},
}

@inproceedings{33253,
  author       = {{Hansmeier, Tim and Brede, Mathis and Platzner, Marco}},
  booktitle    = {{GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion}},
  location     = {{Boston, MA, USA}},
  pages        = {{2071--2079}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion}}},
  doi          = {{10.1145/3520304.3533977}},
  year         = {{2022}},
}

@inproceedings{29137,
  author       = {{Hansmeier, Tim}},
  booktitle    = {{HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}},
  location     = {{Online}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS}}},
  doi          = {{10.1145/3468044.3468055}},
  year         = {{2021}},
}

@inproceedings{21813,
  author       = {{Hansmeier, Tim and Platzner, Marco}},
  booktitle    = {{GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion}},
  isbn         = {{978-1-4503-8351-6}},
  location     = {{Lille, France}},
  pages        = {{1639–1647}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS}}},
  doi          = {{10.1145/3449726.3463159}},
  year         = {{2021}},
}

@inproceedings{17063,
  author       = {{Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}},
  isbn         = {{978-1-4503-7127-8}},
  location     = {{Cancún, Mexico}},
  pages        = {{1756--1764}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{An Adaption Mechanism for the Error Threshold of XCSF}}},
  doi          = {{10.1145/3377929.3398106}},
  year         = {{2020}},
}

@inproceedings{16363,
  author       = {{Hansmeier, Tim and Kaufmann, Paul and Platzner, Marco}},
  booktitle    = {{GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion}},
  isbn         = {{978-1-4503-7127-8}},
  location     = {{Cancún, Mexico}},
  pages        = {{125--126}},
  publisher    = {{Association for Computing Machinery (ACM)}},
  title        = {{{Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold}}},
  doi          = {{10.1145/3377929.3389968}},
  year         = {{2020}},
}

@article{12967,
  abstract     = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}},
  author       = {{Hansmeier, Tim and Platzner, Marco and Pantho, Md Jubaer Hossain and Andrews, David}},
  issn         = {{1939-8018}},
  journal      = {{Journal of Signal Processing Systems}},
  number       = {{11}},
  pages        = {{1259 -- 1272}},
  title        = {{{An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology}}},
  doi          = {{10.1007/s11265-018-1435-y}},
  volume       = {{91}},
  year         = {{2019}},
}

@misc{14546,
  author       = {{Hansmeier, Tim}},
  publisher    = {{Universität Paderborn}},
  title        = {{{Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers}}},
  year         = {{2019}},
}

@inproceedings{3373,
  abstract     = {{Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory.}},
  author       = {{Hansmeier, Tim and Platzner, Marco and Andrews, David}},
  booktitle    = {{ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications}},
  isbn         = {{9783319788890}},
  issn         = {{0302-9743}},
  location     = {{Santorini, Greece}},
  pages        = {{153--165}},
  publisher    = {{Springer International Publishing}},
  title        = {{{An FPGA/HMC-Based Accelerator for Resolution Proof Checking}}},
  doi          = {{10.1007/978-3-319-78890-6_13}},
  volume       = {{10824}},
  year         = {{2018}},
}

@misc{3580,
  author       = {{Hansmeier, Tim}},
  publisher    = {{Universität Paderborn}},
  title        = {{{An FPGA Accelerator for Checking Resolution Proofs}}},
  year         = {{2017}},
}