TY - CHAP AU - Hansmeier, Tim AU - Kenter, Tobias AU - Meyer, Marius AU - Riebler, Heinrich AU - Platzner, Marco AU - Plessl, Christian ED - Haake, Claus-Jochen ED - Meyer auf der Heide, Friedhelm ED - Platzner, Marco ED - Wachsmuth, Henning ED - Wehrheim, Heike ID - 45893 T2 - On-The-Fly Computing -- Individualized IT-services in dynamic markets TI - Compute Centers I: Heterogeneous Execution Environments VL - 412 ER - TY - CONF AU - Hansmeier, Tim AU - Platzner, Marco ID - 30971 SN - 0302-9743 T2 - Applications of Evolutionary Computation, EvoApplications 2022, Proceedings TI - Integrating Safety Guarantees into the Learning Classifier System XCS VL - 13224 ER - TY - CONF AU - Hansmeier, Tim AU - Brede, Mathis AU - Platzner, Marco ID - 33253 T2 - GECCO '22: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - XCS on Embedded Systems: An Analysis of Execution Profiles and Accelerated Classifier Deletion ER - TY - CONF AU - Hansmeier, Tim ID - 29137 T2 - HEART '21: Proceedings of the 11th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies TI - Self-aware Operation of Heterogeneous Compute Nodes using the Learning Classifier System XCS ER - TY - CONF AU - Hansmeier, Tim AU - Platzner, Marco ID - 21813 SN - 978-1-4503-8351-6 T2 - GECCO '21: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - An Experimental Comparison of Explore/Exploit Strategies for the Learning Classifier System XCS ER - TY - CONF AU - Hansmeier, Tim AU - Kaufmann, Paul AU - Platzner, Marco ID - 17063 SN - 978-1-4503-7127-8 T2 - GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - An Adaption Mechanism for the Error Threshold of XCSF ER - TY - CONF AU - Hansmeier, Tim AU - Kaufmann, Paul AU - Platzner, Marco ID - 16363 SN - 978-1-4503-7127-8 T2 - GECCO '20: Proceedings of the Genetic and Evolutionary Computation Conference Companion TI - Enabling XCSF to Cope with Dynamic Environments via an Adaptive Error Threshold ER - TY - JOUR AB - Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. AU - Hansmeier, Tim AU - Platzner, Marco AU - Pantho, Md Jubaer Hossain AU - Andrews, David ID - 12967 IS - 11 JF - Journal of Signal Processing Systems SN - 1939-8018 TI - An Accelerator for Resolution Proof Checking based on FPGA and Hybrid Memory Cube Technology VL - 91 ER - TY - GEN AU - Hansmeier, Tim ID - 14546 TI - Autonomous Operation of High-Performance Compute Nodes through Self-Awareness and Learning Classifiers ER - TY - CONF AB - Modern Boolean satisfiability solvers can emit proofs of unsatisfiability. There is substantial interest in being able to verify such proofs and also in using them for further computations. In this paper, we present an FPGA accelerator for checking resolution proofs, a popular proof format. Our accelerator exploits parallelism at the low level by implementing the basic resolution step in hardware, and at the high level by instantiating a number of parallel modules for proof checking. Since proof checking involves highly irregular memory accesses, we employ Hybrid Memory Cube technology for accelerator memory. The results show that while the accelerator is scalable and achieves speedups for all benchmark proofs, performance improvements are currently limited by the overhead of transitioning the proof into the accelerator memory. AU - Hansmeier, Tim AU - Platzner, Marco AU - Andrews, David ID - 3373 SN - 0302-9743 T2 - ARC 2018: Applied Reconfigurable Computing. Architectures, Tools, and Applications TI - An FPGA/HMC-Based Accelerator for Resolution Proof Checking VL - 10824 ER - TY - GEN AU - Hansmeier, Tim ID - 3580 TI - An FPGA Accelerator for Checking Resolution Proofs ER -