@inproceedings{54468, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{To apear in IEEE ISVLSI 2024}}, location = {{Knoxville, Tennessee, USA}}, title = {{{DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate Circuits via Check-pointing}}}, year = {{2024}}, } @inbook{45899, author = {{Boschmann, Alexander and Clausing, Lennart and Jentzsch, Felix and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{On-The-Fly Computing -- Individualized IT-services in dynamic markets}}, editor = {{Haake, Claus-Jochen and Meyer auf der Heide, Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}}, pages = {{225--236}}, publisher = {{Heinz Nixdorf Institut, Universität Paderborn}}, title = {{{Flexible Industrial Analytics on Reconfigurable Systems-On-Chip}}}, doi = {{10.5281/zenodo.8068713}}, volume = {{412}}, year = {{2023}}, } @inproceedings{21610, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021}}, location = {{Virtual}}, pages = {{27--32}}, publisher = {{ACM}}, title = {{{LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate Circuit Synthesis}}}, doi = {{https://doi.org/10.1145/3453688.3461506}}, year = {{2021}}, } @inproceedings{30908, author = {{Ghasemzadeh Mohammadi, Hassan and Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil and Rautmare, Sneha and Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk }}, booktitle = {{ Machine Learning and Principles and Practice of Knowledge Discovery in Databases}}, publisher = {{Springer}}, title = {{{FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics}}}, doi = {{https://doi.org/10.1007/978-3-030-93736-2_27}}, year = {{2021}}, } @inproceedings{16213, abstract = {{Automated synthesis of approximate circuits via functional approximations is of prominent importance to provide efficiency in energy, runtime, and chip area required to execute an application. Approximate circuits are usually obtained either through analytical approximation methods leveraging approximate transformations such as bit-width scaling or via iterative search-based optimization methods when a library of approximate components, e.g., approximate adders and multipliers, is available. For the latter, exploring the extremely large design space is challenging in terms of both computations and quality of results. While the combination of both methods can create more room for further approximations, the \textit{Design Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such a hybrid synthesis methodology that applies a low-cost analytical method followed by parallel stochastic search-based optimization. We address the DSE challenge through efficient pruning of the design space and skipping unnecessary expensive testing and/or verification steps. The experimental results reveal up to 10.57x area savings in comparison with both purely analytical or search-based approaches. }}, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020}}, location = {{Beijing, China}}, pages = {{421--426}}, publisher = {{ACM}}, title = {{{A Hybrid Synthesis Methodology for Approximate Circuits}}}, doi = {{10.1145/3386263.3406952}}, year = {{2020}}, } @inproceedings{20808, author = {{Ghasemzadeh Mohammadi, Hassan and Arshad, Rahil and Rautmare, Sneha and Manjunatha, Suraj and Kuschel, Maurice and Jentzsch, Felix Paul and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk}}, booktitle = {{2020 25th IEEE International Conference on Emerging Technologies and Factory Automation (ETFA)}}, isbn = {{9781728189567}}, title = {{{DeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep Learning on Embedded Platforms}}}, doi = {{10.1109/etfa46521.2020.9211880}}, year = {{2020}}, } @article{3585, abstract = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}}, issn = {{0026-2714}}, journal = {{Microelectronics Reliability}}, keywords = {{Approximate Computing, Framework, Pareto Front, Accuracy}}, pages = {{277--290}}, publisher = {{Elsevier}}, title = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}}, doi = {{10.1016/j.microrel.2019.04.003}}, volume = {{99}}, year = {{2019}}, } @unpublished{16853, abstract = {{State-of-the-art frameworks for generating approximate circuits usually rely on information gained through circuit synthesis and/or verification to explore the search space and to find an optimal solution. Throughout the process, a large number of circuits may be subject to processing, leading to considerable runtimes. In this work, we propose a search which takes error bounds and pre-computed impact factors into account to reduce the number of invoked synthesis and verification processes. In our experimental results, we achieved speed-ups of up to 76x while area savings remain comparable to the reference search method, simulated annealing.}}, author = {{Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Fourth Workshop on Approximate Computing (AxC 2019)}}, keywords = {{Approximate computing, parameter selection, search space exploration, verification, circuit synthesis}}, pages = {{2}}, title = {{{Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}}}, year = {{2019}}, } @inproceedings{10577, abstract = {{State-of-the-art frameworks for generating approximate circuits automatically explore the search space in an iterative process - often greedily. Synthesis and verification processes are invoked in each iteration to evaluate the found solutions and to guide the search algorithm. As a result, a large number of approximate circuits is subjected to analysis - leading to long runtimes - but only a few approximate circuits might form an acceptable solution. In this paper, we present our Jump Search (JS) method which seeks to reduce the runtime of an approximation process by reducing the number of expensive synthesis and verification steps. To reduce the runtime, JS computes impact factors for each approximation candidate in the circuit to create a selection of approximate circuits without invoking synthesis or verification processes. We denote the selection as path from which JS determines the final solution. In our experimental results, JS achieved speed-ups of up to 57x while area savings remain comparable to the reference search method, Simulated Annealing.}}, author = {{Witschen, Linus Matthias and Ghasemzadeh Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco}}, booktitle = {{Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19}}, isbn = {{9781450362528}}, keywords = {{Approximate computing, design automation, parameter selection, circuit synthesis}}, location = {{Tysons Corner, VA, USA}}, publisher = {{ACM}}, title = {{{Jump Search: A Fast Technique for the Synthesis of Approximate Circuits}}}, doi = {{10.1145/3299874.3317998}}, year = {{2019}}, } @unpublished{3586, abstract = {{Existing approaches and tools for the generation of approximate circuits often lack generality and are restricted to certain circuit types, approximation techniques, and quality assurance methods. Moreover, only few tools are publicly available. This hinders the development and evaluation of new techniques for approximating circuits and their comparison to previous approaches. In this paper, we first analyze and classify related approaches and then present CIRCA, our flexible framework for search-based approximate circuit generation. CIRCA is developed with a focus on modularity and extensibility. We present the architecture of CIRCA with its clear separation into stages and functional blocks, report on the current prototype, and show initial experiments.}}, author = {{Witschen, Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais, Muhammad and Platzner, Marco}}, booktitle = {{Third Workshop on Approximate Computing (AxC 2018)}}, keywords = {{Approximate Computing, Framework, Pareto Front, Accuracy}}, pages = {{6}}, title = {{{CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation}}}, year = {{2018}}, } @inproceedings{10598, abstract = {{Approximate computing has become a very popular design strategy that exploits error resilient computations to achieve higher performance and energy efficiency. Automated synthesis of approximate circuits is performed via functional approximation, in which various parts of the target circuit are extensively examined with a library of approximate components/transformations to trade off the functional accuracy and computational budget (i.e., power). However, as the number of possible approximate transformations increases, traditional search techniques suffer from a combinatorial explosion due to the large branching factor. In this work, we present a comprehensive framework for automated synthesis of approximate circuits from either structural or behavioral descriptions. We adapt the Monte Carlo Tree Search (MCTS), as a stochastic search technique, to deal with the large design space exploration, which enables a broader range of potential possible approximations through lightweight random simulations. The proposed framework is able to recognize the design Pareto set even with low computational budgets. Experimental results highlight the capabilities of the proposed synthesis framework by resulting in up to 61.69% energy saving while maintaining the predefined quality constraints.}}, author = {{Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}}, booktitle = {{26th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC)}}, keywords = {{Approximate computing, High-level synthesis, Accuracy, Monte-Carlo tree search, Circuit simulation}}, pages = {{219--224}}, title = {{{An MCTS-based Framework for Synthesis of Approximate Circuits}}}, doi = {{10.1109/VLSI-SoC.2018.8645026}}, year = {{2018}}, } @article{10769, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}}, journal = {{IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}}, number = {{99}}, pages = {{1--1}}, publisher = {{IEEE}}, title = {{{Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation}}}, doi = {{10.1109/TCAD.2016.2547908}}, volume = {{PP}}, year = {{2016}}, } @article{15879, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and Micheli, Giovanni De and Sanchez, Ernesto and Reorda, Matteo Sonza}}, issn = {{1550-4832}}, journal = {{ACM Journal on Emerging Technologies in Computing Systems}}, pages = {{1--13}}, title = {{{A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors}}}, doi = {{10.1145/2988234}}, year = {{2016}}, } @article{10770, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}}, journal = {{IEEE Transactions on Nanotechnology}}, number = {{6}}, pages = {{1117--1126}}, publisher = {{IEEE}}, title = {{{From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires}}}, doi = {{10.1109/TNANO.2015.2482359}}, volume = {{14}}, year = {{2015}}, } @inproceedings{10771, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza}}, booktitle = {{2015 IEEE Computer Society Annual Symposium on VLSI}}, pages = {{491--496}}, publisher = {{IEEE}}, title = {{{On the design of a fault tolerant ripple-carry adder with controllable-polarity transistors}}}, doi = {{10.1109/ISVLSI.2015.13}}, year = {{2015}}, } @inproceedings{10772, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}}, booktitle = {{Proceedings of the 2015 Design, Automation & Test in Europe Conference \& Exhibition}}, pages = {{453--458}}, publisher = {{EDA Consortium}}, title = {{{Fault modeling in controllable polarity silicon nanowire circuits}}}, doi = {{10.7873/DATE.2015.0428}}, year = {{2015}}, } @inproceedings{10773, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}}, booktitle = {{2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)}}, pages = {{163--168}}, publisher = {{IEEE}}, title = {{{Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection}}}, doi = {{10.1109/NANOARCH.2014.6880479}}, year = {{2014}}, } @inproceedings{10774, author = {{Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli, Giovanni}}, booktitle = {{2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)}}, pages = {{83--88}}, publisher = {{IEEE}}, title = {{{A fast TCAD-based methodology for Variation analysis of emerging nano-devices}}}, doi = {{10.1109/DFT.2013.6653587}}, year = {{2013}}, } @inproceedings{10775, author = {{Gaillardon, Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}}, booktitle = {{2013 14th Latin American Test Workshop-LATW}}, pages = {{1--6}}, publisher = {{IEEE}}, title = {{{Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study}}}, doi = {{10.1109/LATW.2013.6562673}}, year = {{2013}}, } @inproceedings{10776, author = {{Khatir, Mehrdad and Ghasemzadeh Mohammadi, Hassan and Ejlali, Alireza}}, booktitle = {{Computer Design (ICCD), 2010 IEEE International Conference on}}, pages = {{138--144}}, publisher = {{IEEE}}, title = {{{Sub-threshold charge recovery circuits}}}, doi = {{10.1109/ICCD.2010.5647815}}, year = {{2010}}, }