---
_id: '54468'
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. DeepApprox: Rapid Deep Learning
based Design Space Exploration of Approximate Circuits via Check-pointing. In:
To Apear in IEEE ISVLSI 2024. ; 2024.'
apa: 'Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2024). DeepApprox:
Rapid Deep Learning based Design Space Exploration of Approximate Circuits via
Check-pointing. To Apear in IEEE ISVLSI 2024. IEEE Computer Society Annual
Symposium on VLSI, Knoxville, Tennessee, USA.'
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2024, title={DeepApprox:
Rapid Deep Learning based Design Space Exploration of Approximate Circuits via
Check-pointing}, booktitle={To apear in IEEE ISVLSI 2024}, author={Awais, Muhammad
and Ghasemzadeh Mohammadi, Hassan and Platzner, Marco}, year={2024} }'
chicago: 'Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “DeepApprox:
Rapid Deep Learning Based Design Space Exploration of Approximate Circuits via
Check-Pointing.” In To Apear in IEEE ISVLSI 2024, 2024.'
ieee: 'M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “DeepApprox: Rapid Deep
Learning based Design Space Exploration of Approximate Circuits via Check-pointing,”
presented at the IEEE Computer Society Annual Symposium on VLSI, Knoxville, Tennessee,
USA, 2024.'
mla: 'Awais, Muhammad, et al. “DeepApprox: Rapid Deep Learning Based Design Space
Exploration of Approximate Circuits via Check-Pointing.” To Apear in IEEE ISVLSI
2024, 2024.'
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: To Apear in IEEE ISVLSI
2024, 2024.'
conference:
end_date: 2024-07-03
location: Knoxville, Tennessee, USA
name: IEEE Computer Society Annual Symposium on VLSI
start_date: 2024-07-01
date_created: 2024-05-28T08:14:43Z
date_updated: 2024-05-29T08:26:29Z
department:
- _id: '78'
language:
- iso: eng
publication: To apear in IEEE ISVLSI 2024
status: public
title: 'DeepApprox: Rapid Deep Learning based Design Space Exploration of Approximate
Circuits via Check-pointing'
type: conference
user_id: '64665'
year: '2024'
...
---
_id: '45899'
author:
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Lennart
full_name: Clausing, Lennart
id: '74287'
last_name: Clausing
orcid: 0000-0003-3789-6034
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Boschmann A, Clausing L, Jentzsch F, Ghasemzadeh Mohammadi H, Platzner M.
Flexible Industrial Analytics on Reconfigurable Systems-On-Chip. In: Haake C-J,
Meyer auf der Heide F, Platzner M, Wachsmuth H, Wehrheim H, eds. On-The-Fly
Computing -- Individualized IT-Services in Dynamic Markets. Vol 412. Verlagsschriftenreihe
des Heinz Nixdorf Instituts. Heinz Nixdorf Institut, Universität Paderborn; 2023:225-236.
doi:10.5281/zenodo.8068713'
apa: Boschmann, A., Clausing, L., Jentzsch, F., Ghasemzadeh Mohammadi, H., &
Platzner, M. (2023). Flexible Industrial Analytics on Reconfigurable Systems-On-Chip.
In C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, & H. Wehrheim
(Eds.), On-The-Fly Computing -- Individualized IT-services in dynamic markets
(Vol. 412, pp. 225–236). Heinz Nixdorf Institut, Universität Paderborn. https://doi.org/10.5281/zenodo.8068713
bibtex: '@inbook{Boschmann_Clausing_Jentzsch_Ghasemzadeh Mohammadi_Platzner_2023,
place={Paderborn}, series={Verlagsschriftenreihe des Heinz Nixdorf Instituts},
title={Flexible Industrial Analytics on Reconfigurable Systems-On-Chip}, volume={412},
DOI={10.5281/zenodo.8068713},
booktitle={On-The-Fly Computing -- Individualized IT-services in dynamic markets},
publisher={Heinz Nixdorf Institut, Universität Paderborn}, author={Boschmann,
Alexander and Clausing, Lennart and Jentzsch, Felix and Ghasemzadeh Mohammadi,
Hassan and Platzner, Marco}, editor={Haake, Claus-Jochen and Meyer auf der Heide,
Friedhelm and Platzner, Marco and Wachsmuth, Henning and Wehrheim, Heike}, year={2023},
pages={225–236}, collection={Verlagsschriftenreihe des Heinz Nixdorf Instituts}
}'
chicago: 'Boschmann, Alexander, Lennart Clausing, Felix Jentzsch, Hassan Ghasemzadeh
Mohammadi, and Marco Platzner. “Flexible Industrial Analytics on Reconfigurable
Systems-On-Chip.” In On-The-Fly Computing -- Individualized IT-Services in
Dynamic Markets, edited by Claus-Jochen Haake, Friedhelm Meyer auf der Heide,
Marco Platzner, Henning Wachsmuth, and Heike Wehrheim, 412:225–36. Verlagsschriftenreihe
Des Heinz Nixdorf Instituts. Paderborn: Heinz Nixdorf Institut, Universität Paderborn,
2023. https://doi.org/10.5281/zenodo.8068713.'
ieee: 'A. Boschmann, L. Clausing, F. Jentzsch, H. Ghasemzadeh Mohammadi, and M.
Platzner, “Flexible Industrial Analytics on Reconfigurable Systems-On-Chip,” in
On-The-Fly Computing -- Individualized IT-services in dynamic markets,
vol. 412, C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, and
H. Wehrheim, Eds. Paderborn: Heinz Nixdorf Institut, Universität Paderborn, 2023,
pp. 225–236.'
mla: Boschmann, Alexander, et al. “Flexible Industrial Analytics on Reconfigurable
Systems-On-Chip.” On-The-Fly Computing -- Individualized IT-Services in Dynamic
Markets, edited by Claus-Jochen Haake et al., vol. 412, Heinz Nixdorf Institut,
Universität Paderborn, 2023, pp. 225–36, doi:10.5281/zenodo.8068713.
short: 'A. Boschmann, L. Clausing, F. Jentzsch, H. Ghasemzadeh Mohammadi, M. Platzner,
in: C.-J. Haake, F. Meyer auf der Heide, M. Platzner, H. Wachsmuth, H. Wehrheim
(Eds.), On-The-Fly Computing -- Individualized IT-Services in Dynamic Markets,
Heinz Nixdorf Institut, Universität Paderborn, Paderborn, 2023, pp. 225–236.'
date_created: 2023-07-07T08:36:58Z
date_updated: 2024-05-02T10:33:26Z
ddc:
- '004'
department:
- _id: '7'
- _id: '78'
doi: 10.5281/zenodo.8068713
editor:
- first_name: Claus-Jochen
full_name: Haake, Claus-Jochen
last_name: Haake
- first_name: Friedhelm
full_name: Meyer auf der Heide, Friedhelm
last_name: Meyer auf der Heide
- first_name: Marco
full_name: Platzner, Marco
last_name: Platzner
- first_name: Henning
full_name: Wachsmuth, Henning
last_name: Wachsmuth
- first_name: Heike
full_name: Wehrheim, Heike
last_name: Wehrheim
file:
- access_level: open_access
content_type: application/pdf
creator: florida
date_created: 2023-07-07T08:36:40Z
date_updated: 2023-07-07T11:14:23Z
file_id: '45900'
file_name: T1-Chapter-SFB-Buch-Final.pdf
file_size: 468973
relation: main_file
file_date_updated: 2023-07-07T11:14:23Z
has_accepted_license: '1'
intvolume: ' 412'
language:
- iso: eng
oa: '1'
page: 225-236
place: Paderborn
project:
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
publication: On-The-Fly Computing -- Individualized IT-services in dynamic markets
publisher: Heinz Nixdorf Institut, Universität Paderborn
series_title: Verlagsschriftenreihe des Heinz Nixdorf Instituts
status: public
title: Flexible Industrial Analytics on Reconfigurable Systems-On-Chip
type: book_chapter
user_id: '398'
volume: 412
year: '2023'
...
---
_id: '21610'
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. LDAX: A Learning-based Fast
Design Space Exploration Framework for Approximate Circuit Synthesis. In: Proceedings
of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021. ACM; 2021:27-32.
doi:https://doi.org/10.1145/3453688.3461506'
apa: 'Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2021). LDAX: A Learning-based
Fast Design Space Exploration Framework for Approximate Circuit Synthesis. In
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021 (pp.
27–32). Virtual: ACM. https://doi.org/10.1145/3453688.3461506'
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2021, title={LDAX:
A Learning-based Fast Design Space Exploration Framework for Approximate Circuit
Synthesis}, DOI={https://doi.org/10.1145/3453688.3461506},
booktitle={Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021},
publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and
Platzner, Marco}, year={2021}, pages={27–32} }'
chicago: 'Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “LDAX:
A Learning-Based Fast Design Space Exploration Framework for Approximate Circuit
Synthesis.” In Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI)
2021, 27–32. ACM, 2021. https://doi.org/10.1145/3453688.3461506.'
ieee: 'M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “LDAX: A Learning-based
Fast Design Space Exploration Framework for Approximate Circuit Synthesis,” in
Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, Virtual,
2021, pp. 27–32.'
mla: 'Awais, Muhammad, et al. “LDAX: A Learning-Based Fast Design Space Exploration
Framework for Approximate Circuit Synthesis.” Proceedings of the ACM Great
Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32, doi:https://doi.org/10.1145/3453688.3461506.'
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021, ACM, 2021, pp. 27–32.'
conference:
end_date: 2021-06-25
location: Virtual
name: 31st ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021
start_date: 2021-06-22
date_created: 2021-04-13T10:17:47Z
date_updated: 2022-01-06T06:55:07Z
department:
- _id: '78'
doi: https://doi.org/10.1145/3453688.3461506
language:
- iso: eng
page: 27-32
publication: Proceedings of the ACM Great Lakes Symposium on VLSI (GLSVLSI) 2021
publication_status: published
publisher: ACM
status: public
title: 'LDAX: A Learning-based Fast Design Space Exploration Framework for Approximate
Circuit Synthesis'
type: conference
user_id: '64665'
year: '2021'
...
---
_id: '30908'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Felix
full_name: Jentzsch, Felix
id: '55631'
last_name: Jentzsch
orcid: 0000-0003-4987-5708
- first_name: Maurice
full_name: Kuschel, Maurice
last_name: Kuschel
- first_name: 'Rahil '
full_name: 'Arshad, Rahil '
last_name: Arshad
- first_name: Sneha
full_name: Rautmare, Sneha
last_name: Rautmare
- first_name: Suraj
full_name: Manjunatha, Suraj
last_name: Manjunatha
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: 'Dirk '
full_name: 'Schollbach, Dirk '
last_name: Schollbach
citation:
ama: 'Ghasemzadeh Mohammadi H, Jentzsch F, Kuschel M, et al. FLight: FPGA Acceleration
of Lightweight DNN Model Inference in Industrial Analytics. In: Machine Learning
and Principles and Practice of Knowledge Discovery in Databases. Springer;
2021. doi:https://doi.org/10.1007/978-3-030-93736-2_27'
apa: 'Ghasemzadeh Mohammadi, H., Jentzsch, F., Kuschel, M., Arshad, R., Rautmare,
S., Manjunatha, S., Platzner, M., Boschmann, A., & Schollbach, D. (2021).
FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.
Machine Learning and Principles and Practice of Knowledge Discovery in Databases.
https://doi.org/10.1007/978-3-030-93736-2_27'
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Jentzsch_Kuschel_Arshad_Rautmare_Manjunatha_Platzner_Boschmann_Schollbach_2021,
title={FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial
Analytics}, DOI={https://doi.org/10.1007/978-3-030-93736-2_27},
booktitle={ Machine Learning and Principles and Practice of Knowledge Discovery
in Databases}, publisher={Springer}, author={Ghasemzadeh Mohammadi, Hassan and
Jentzsch, Felix and Kuschel, Maurice and Arshad, Rahil and Rautmare, Sneha and
Manjunatha, Suraj and Platzner, Marco and Boschmann, Alexander and Schollbach,
Dirk }, year={2021} }'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Felix Jentzsch, Maurice Kuschel, Rahil Arshad,
Sneha Rautmare, Suraj Manjunatha, Marco Platzner, Alexander Boschmann, and Dirk Schollbach.
“FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial Analytics.”
In Machine Learning and Principles and Practice of Knowledge Discovery in
Databases. Springer, 2021. https://doi.org/10.1007/978-3-030-93736-2_27.'
ieee: 'H. Ghasemzadeh Mohammadi et al., “FLight: FPGA Acceleration of Lightweight
DNN Model Inference in Industrial Analytics,” 2021, doi: https://doi.org/10.1007/978-3-030-93736-2_27.'
mla: 'Ghasemzadeh Mohammadi, Hassan, et al. “FLight: FPGA Acceleration of Lightweight
DNN Model Inference in Industrial Analytics.” Machine Learning and Principles
and Practice of Knowledge Discovery in Databases, Springer, 2021, doi:https://doi.org/10.1007/978-3-030-93736-2_27.'
short: 'H. Ghasemzadeh Mohammadi, F. Jentzsch, M. Kuschel, R. Arshad, S. Rautmare,
S. Manjunatha, M. Platzner, A. Boschmann, D. Schollbach, in: Machine Learning
and Principles and Practice of Knowledge Discovery in Databases, Springer, 2021.'
date_created: 2022-04-18T10:16:55Z
date_updated: 2023-09-15T15:09:07Z
department:
- _id: '78'
doi: https://doi.org/10.1007/978-3-030-93736-2_27
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
publication: ' Machine Learning and Principles and Practice of Knowledge Discovery
in Databases'
publisher: Springer
status: public
title: 'FLight: FPGA Acceleration of Lightweight DNN Model Inference in Industrial
Analytics'
type: conference
user_id: '477'
year: '2021'
...
---
_id: '16213'
abstract:
- lang: eng
text: 'Automated synthesis of approximate circuits via functional approximations
is of prominent importance to provide efficiency in energy, runtime, and chip
area required to execute an application. Approximate circuits are usually obtained
either through analytical approximation methods leveraging approximate transformations
such as bit-width scaling or via iterative search-based optimization methods when
a library of approximate components, e.g., approximate adders and multipliers,
is available. For the latter, exploring the extremely large design space is challenging
in terms of both computations and quality of results. While the combination of
both methods can create more room for further approximations, the \textit{Design
Space Exploration}~(DSE) becomes a crucial issue. In this paper, we present such
a hybrid synthesis methodology that applies a low-cost analytical method followed
by parallel stochastic search-based optimization. We address the DSE challenge
through efficient pruning of the design space and skipping unnecessary expensive
testing and/or verification steps. The experimental results reveal up to 10.57x
area savings in comparison with both purely analytical or search-based approaches. '
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. A Hybrid Synthesis Methodology
for Approximate Circuits. In: Proceedings of the 30th ACM Great Lakes Symposium
on VLSI (GLSVLSI) 2020. ACM; 2020:421-426. doi:10.1145/3386263.3406952'
apa: 'Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2020). A Hybrid
Synthesis Methodology for Approximate Circuits. In Proceedings of the 30th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020 (pp. 421–426). Beijing, China:
ACM. https://doi.org/10.1145/3386263.3406952'
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2020, title={A Hybrid
Synthesis Methodology for Approximate Circuits}, DOI={10.1145/3386263.3406952},
booktitle={Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI)
2020}, publisher={ACM}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan
and Platzner, Marco}, year={2020}, pages={421–426} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “A Hybrid
Synthesis Methodology for Approximate Circuits.” In Proceedings of the 30th
ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, 421–26. ACM, 2020. https://doi.org/10.1145/3386263.3406952.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “A Hybrid Synthesis Methodology
for Approximate Circuits,” in Proceedings of the 30th ACM Great Lakes Symposium
on VLSI (GLSVLSI) 2020, Beijing, China, 2020, pp. 421–426.
mla: Awais, Muhammad, et al. “A Hybrid Synthesis Methodology for Approximate Circuits.”
Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020,
ACM, 2020, pp. 421–26, doi:10.1145/3386263.3406952.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: Proceedings of the
30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020, ACM, 2020, pp. 421–426.'
conference:
location: Beijing, China
name: ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020
date_created: 2020-03-02T15:49:38Z
date_updated: 2022-01-06T06:52:45Z
department:
- _id: '78'
doi: 10.1145/3386263.3406952
language:
- iso: eng
page: 421-426
publication: Proceedings of the 30th ACM Great Lakes Symposium on VLSI (GLSVLSI) 2020
publication_status: published
publisher: ACM
status: public
title: A Hybrid Synthesis Methodology for Approximate Circuits
type: conference
user_id: '64665'
year: '2020'
...
---
_id: '20808'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Rahil
full_name: Arshad, Rahil
last_name: Arshad
- first_name: Sneha
full_name: Rautmare, Sneha
last_name: Rautmare
- first_name: Suraj
full_name: Manjunatha, Suraj
last_name: Manjunatha
- first_name: Maurice
full_name: Kuschel, Maurice
last_name: Kuschel
- first_name: Felix Paul
full_name: Jentzsch, Felix Paul
last_name: Jentzsch
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
- first_name: Alexander
full_name: Boschmann, Alexander
last_name: Boschmann
- first_name: Dirk
full_name: Schollbach, Dirk
last_name: Schollbach
citation:
ama: 'Ghasemzadeh Mohammadi H, Arshad R, Rautmare S, et al. DeepWind: An Accurate
Wind Turbine Condition Monitoring Framework via Deep Learning on Embedded Platforms.
In: 2020 25th IEEE International Conference on Emerging Technologies and Factory
Automation (ETFA). ; 2020. doi:10.1109/etfa46521.2020.9211880'
apa: 'Ghasemzadeh Mohammadi, H., Arshad, R., Rautmare, S., Manjunatha, S., Kuschel,
M., Jentzsch, F. P., Platzner, M., Boschmann, A., & Schollbach, D. (2020).
DeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep Learning
on Embedded Platforms. 2020 25th IEEE International Conference on Emerging
Technologies and Factory Automation (ETFA). https://doi.org/10.1109/etfa46521.2020.9211880'
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Arshad_Rautmare_Manjunatha_Kuschel_Jentzsch_Platzner_Boschmann_Schollbach_2020,
title={DeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep
Learning on Embedded Platforms}, DOI={10.1109/etfa46521.2020.9211880},
booktitle={2020 25th IEEE International Conference on Emerging Technologies and
Factory Automation (ETFA)}, author={Ghasemzadeh Mohammadi, Hassan and Arshad,
Rahil and Rautmare, Sneha and Manjunatha, Suraj and Kuschel, Maurice and Jentzsch,
Felix Paul and Platzner, Marco and Boschmann, Alexander and Schollbach, Dirk},
year={2020} }'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Rahil Arshad, Sneha Rautmare, Suraj Manjunatha,
Maurice Kuschel, Felix Paul Jentzsch, Marco Platzner, Alexander Boschmann, and
Dirk Schollbach. “DeepWind: An Accurate Wind Turbine Condition Monitoring Framework
via Deep Learning on Embedded Platforms.” In 2020 25th IEEE International Conference
on Emerging Technologies and Factory Automation (ETFA), 2020. https://doi.org/10.1109/etfa46521.2020.9211880.'
ieee: 'H. Ghasemzadeh Mohammadi et al., “DeepWind: An Accurate Wind Turbine
Condition Monitoring Framework via Deep Learning on Embedded Platforms,” 2020,
doi: 10.1109/etfa46521.2020.9211880.'
mla: 'Ghasemzadeh Mohammadi, Hassan, et al. “DeepWind: An Accurate Wind Turbine
Condition Monitoring Framework via Deep Learning on Embedded Platforms.” 2020
25th IEEE International Conference on Emerging Technologies and Factory Automation
(ETFA), 2020, doi:10.1109/etfa46521.2020.9211880.'
short: 'H. Ghasemzadeh Mohammadi, R. Arshad, S. Rautmare, S. Manjunatha, M. Kuschel,
F.P. Jentzsch, M. Platzner, A. Boschmann, D. Schollbach, in: 2020 25th IEEE International
Conference on Emerging Technologies and Factory Automation (ETFA), 2020.'
date_created: 2020-12-21T10:03:49Z
date_updated: 2023-07-09T13:08:07Z
doi: 10.1109/etfa46521.2020.9211880
language:
- iso: eng
project:
- _id: '83'
name: 'SFB 901 - T1: SFB 901 -Subproject T1'
- _id: '82'
name: 'SFB 901 - T: SFB 901 - Project Area T'
- _id: '1'
grant_number: '160364472'
name: 'SFB 901: SFB 901: On-The-Fly Computing - Individualisierte IT-Dienstleistungen
in dynamischen Märkten '
publication: 2020 25th IEEE International Conference on Emerging Technologies and
Factory Automation (ETFA)
publication_identifier:
isbn:
- '9781728189567'
publication_status: published
status: public
title: 'DeepWind: An Accurate Wind Turbine Condition Monitoring Framework via Deep
Learning on Embedded Platforms'
type: conference
user_id: '398'
year: '2020'
...
---
_id: '3585'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Microelectronics Reliability. 2019;99:277-290. doi:10.1016/j.microrel.2019.04.003'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (2019). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Microelectronics Reliability, 99, 277–290. https://doi.org/10.1016/j.microrel.2019.04.003'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner_2019, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
volume={99}, DOI={10.1016/j.microrel.2019.04.003},
journal={Microelectronics Reliability}, publisher={Elsevier}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco}, year={2019}, pages={277–290} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Microelectronics Reliability 99 (2019):
277–90. https://doi.org/10.1016/j.microrel.2019.04.003.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Microelectronics Reliability, vol. 99, pp. 277–290, 2019.'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Microelectronics Reliability,
vol. 99, Elsevier, 2019, pp. 277–90, doi:10.1016/j.microrel.2019.04.003.'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Microelectronics Reliability 99 (2019) 277–290.
date_created: 2018-07-20T14:08:49Z
date_updated: 2022-01-06T06:59:25Z
department:
- _id: '78'
doi: 10.1016/j.microrel.2019.04.003
intvolume: ' 99'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: 277-290
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Microelectronics Reliability
publication_identifier:
issn:
- 0026-2714
publication_status: published
publisher: Elsevier
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: journal_article
user_id: '49051'
volume: 99
year: '2019'
...
---
_id: '16853'
abstract:
- lang: eng
text: State-of-the-art frameworks for generating approximate circuits usually rely
on information gained through circuit synthesis and/or verification to explore
the search space and to find an optimal solution. Throughout the process, a large
number of circuits may be subject to processing, leading to considerable runtimes.
In this work, we propose a search which takes error bounds and pre-computed impact
factors into account to reduce the number of invoked synthesis and verification
processes. In our experimental results, we achieved speed-ups of up to 76x while
area savings remain comparable to the reference search method, simulated annealing.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. Fourth Workshop
on Approximate Computing (AxC 2019).'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(n.d.). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
Fourth Workshop on Approximate Computing (AxC 2019).'
bibtex: '@article{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner, title={Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits}, journal={Fourth Workshop
on Approximate Computing (AxC 2019)}, author={Witschen, Linus Matthias and Ghasemzadeh
Mohammadi, Hassan and Artmann, Matthias and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” Fourth Workshop on Approximate Computing (AxC 2019), n.d.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” Fourth
Workshop on Approximate Computing (AxC 2019). .'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Fourth Workshop on Approximate Computing (AxC 2019).'
short: L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, Fourth
Workshop on Approximate Computing (AxC 2019) (n.d.).
date_created: 2020-04-25T08:02:07Z
date_updated: 2022-01-06T06:52:57Z
ddc:
- '006'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: witschen
date_created: 2020-04-25T08:00:35Z
date_updated: 2020-04-25T08:00:35Z
file_id: '16854'
file_name: AxC19_paper_3.pdf
file_size: 152806
relation: main_file
success: 1
file_date_updated: 2020-04-25T08:00:35Z
has_accepted_license: '1'
keyword:
- Approximate computing
- parameter selection
- search space exploration
- verification
- circuit synthesis
language:
- iso: eng
page: '2'
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Fourth Workshop on Approximate Computing (AxC 2019)
publication_status: accepted
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: preprint
user_id: '49051'
year: '2019'
...
---
_id: '10577'
abstract:
- lang: eng
text: "State-of-the-art frameworks for generating approximate circuits automatically
explore the search space in an iterative process - often greedily. Synthesis and
verification processes are invoked in each iteration to evaluate the found solutions
and to guide the search algorithm. As a result, a large number of approximate
circuits is subjected to analysis - leading to long runtimes - but only a few
approximate circuits might form an acceptable solution.\r\n\r\nIn this paper,
we present our Jump Search (JS) method which seeks to reduce the runtime of an
approximation process by reducing the number of expensive synthesis and verification
steps. To reduce the runtime, JS computes impact factors for each approximation
candidate in the circuit to create a selection of approximate circuits without
invoking synthesis or verification processes. We denote the selection as path
from which JS determines the final solution. In our experimental results, JS achieved
speed-ups of up to 57x while area savings remain comparable to the reference search
method, Simulated Annealing."
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Matthias
full_name: Artmann, Matthias
last_name: Artmann
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Ghasemzadeh Mohammadi H, Artmann M, Platzner M. Jump Search:
A Fast Technique for the Synthesis of Approximate Circuits. In: Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19. New York, NY,
USA: ACM; 2019. doi:10.1145/3299874.3317998'
apa: 'Witschen, L. M., Ghasemzadeh Mohammadi, H., Artmann, M., & Platzner, M.
(2019). Jump Search: A Fast Technique for the Synthesis of Approximate Circuits.
In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19.
New York, NY, USA: ACM. https://doi.org/10.1145/3299874.3317998'
bibtex: '@inproceedings{Witschen_Ghasemzadeh Mohammadi_Artmann_Platzner_2019, place={New
York, NY, USA}, title={Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits}, DOI={10.1145/3299874.3317998},
booktitle={Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI
’19}, publisher={ACM}, author={Witschen, Linus Matthias and Ghasemzadeh Mohammadi,
Hassan and Artmann, Matthias and Platzner, Marco}, year={2019} }'
chicago: 'Witschen, Linus Matthias, Hassan Ghasemzadeh Mohammadi, Matthias Artmann,
and Marco Platzner. “Jump Search: A Fast Technique for the Synthesis of Approximate
Circuits.” In Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI
’19. New York, NY, USA: ACM, 2019. https://doi.org/10.1145/3299874.3317998.'
ieee: 'L. M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, and M. Platzner, “Jump
Search: A Fast Technique for the Synthesis of Approximate Circuits,” in Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, Tysons Corner,
VA, USA, 2019.'
mla: 'Witschen, Linus Matthias, et al. “Jump Search: A Fast Technique for the Synthesis
of Approximate Circuits.” Proceedings of the 2019 on Great Lakes Symposium
on VLSI - GLSVLSI ’19, ACM, 2019, doi:10.1145/3299874.3317998.'
short: 'L.M. Witschen, H. Ghasemzadeh Mohammadi, M. Artmann, M. Platzner, in: Proceedings
of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI ’19, ACM, New York, NY,
USA, 2019.'
conference:
end_date: 2019-05-11
location: Tysons Corner, VA, USA
name: ACM Great Lakes Symposium on VLSI (GLSVLSI)
start_date: 2019-05-09
date_created: 2019-07-08T15:13:10Z
date_updated: 2022-01-06T06:50:45Z
department:
- _id: '78'
doi: 10.1145/3299874.3317998
keyword:
- Approximate computing
- design automation
- parameter selection
- circuit synthesis
language:
- iso: eng
place: New York, NY, USA
project:
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Proceedings of the 2019 on Great Lakes Symposium on VLSI - GLSVLSI '19
publication_identifier:
isbn:
- '9781450362528'
publication_status: published
publisher: ACM
status: public
title: 'Jump Search: A Fast Technique for the Synthesis of Approximate Circuits'
type: conference
user_id: '49051'
year: '2019'
...
---
_id: '3586'
abstract:
- lang: eng
text: Existing approaches and tools for the generation of approximate circuits often
lack generality and are restricted to certain circuit types, approximation techniques,
and quality assurance methods. Moreover, only few tools are publicly available.
This hinders the development and evaluation of new techniques for approximating
circuits and their comparison to previous approaches. In this paper, we first analyze
and classify related approaches and then present CIRCA, our flexible framework
for search-based approximate circuit generation. CIRCA is developed with a focus
on modularity and extensibility. We present the architecture of CIRCA with its
clear separation into stages and functional blocks, report on the current prototype,
and show initial experiments.
author:
- first_name: Linus Matthias
full_name: Witschen, Linus Matthias
id: '49051'
last_name: Witschen
- first_name: Tobias
full_name: Wiersema, Tobias
id: '3118'
last_name: Wiersema
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Witschen LM, Wiersema T, Ghasemzadeh Mohammadi H, Awais M, Platzner M. CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation.
Third Workshop on Approximate Computing (AxC 2018).'
apa: 'Witschen, L. M., Wiersema, T., Ghasemzadeh Mohammadi, H., Awais, M., &
Platzner, M. (n.d.). CIRCA: Towards a Modular and Extensible Framework for Approximate
Circuit Generation. Third Workshop on Approximate Computing (AxC 2018).'
bibtex: '@article{Witschen_Wiersema_Ghasemzadeh Mohammadi_Awais_Platzner, title={CIRCA:
Towards a Modular and Extensible Framework for Approximate Circuit Generation},
journal={Third Workshop on Approximate Computing (AxC 2018)}, author={Witschen,
Linus Matthias and Wiersema, Tobias and Ghasemzadeh Mohammadi, Hassan and Awais,
Muhammad and Platzner, Marco} }'
chicago: 'Witschen, Linus Matthias, Tobias Wiersema, Hassan Ghasemzadeh Mohammadi,
Muhammad Awais, and Marco Platzner. “CIRCA: Towards a Modular and Extensible Framework
for Approximate Circuit Generation.” Third Workshop on Approximate Computing
(AxC 2018), n.d.'
ieee: 'L. M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, and M. Platzner,
“CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit Generation,”
Third Workshop on Approximate Computing (AxC 2018). .'
mla: 'Witschen, Linus Matthias, et al. “CIRCA: Towards a Modular and Extensible
Framework for Approximate Circuit Generation.” Third Workshop on Approximate
Computing (AxC 2018).'
short: L.M. Witschen, T. Wiersema, H. Ghasemzadeh Mohammadi, M. Awais, M. Platzner,
Third Workshop on Approximate Computing (AxC 2018) (n.d.).
date_created: 2018-07-20T14:10:46Z
date_updated: 2022-01-06T06:59:26Z
ddc:
- '000'
department:
- _id: '78'
file:
- access_level: closed
content_type: application/pdf
creator: tobias82
date_created: 2018-07-20T14:13:31Z
date_updated: 2018-07-20T14:13:31Z
file_id: '3587'
file_name: WitschenWMAP2018.pdf
file_size: 285348
relation: main_file
success: 1
file_date_updated: 2018-07-20T14:13:31Z
has_accepted_license: '1'
keyword:
- Approximate Computing
- Framework
- Pareto Front
- Accuracy
language:
- iso: eng
page: '6'
project:
- _id: '12'
name: SFB 901 - Subproject B4
- _id: '1'
name: SFB 901
- _id: '3'
name: SFB 901 - Project Area B
- _id: '52'
name: Computing Resources Provided by the Paderborn Center for Parallel Computing
publication: Third Workshop on Approximate Computing (AxC 2018)
publication_status: accepted
status: public
title: 'CIRCA: Towards a Modular and Extensible Framework for Approximate Circuit
Generation'
type: preprint
user_id: '49051'
year: '2018'
...
---
_id: '10598'
abstract:
- lang: eng
text: "Approximate computing has become a very popular design\r\nstrategy that exploits
error resilient computations to achieve higher\r\nperformance and energy efficiency.
Automated synthesis of approximate\r\ncircuits is performed via functional approximation,
in which various\r\nparts of the target circuit are extensively examined with
a library\r\nof approximate components/transformations to trade off the functional\r\naccuracy
and computational budget (i.e., power). However, as the number\r\nof possible
approximate transformations increases, traditional search\r\ntechniques suffer
from a combinatorial explosion due to the large\r\nbranching factor. In this work,
we present a comprehensive framework\r\nfor automated synthesis of approximate
circuits from either structural\r\nor behavioral descriptions. We adapt the Monte
Carlo Tree Search\r\n(MCTS), as a stochastic search technique, to deal with the
large design\r\nspace exploration, which enables a broader range of potential
possible\r\napproximations through lightweight random simulations. The proposed\r\nframework
is able to recognize the design Pareto set even with low\r\ncomputational budgets.
Experimental results highlight the capabilities of\r\nthe proposed synthesis framework
by resulting in up to 61.69% energy\r\nsaving while maintaining the predefined
quality constraints."
author:
- first_name: Muhammad
full_name: Awais, Muhammad
id: '64665'
last_name: Awais
orcid: https://orcid.org/0000-0003-4148-2969
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Marco
full_name: Platzner, Marco
id: '398'
last_name: Platzner
citation:
ama: 'Awais M, Ghasemzadeh Mohammadi H, Platzner M. An MCTS-based Framework for
Synthesis of Approximate Circuits. In: 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC). ; 2018:219-224. doi:10.1109/VLSI-SoC.2018.8645026'
apa: Awais, M., Ghasemzadeh Mohammadi, H., & Platzner, M. (2018). An MCTS-based
Framework for Synthesis of Approximate Circuits. In 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC) (pp. 219–224). https://doi.org/10.1109/VLSI-SoC.2018.8645026
bibtex: '@inproceedings{Awais_Ghasemzadeh Mohammadi_Platzner_2018, title={An MCTS-based
Framework for Synthesis of Approximate Circuits}, DOI={10.1109/VLSI-SoC.2018.8645026},
booktitle={26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)}, author={Awais, Muhammad and Ghasemzadeh Mohammadi, Hassan and Platzner,
Marco}, year={2018}, pages={219–224} }'
chicago: Awais, Muhammad, Hassan Ghasemzadeh Mohammadi, and Marco Platzner. “An
MCTS-Based Framework for Synthesis of Approximate Circuits.” In 26th IFIP/IEEE
International Conference on Very Large Scale Integration (VLSI-SoC), 219–24,
2018. https://doi.org/10.1109/VLSI-SoC.2018.8645026.
ieee: M. Awais, H. Ghasemzadeh Mohammadi, and M. Platzner, “An MCTS-based Framework
for Synthesis of Approximate Circuits,” in 26th IFIP/IEEE International Conference
on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.
mla: Awais, Muhammad, et al. “An MCTS-Based Framework for Synthesis of Approximate
Circuits.” 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC), 2018, pp. 219–24, doi:10.1109/VLSI-SoC.2018.8645026.
short: 'M. Awais, H. Ghasemzadeh Mohammadi, M. Platzner, in: 26th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC), 2018, pp. 219–224.'
date_created: 2019-07-10T09:21:38Z
date_updated: 2022-01-06T06:50:46Z
department:
- _id: '78'
doi: 10.1109/VLSI-SoC.2018.8645026
keyword:
- Approximate computing
- High-level synthesis
- Accuracy
- Monte-Carlo tree search
- Circuit simulation
language:
- iso: eng
page: 219-224
publication: 26th IFIP/IEEE International Conference on Very Large Scale Integration
(VLSI-SoC)
status: public
title: An MCTS-based Framework for Synthesis of Approximate Circuits
type: conference
user_id: '64665'
year: '2018'
...
---
_id: '10769'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Efficient Statistical
Parameter Selection for Nonlinear Modeling of Process/Performance Variation. IEEE
Transactions on Computer-Aided Design of Integrated Circuits and Systems.
2016;PP(99):1-1. doi:10.1109/TCAD.2016.2547908
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2016).
Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance
Variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, PP(99), 1–1. https://doi.org/10.1109/TCAD.2016.2547908
bibtex: '@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2016, title={Efficient
Statistical Parameter Selection for Nonlinear Modeling of Process/Performance
Variation}, volume={PP}, DOI={10.1109/TCAD.2016.2547908},
number={99}, journal={IEEE Transactions on Computer-Aided Design of Integrated
Circuits and Systems}, publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan
and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2016}, pages={1–1}
}'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni
De Micheli. “Efficient Statistical Parameter Selection for Nonlinear Modeling
of Process/Performance Variation.” IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems PP, no. 99 (2016): 1–1. https://doi.org/10.1109/TCAD.2016.2547908.'
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Efficient
Statistical Parameter Selection for Nonlinear Modeling of Process/Performance
Variation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits
and Systems, vol. PP, no. 99, pp. 1–1, 2016.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “Efficient Statistical Parameter Selection
for Nonlinear Modeling of Process/Performance Variation.” IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems, vol. PP, no.
99, IEEE, 2016, pp. 1–1, doi:10.1109/TCAD.2016.2547908.
short: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions
on Computer-Aided Design of Integrated Circuits and Systems PP (2016) 1–1.
date_created: 2019-07-10T12:08:14Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/TCAD.2016.2547908
extern: '1'
issue: '99'
language:
- iso: eng
page: 1-1
publication: IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems
publisher: IEEE
status: public
title: Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance
Variation
type: journal_article
user_id: '3118'
volume: PP
year: '2016'
...
---
_id: '15879'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Jian
full_name: Zhang, Jian
last_name: Zhang
- first_name: Giovanni De
full_name: Micheli, Giovanni De
last_name: Micheli
- first_name: Ernesto
full_name: Sanchez, Ernesto
last_name: Sanchez
- first_name: Matteo Sonza
full_name: Reorda, Matteo Sonza
last_name: Reorda
citation:
ama: Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, Micheli GD, Sanchez E, Reorda
MS. A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.
ACM Journal on Emerging Technologies in Computing Systems. 2016:1-13. doi:10.1145/2988234
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., Micheli, G. D., Sanchez,
E., & Reorda, M. S. (2016). A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity
Transistors. ACM Journal on Emerging Technologies in Computing Systems,
1–13. https://doi.org/10.1145/2988234
bibtex: '@article{Ghasemzadeh Mohammadi_Gaillardon_Zhang_Micheli_Sanchez_Reorda_2016,
title={A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors},
DOI={10.1145/2988234}, journal={ACM
Journal on Emerging Technologies in Computing Systems}, author={Ghasemzadeh Mohammadi,
Hassan and Gaillardon, Pierre-Emmanuel and Zhang, Jian and Micheli, Giovanni De
and Sanchez, Ernesto and Reorda, Matteo Sonza}, year={2016}, pages={1–13} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Jian Zhang,
Giovanni De Micheli, Ernesto Sanchez, and Matteo Sonza Reorda. “A Fault-Tolerant
Ripple-Carry Adder with Controllable-Polarity Transistors.” ACM Journal on
Emerging Technologies in Computing Systems, 2016, 1–13. https://doi.org/10.1145/2988234.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. D. Micheli, E. Sanchez,
and M. S. Reorda, “A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity
Transistors,” ACM Journal on Emerging Technologies in Computing Systems,
pp. 1–13, 2016.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Fault-Tolerant Ripple-Carry Adder
with Controllable-Polarity Transistors.” ACM Journal on Emerging Technologies
in Computing Systems, 2016, pp. 1–13, doi:10.1145/2988234.
short: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G.D. Micheli, E. Sanchez,
M.S. Reorda, ACM Journal on Emerging Technologies in Computing Systems (2016)
1–13.
date_created: 2020-02-11T16:03:47Z
date_updated: 2022-01-06T06:52:39Z
doi: 10.1145/2988234
language:
- iso: eng
page: 1-13
publication: ACM Journal on Emerging Technologies in Computing Systems
publication_identifier:
issn:
- 1550-4832
publication_status: published
status: public
title: A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors
type: journal_article
user_id: '61186'
year: '2016'
...
---
_id: '10770'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. From Defect Analysis
to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires. IEEE
Transactions on Nanotechnology. 2015;14(6):1117-1126. doi:10.1109/TNANO.2015.2482359
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015).
From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon
Nanowires. IEEE Transactions on Nanotechnology, 14(6), 1117–1126.
https://doi.org/10.1109/TNANO.2015.2482359
bibtex: '@article{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={From
Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon
Nanowires}, volume={14}, DOI={10.1109/TNANO.2015.2482359},
number={6}, journal={IEEE Transactions on Nanotechnology}, publisher={IEEE}, author={Ghasemzadeh
Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015},
pages={1117–1126} }'
chicago: 'Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni
De Micheli. “From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity
Silicon Nanowires.” IEEE Transactions on Nanotechnology 14, no. 6 (2015):
1117–26. https://doi.org/10.1109/TNANO.2015.2482359.'
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “From Defect
Analysis to Gate-Level Fault Modeling of Controllable-Polarity Silicon Nanowires,”
IEEE Transactions on Nanotechnology, vol. 14, no. 6, pp. 1117–1126, 2015.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “From Defect Analysis to Gate-Level Fault
Modeling of Controllable-Polarity Silicon Nanowires.” IEEE Transactions on
Nanotechnology, vol. 14, no. 6, IEEE, 2015, pp. 1117–26, doi:10.1109/TNANO.2015.2482359.
short: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, IEEE Transactions
on Nanotechnology 14 (2015) 1117–1126.
date_created: 2019-07-10T12:08:15Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/TNANO.2015.2482359
extern: '1'
intvolume: ' 14'
issue: '6'
language:
- iso: eng
page: 1117-1126
publication: IEEE Transactions on Nanotechnology
publisher: IEEE
status: public
title: From Defect Analysis to Gate-Level Fault Modeling of Controllable-Polarity
Silicon Nanowires
type: journal_article
user_id: '3118'
volume: 14
year: '2015'
...
---
_id: '10771'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Jian
full_name: Zhang, Jian
last_name: Zhang
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
- first_name: Eduardo
full_name: Sanchez, Eduardo
last_name: Sanchez
- first_name: Matteo Sonza
full_name: Reorda, Matteo Sonza
last_name: Reorda
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Zhang J, De Micheli G, Sanchez E,
Reorda MS. On the design of a fault tolerant ripple-carry adder with controllable-polarity
transistors. In: 2015 IEEE Computer Society Annual Symposium on VLSI. IEEE;
2015:491-496. doi:10.1109/ISVLSI.2015.13'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Zhang, J., De Micheli, G., Sanchez,
E., & Reorda, M. S. (2015). On the design of a fault tolerant ripple-carry
adder with controllable-polarity transistors. In 2015 IEEE Computer Society
Annual Symposium on VLSI (pp. 491–496). IEEE. https://doi.org/10.1109/ISVLSI.2015.13
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Zhang_De Micheli_Sanchez_Reorda_2015,
title={On the design of a fault tolerant ripple-carry adder with controllable-polarity
transistors}, DOI={10.1109/ISVLSI.2015.13},
booktitle={2015 IEEE Computer Society Annual Symposium on VLSI}, publisher={IEEE},
author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Zhang,
Jian and De Micheli, Giovanni and Sanchez, Eduardo and Reorda, Matteo Sonza},
year={2015}, pages={491–496} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Jian Zhang,
Giovanni De Micheli, Eduardo Sanchez, and Matteo Sonza Reorda. “On the Design
of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.”
In 2015 IEEE Computer Society Annual Symposium on VLSI, 491–96. IEEE, 2015.
https://doi.org/10.1109/ISVLSI.2015.13.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E. Sanchez,
and M. S. Reorda, “On the design of a fault tolerant ripple-carry adder with controllable-polarity
transistors,” in 2015 IEEE Computer Society Annual Symposium on VLSI, 2015,
pp. 491–496.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “On the Design of a Fault Tolerant Ripple-Carry
Adder with Controllable-Polarity Transistors.” 2015 IEEE Computer Society Annual
Symposium on VLSI, IEEE, 2015, pp. 491–96, doi:10.1109/ISVLSI.2015.13.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, J. Zhang, G. De Micheli, E.
Sanchez, M.S. Reorda, in: 2015 IEEE Computer Society Annual Symposium on VLSI,
IEEE, 2015, pp. 491–496.'
date_created: 2019-07-10T12:08:16Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ISVLSI.2015.13
extern: '1'
language:
- iso: eng
page: 491-496
publication: 2015 IEEE Computer Society Annual Symposium on VLSI
publisher: IEEE
status: public
title: On the design of a fault tolerant ripple-carry adder with controllable-polarity
transistors
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10772'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, De Micheli G. Fault modeling in controllable
polarity silicon nanowire circuits. In: Proceedings of the 2015 Design, Automation
& Test in Europe Conference \& Exhibition. EDA Consortium; 2015:453-458.
doi:10.7873/DATE.2015.0428'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., & De Micheli, G. (2015).
Fault modeling in controllable polarity silicon nanowire circuits. In Proceedings
of the 2015 Design, Automation & Test in Europe Conference \& Exhibition
(pp. 453–458). EDA Consortium. https://doi.org/10.7873/DATE.2015.0428
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_De Micheli_2015, title={Fault
modeling in controllable polarity silicon nanowire circuits}, DOI={10.7873/DATE.2015.0428},
booktitle={Proceedings of the 2015 Design, Automation & Test in Europe Conference
\& Exhibition}, publisher={EDA Consortium}, author={Ghasemzadeh Mohammadi,
Hassan and Gaillardon, Pierre-Emmanuel and De Micheli, Giovanni}, year={2015},
pages={453–458} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, and Giovanni
De Micheli. “Fault Modeling in Controllable Polarity Silicon Nanowire Circuits.”
In Proceedings of the 2015 Design, Automation & Test in Europe Conference
\& Exhibition, 453–58. EDA Consortium, 2015. https://doi.org/10.7873/DATE.2015.0428.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, and G. De Micheli, “Fault modeling
in controllable polarity silicon nanowire circuits,” in Proceedings of the
2015 Design, Automation & Test in Europe Conference \& Exhibition,
2015, pp. 453–458.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “Fault Modeling in Controllable Polarity
Silicon Nanowire Circuits.” Proceedings of the 2015 Design, Automation &
Test in Europe Conference \& Exhibition, EDA Consortium, 2015, pp. 453–58,
doi:10.7873/DATE.2015.0428.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, G. De Micheli, in: Proceedings
of the 2015 Design, Automation & Test in Europe Conference \& Exhibition,
EDA Consortium, 2015, pp. 453–458.'
date_created: 2019-07-10T12:08:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.7873/DATE.2015.0428
extern: '1'
language:
- iso: eng
page: 453-458
publication: Proceedings of the 2015 Design, Automation & Test in Europe Conference
\& Exhibition
publisher: EDA Consortium
status: public
title: Fault modeling in controllable polarity silicon nanowire circuits
type: conference
user_id: '3118'
year: '2015'
...
---
_id: '10773'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Majid
full_name: Yazdani, Majid
last_name: Yazdani
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. Fast process
variation analysis in nano-scaled technologies using column-wise sparse parameter
selection. In: 2014 IEEE/ACM International Symposium on Nanoscale Architectures
(NANOARCH). IEEE; 2014:163-168. doi:10.1109/NANOARCH.2014.6880479'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli,
G. (2014). Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection. In 2014 IEEE/ACM International Symposium on Nanoscale
Architectures (NANOARCH) (pp. 163–168). IEEE. https://doi.org/10.1109/NANOARCH.2014.6880479
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2014,
title={Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection}, DOI={10.1109/NANOARCH.2014.6880479},
booktitle={2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)},
publisher={IEEE}, author={Ghasemzadeh Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel
and Yazdani, Majid and De Micheli, Giovanni}, year={2014}, pages={163–168} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani,
and Giovanni De Micheli. “Fast Process Variation Analysis in Nano-Scaled Technologies
Using Column-Wise Sparse Parameter Selection.” In 2014 IEEE/ACM International
Symposium on Nanoscale Architectures (NANOARCH), 163–68. IEEE, 2014. https://doi.org/10.1109/NANOARCH.2014.6880479.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli,
“Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection,” in 2014 IEEE/ACM International Symposium on Nanoscale
Architectures (NANOARCH), 2014, pp. 163–168.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “Fast Process Variation Analysis in Nano-Scaled
Technologies Using Column-Wise Sparse Parameter Selection.” 2014 IEEE/ACM International
Symposium on Nanoscale Architectures (NANOARCH), IEEE, 2014, pp. 163–68, doi:10.1109/NANOARCH.2014.6880479.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in:
2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), IEEE,
2014, pp. 163–168.'
date_created: 2019-07-10T12:10:16Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/NANOARCH.2014.6880479
extern: '1'
language:
- iso: eng
page: 163-168
publication: 2014 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH)
publisher: IEEE
status: public
title: Fast process variation analysis in nano-scaled technologies using column-wise
sparse parameter selection
type: conference
user_id: '3118'
year: '2014'
...
---
_id: '10774'
author:
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Majid
full_name: Yazdani, Majid
last_name: Yazdani
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Ghasemzadeh Mohammadi H, Gaillardon P-E, Yazdani M, De Micheli G. A fast TCAD-based
methodology for Variation analysis of emerging nano-devices. In: 2013 IEEE
International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFTS). IEEE; 2013:83-88. doi:10.1109/DFT.2013.6653587'
apa: Ghasemzadeh Mohammadi, H., Gaillardon, P.-E., Yazdani, M., & De Micheli,
G. (2013). A fast TCAD-based methodology for Variation analysis of emerging nano-devices.
In 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS) (pp. 83–88). IEEE. https://doi.org/10.1109/DFT.2013.6653587
bibtex: '@inproceedings{Ghasemzadeh Mohammadi_Gaillardon_Yazdani_De Micheli_2013,
title={A fast TCAD-based methodology for Variation analysis of emerging nano-devices},
DOI={10.1109/DFT.2013.6653587},
booktitle={2013 IEEE International Symposium on Defect and Fault Tolerance in
VLSI and Nanotechnology Systems (DFTS)}, publisher={IEEE}, author={Ghasemzadeh
Mohammadi, Hassan and Gaillardon, Pierre-Emmanuel and Yazdani, Majid and De Micheli,
Giovanni}, year={2013}, pages={83–88} }'
chicago: Ghasemzadeh Mohammadi, Hassan, Pierre-Emmanuel Gaillardon, Majid Yazdani,
and Giovanni De Micheli. “A Fast TCAD-Based Methodology for Variation Analysis
of Emerging Nano-Devices.” In 2013 IEEE International Symposium on Defect and
Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), 83–88. IEEE, 2013.
https://doi.org/10.1109/DFT.2013.6653587.
ieee: H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, and G. De Micheli,
“A fast TCAD-based methodology for Variation analysis of emerging nano-devices,”
in 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS), 2013, pp. 83–88.
mla: Ghasemzadeh Mohammadi, Hassan, et al. “A Fast TCAD-Based Methodology for Variation
Analysis of Emerging Nano-Devices.” 2013 IEEE International Symposium on Defect
and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS), IEEE, 2013,
pp. 83–88, doi:10.1109/DFT.2013.6653587.
short: 'H. Ghasemzadeh Mohammadi, P.-E. Gaillardon, M. Yazdani, G. De Micheli, in:
2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology
Systems (DFTS), IEEE, 2013, pp. 83–88.'
date_created: 2019-07-10T12:10:17Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/DFT.2013.6653587
extern: '1'
language:
- iso: eng
page: 83-88
publication: 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI
and Nanotechnology Systems (DFTS)
publisher: IEEE
status: public
title: A fast TCAD-based methodology for Variation analysis of emerging nano-devices
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '10775'
author:
- first_name: Pierre-Emmanuel
full_name: Gaillardon, Pierre-Emmanuel
last_name: Gaillardon
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Giovanni
full_name: De Micheli, Giovanni
last_name: De Micheli
citation:
ama: 'Gaillardon P-E, Ghasemzadeh Mohammadi H, De Micheli G. Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study. In:
2013 14th Latin American Test Workshop-LATW. IEEE; 2013:1-6. doi:10.1109/LATW.2013.6562673'
apa: 'Gaillardon, P.-E., Ghasemzadeh Mohammadi, H., & De Micheli, G. (2013).
Vertically-stacked silicon nanowire transistors with controllable polarity: A
robustness study. In 2013 14th Latin American Test Workshop-LATW (pp. 1–6).
IEEE. https://doi.org/10.1109/LATW.2013.6562673'
bibtex: '@inproceedings{Gaillardon_Ghasemzadeh Mohammadi_De Micheli_2013, title={Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study},
DOI={10.1109/LATW.2013.6562673},
booktitle={2013 14th Latin American Test Workshop-LATW}, publisher={IEEE}, author={Gaillardon,
Pierre-Emmanuel and Ghasemzadeh Mohammadi, Hassan and De Micheli, Giovanni}, year={2013},
pages={1–6} }'
chicago: 'Gaillardon, Pierre-Emmanuel, Hassan Ghasemzadeh Mohammadi, and Giovanni
De Micheli. “Vertically-Stacked Silicon Nanowire Transistors with Controllable
Polarity: A Robustness Study.” In 2013 14th Latin American Test Workshop-LATW,
1–6. IEEE, 2013. https://doi.org/10.1109/LATW.2013.6562673.'
ieee: 'P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, and G. De Micheli, “Vertically-stacked
silicon nanowire transistors with controllable polarity: A robustness study,”
in 2013 14th Latin American Test Workshop-LATW, 2013, pp. 1–6.'
mla: 'Gaillardon, Pierre-Emmanuel, et al. “Vertically-Stacked Silicon Nanowire Transistors
with Controllable Polarity: A Robustness Study.” 2013 14th Latin American Test
Workshop-LATW, IEEE, 2013, pp. 1–6, doi:10.1109/LATW.2013.6562673.'
short: 'P.-E. Gaillardon, H. Ghasemzadeh Mohammadi, G. De Micheli, in: 2013 14th
Latin American Test Workshop-LATW, IEEE, 2013, pp. 1–6.'
date_created: 2019-07-10T12:10:18Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/LATW.2013.6562673
extern: '1'
language:
- iso: eng
page: 1-6
publication: 2013 14th Latin American Test Workshop-LATW
publisher: IEEE
status: public
title: 'Vertically-stacked silicon nanowire transistors with controllable polarity:
A robustness study'
type: conference
user_id: '3118'
year: '2013'
...
---
_id: '10776'
author:
- first_name: Mehrdad
full_name: Khatir, Mehrdad
last_name: Khatir
- first_name: Hassan
full_name: Ghasemzadeh Mohammadi, Hassan
id: '61186'
last_name: Ghasemzadeh Mohammadi
- first_name: Alireza
full_name: Ejlali, Alireza
last_name: Ejlali
citation:
ama: 'Khatir M, Ghasemzadeh Mohammadi H, Ejlali A. Sub-threshold charge recovery
circuits. In: Computer Design (ICCD), 2010 IEEE International Conference On.
IEEE; 2010:138-144. doi:10.1109/ICCD.2010.5647815'
apa: Khatir, M., Ghasemzadeh Mohammadi, H., & Ejlali, A. (2010). Sub-threshold
charge recovery circuits. In Computer Design (ICCD), 2010 IEEE International
Conference on (pp. 138–144). IEEE. https://doi.org/10.1109/ICCD.2010.5647815
bibtex: '@inproceedings{Khatir_Ghasemzadeh Mohammadi_Ejlali_2010, title={Sub-threshold
charge recovery circuits}, DOI={10.1109/ICCD.2010.5647815},
booktitle={Computer Design (ICCD), 2010 IEEE International Conference on}, publisher={IEEE},
author={Khatir, Mehrdad and Ghasemzadeh Mohammadi, Hassan and Ejlali, Alireza},
year={2010}, pages={138–144} }'
chicago: Khatir, Mehrdad, Hassan Ghasemzadeh Mohammadi, and Alireza Ejlali. “Sub-Threshold
Charge Recovery Circuits.” In Computer Design (ICCD), 2010 IEEE International
Conference On, 138–44. IEEE, 2010. https://doi.org/10.1109/ICCD.2010.5647815.
ieee: M. Khatir, H. Ghasemzadeh Mohammadi, and A. Ejlali, “Sub-threshold charge
recovery circuits,” in Computer Design (ICCD), 2010 IEEE International Conference
on, 2010, pp. 138–144.
mla: Khatir, Mehrdad, et al. “Sub-Threshold Charge Recovery Circuits.” Computer
Design (ICCD), 2010 IEEE International Conference On, IEEE, 2010, pp. 138–44,
doi:10.1109/ICCD.2010.5647815.
short: 'M. Khatir, H. Ghasemzadeh Mohammadi, A. Ejlali, in: Computer Design (ICCD),
2010 IEEE International Conference On, IEEE, 2010, pp. 138–144.'
date_created: 2019-07-10T12:10:19Z
date_updated: 2022-01-06T06:50:50Z
department:
- _id: '78'
doi: 10.1109/ICCD.2010.5647815
extern: '1'
language:
- iso: eng
page: 138-144
publication: Computer Design (ICCD), 2010 IEEE International Conference on
publisher: IEEE
status: public
title: Sub-threshold charge recovery circuits
type: conference
user_id: '3118'
year: '2010'
...