[{"_id":"59816","language":[{"iso":"eng"}],"main_file_link":[{"open_access":"1"}],"doi":"10.1145/3728179.3728190","user_id":"16153","conference":{"end_date":"2025-05-28","name":"The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) ","start_date":"2025-05-26","location":"Kumamoto, Japan"},"author":[{"last_name":"Pape","first_name":"Gerrit","full_name":"Pape, Gerrit"},{"id":"62900","full_name":"Wintermann, Bjarne","last_name":"Wintermann","first_name":"Bjarne","orcid":"0009-0000-0856-6250"},{"id":"67601","orcid":"0009-0003-9757-988X","last_name":"Jungemann","first_name":"Linus","full_name":"Jungemann, Linus"},{"first_name":"Michael","last_name":"Lass","full_name":"Lass, Michael"},{"full_name":"Meyer, Marius","first_name":"Marius","last_name":"Meyer"},{"full_name":"Riebler, Heinrich","first_name":"Heinrich","last_name":"Riebler","id":"8961"},{"id":"16153","last_name":"Plessl","orcid":"0000-0001-5728-9982","first_name":"Christian","full_name":"Plessl, Christian"}],"title":"AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference","status":"public","year":"2025","date_updated":"2026-05-13T09:46:42Z","publication_status":"published","date_created":"2025-05-06T09:53:41Z","oa":"1","department":[{"_id":"27"}],"type":"conference","citation":{"ama":"Pape G, Wintermann B, Jungemann L, et al. AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. In: <i>Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. ; 2025. doi:<a href=\"https://doi.org/10.1145/3728179.3728190\">10.1145/3728179.3728190</a>","bibtex":"@inproceedings{Pape_Wintermann_Jungemann_Lass_Meyer_Riebler_Plessl_2025, title={AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference}, DOI={<a href=\"https://doi.org/10.1145/3728179.3728190\">10.1145/3728179.3728190</a>}, booktitle={Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies}, author={Pape, Gerrit and Wintermann, Bjarne and Jungemann, Linus and Lass, Michael and Meyer, Marius and Riebler, Heinrich and Plessl, Christian}, year={2025} }","mla":"Pape, Gerrit, et al. “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference.” <i>Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>, 2025, doi:<a href=\"https://doi.org/10.1145/3728179.3728190\">10.1145/3728179.3728190</a>.","chicago":"Pape, Gerrit, Bjarne Wintermann, Linus Jungemann, Michael Lass, Marius Meyer, Heinrich Riebler, and Christian Plessl. “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference.” In <i>Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>, 2025. <a href=\"https://doi.org/10.1145/3728179.3728190\">https://doi.org/10.1145/3728179.3728190</a>.","short":"G. Pape, B. Wintermann, L. Jungemann, M. Lass, M. Meyer, H. Riebler, C. Plessl, in: Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2025.","apa":"Pape, G., Wintermann, B., Jungemann, L., Lass, M., Meyer, M., Riebler, H., &#38; Plessl, C. (2025). AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference. <i>Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies</i>. The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) , Kumamoto, Japan. <a href=\"https://doi.org/10.1145/3728179.3728190\">https://doi.org/10.1145/3728179.3728190</a>","ieee":"G. Pape <i>et al.</i>, “AuroraFlow, an Easy-to-Use, Low-Latency FPGA Communication Solution Demonstrated on Multi-FPGA Neural Network Inference,” presented at the The International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies 2025 (HEART 2025) , Kumamoto, Japan, 2025, doi: <a href=\"https://doi.org/10.1145/3728179.3728190\">10.1145/3728179.3728190</a>."},"publication":"Proceedings of the 15th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies","project":[{"name":"EKI-App: EKI-App: Energieeffiziente Künstliche Intelligenz im Rechenzentrum durch Approximation von tiefen neuronalen Netzen für Field-Programmable Gate Arrays","_id":"296"}]}]