[{"status":"public","title":"Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations","year":"2026","author":[{"id":"63972","last_name":"Hannemann","first_name":"Kai Arne","full_name":"Hannemann, Kai Arne"},{"id":"74648","first_name":"Lars","last_name":"Luchterhandt","full_name":"Luchterhandt, Lars"},{"id":"16243","full_name":"Müller, Wolfgang","first_name":"Wolfgang","last_name":"Müller"},{"last_name":"Ulbricht","first_name":"Markus","full_name":"Ulbricht, Markus"},{"first_name":"Li","last_name":"Lu","full_name":"Lu, Li"}],"conference":{"end_date":"2026-02-24","location":"Potsdam","name":"38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen","start_date":"2026-02-22"},"date_updated":"2026-07-16T11:08:27Z","has_accepted_license":"1","_id":"63758","language":[{"iso":"eng"}],"user_id":"63972","publication":"38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen","citation":{"bibtex":"@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_2026, place={Potsdam}, title={Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations}, booktitle={38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen}, author={Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li}, year={2026} }","ama":"Hannemann KA, Luchterhandt L, Müller W, Ulbricht M, Lu L. Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations. In: <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>. ; 2026.","mla":"Hannemann, Kai Arne, et al. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.” <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>, 2026.","chicago":"Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, and Li Lu. “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations.” In <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>. Potsdam, 2026.","short":"K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, in: 38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen, Potsdam, 2026.","ieee":"K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, and L. Lu, “Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations,” presented at the 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Potsdam, 2026.","apa":"Hannemann, K. A., Luchterhandt, L., Müller, W., Ulbricht, M., &#38; Lu, L. (2026). Redesigning the TETRISC Architecture for Scalable Rocket Chip Implementations. <i>38. ITG / GMM / GI - Workshop Testmethoden Und Zuverlässigkeit von Schaltungen Und Systemen</i>. 38. ITG / GMM / GI - Workshop Testmethoden und Zuverlässigkeit von Schaltungen und Systemen, Potsdam."},"abstract":[{"text":"Resilient systems require monitoring and prediction of environmental and intrinsic conditions and the ability to adapt to changing circumstances to optimize the trade-off between performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. This paper presents the migration of TETRISC to the Rocket Chip SoC, which is freely scalable to the number of processors through parametrizable Chisel models. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis for the rapid prototyping of resilient, scalable architectures that are online configurable through software for different multicore and lock-step modes.","lang":"eng"}],"date_created":"2026-01-27T13:14:51Z","place":"Potsdam","keyword":["RISC-V","Multicore","Fault Tolerant","TETRISC","Chisel","Chipyard"],"type":"conference","department":[{"_id":"58"}]},{"publication":"29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)","citation":{"apa":"Hannemann, K. A., Luchterhandt, L., Müller, W., Ulbricht, M., Lu, L., &#38; Scheytt, J. C. (2026). TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture. <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>. 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026), Würzburg.","ieee":"K. A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, and J. C. Scheytt, “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture,” presented at the 29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026), Würzburg, 2026.","short":"K.A. Hannemann, L. Luchterhandt, W. Müller, M. Ulbricht, L. Lu, J.C. Scheytt, in: 29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026), 2026.","chicago":"Hannemann, Kai Arne, Lars Luchterhandt, Wolfgang Müller, Markus Ulbricht, Li Lu, and J. Christoph Scheytt. “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture.” In <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>, 2026.","mla":"Hannemann, Kai Arne, et al. “TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture.” <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>, 2026.","ama":"Hannemann KA, Luchterhandt L, Müller W, Ulbricht M, Lu L, Scheytt JC. TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture. In: <i>29. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen (MBMV 2026)</i>. ; 2026.","bibtex":"@inproceedings{Hannemann_Luchterhandt_Müller_Ulbricht_Lu_Scheytt_2026, title={TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture}, booktitle={29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)}, author={Hannemann, Kai Arne and Luchterhandt, Lars and Müller, Wolfgang and Ulbricht, Markus and Lu, Li and Scheytt, J. Christoph}, year={2026} }"},"abstract":[{"lang":"eng","text":"Resilient systems require monitoring and prediction of environmental and intrinsic conditions, as well as the ability to adapt to environmental hazards while optimizing the trade-off among performance, power consumption, and fault tolerance. TETRISC was introduced as a resilient multicore RISC-V processor system based on the PULPissimo platform. We introduce the migration of TETRISC to the open-source Rocket Chip SoC, targeting scalable TETRISC Chisel implementations. As such, we discuss and evaluate the main advantages and obstacles that come with the Chipyard framework for RTL simulation and FPGA synthesis, enabling rapid prototyping of resilient, scalable architectures configurable for multicore and lockstep modes."}],"date_created":"2026-05-08T17:18:10Z","type":"conference","department":[{"_id":"58"}],"year":"2026","title":"TETRISC on Rocket Chip: A Scalable and Adaptive RISC-V Multicore Architecture","status":"public","author":[{"full_name":"Hannemann, Kai Arne","first_name":"Kai Arne","last_name":"Hannemann","id":"63972"},{"first_name":"Lars","last_name":"Luchterhandt","full_name":"Luchterhandt, Lars","id":"74648"},{"full_name":"Müller, Wolfgang","last_name":"Müller","first_name":"Wolfgang","id":"16243"},{"first_name":"Markus","last_name":"Ulbricht","full_name":"Ulbricht, Markus"},{"full_name":"Lu, Li","last_name":"Lu","first_name":"Li"},{"id":"37144","orcid":"0000-0002-5950-6618 ","last_name":"Scheytt","first_name":"J. Christoph","full_name":"Scheytt, J. Christoph"}],"conference":{"end_date":"2026-03-18","start_date":"2026-03-17","name":"29. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV 2026)","location":"Würzburg"},"date_updated":"2026-07-16T11:05:58Z","language":[{"iso":"eng"}],"_id":"65595","user_id":"63972"},{"place":"Warnemünde","date_created":"2025-02-26T14:33:18Z","department":[{"_id":"58"}],"type":"conference","citation":{"mla":"Hannemann, Kai Arne, et al. “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study.” <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>, VDE Verlag, 2025.","bibtex":"@inproceedings{Hannemann_Bütün_Müller_Scheytt_2025, place={Warnemünde}, title={Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study}, booktitle={MBMV 2025 - 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen}, publisher={VDE Verlag}, author={Hannemann, Kai Arne and Bütün, Hüseyin Berke and Müller, Wolfgang and Scheytt, J. Christoph}, year={2025} }","ama":"Hannemann KA, Bütün HB, Müller W, Scheytt JC. Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study. In: <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>. VDE Verlag; 2025.","ieee":"K. A. Hannemann, H. B. Bütün, W. Müller, and J. C. Scheytt, “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study,” 2025.","apa":"Hannemann, K. A., Bütün, H. B., Müller, W., &#38; Scheytt, J. C. (2025). Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study. <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>.","chicago":"Hannemann, Kai Arne, Hüseyin Berke Bütün, Wolfgang Müller, and J. Christoph Scheytt. “Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study.” In <i>MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen</i>. Warnemünde: VDE Verlag, 2025.","short":"K.A. Hannemann, H.B. Bütün, W. Müller, J.C. Scheytt, in: MBMV 2025 - 28. Workshop Methoden Und Beschreibungssprachen Zur Modellierung Und Verifikation von Schaltungen Und Systemen, VDE Verlag, Warnemünde, 2025."},"publication":"MBMV 2025 - 28. Workshop Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen","project":[{"name":"PC2: Computing Resources Provided by the Paderborn Center for Parallel Computing","_id":"52"}],"language":[{"iso":"eng"}],"_id":"58856","publisher":"VDE Verlag","user_id":"16243","publication_identifier":{"isbn":["978-3-8007-6515-7"]},"author":[{"first_name":"Kai Arne","last_name":"Hannemann","full_name":"Hannemann, Kai Arne","id":"63972"},{"first_name":"Hüseyin Berke","last_name":"Bütün","full_name":"Bütün, Hüseyin Berke"},{"last_name":"Müller","first_name":"Wolfgang","full_name":"Müller, Wolfgang","id":"16243"},{"id":"37144","last_name":"Scheytt","first_name":"J. Christoph","orcid":"0000-0002-5950-6618 ","full_name":"Scheytt, J. Christoph"}],"status":"public","title":"Verilator and FireSim RTL Simulations on a HPC Cluster: A Comparative Case Study","year":"2025","date_updated":"2025-11-20T12:46:44Z"}]